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target-arm/neon_helper.c: Use make_float32/float32_val macros
[qemu.git] / hw / rtl8139.c
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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f
BP		 51/* For crc32 */
52#include <zlib.h>
53
87ecb68b
PB		 54#include "hw.h"
55#include "pci.h"
56#include "qemu-timer.h"
57#include "net.h"
254111ec 58#include "loader.h"
1ca4d09a 59#include "sysemu.h"
bf6b87a8 60#include "iov.h"
a41b2ff2 61
a41b2ff2
PB		 62/* debug RTL8139 card */
63//#define DEBUG_RTL8139 1
64
6cadb320
FB		 65#define PCI_FREQUENCY 33000000L
66
a41b2ff2
PB		 67/* debug RTL8139 card C+ mode only */
68//#define DEBUG_RTL8139CP 1
69
a41b2ff2
PB		 70#define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73/* arg % size for size which is a power of 2 */
74#define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
18dabfd1
BP		 77#define ETHER_ADDR_LEN 6
78#define ETHER_TYPE_LEN 2
79#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
80#define ETH_P_IP 0x0800 /* Internet Protocol packet */
81#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
82#define ETH_MTU 1500
83
84#define VLAN_TCI_LEN 2
85#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
86
6cadb320
FB		 87#if defined (DEBUG_RTL8139)
88# define DEBUG_PRINT(x) do { printf x ; } while (0)
89#else
90# define DEBUG_PRINT(x)
91#endif
92
a41b2ff2
PB		 93/* Symbolic offsets to registers. */
94enum RTL8139_registers {
95 MAC0 = 0, /* Ethernet hardware address. */
96 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 97 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
98 /* Dump Tally Conter control register(64bit). C+ mode only */
99 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 100 RxBuf = 0x30,
101 ChipCmd = 0x37,
102 RxBufPtr = 0x38,
103 RxBufAddr = 0x3A,
104 IntrMask = 0x3C,
105 IntrStatus = 0x3E,
106 TxConfig = 0x40,
107 RxConfig = 0x44,
108 Timer = 0x48, /* A general-purpose counter. */
109 RxMissed = 0x4C, /* 24 bits valid, write clears. */
110 Cfg9346 = 0x50,
111 Config0 = 0x51,
112 Config1 = 0x52,
113 FlashReg = 0x54,
114 MediaStatus = 0x58,
115 Config3 = 0x59,
116 Config4 = 0x5A, /* absent on RTL-8139A */
117 HltClk = 0x5B,
118 MultiIntr = 0x5C,
119 PCIRevisionID = 0x5E,
120 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
121 BasicModeCtrl = 0x62,
122 BasicModeStatus = 0x64,
123 NWayAdvert = 0x66,
124 NWayLPAR = 0x68,
125 NWayExpansion = 0x6A,
126 /* Undocumented registers, but required for proper operation. */
127 FIFOTMS = 0x70, /* FIFO Control and test. */
128 CSCR = 0x74, /* Chip Status and Configuration Register. */
129 PARA78 = 0x78,
130 PARA7c = 0x7c, /* Magic transceiver parameter register. */
131 Config5 = 0xD8, /* absent on RTL-8139A */
132 /* C+ mode */
133 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
134 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
135 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
136 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
137 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
138 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
139 TxThresh = 0xEC, /* Early Tx threshold */
140};
141
142enum ClearBitMasks {
143 MultiIntrClear = 0xF000,
144 ChipCmdClear = 0xE2,
145 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
146};
147
148enum ChipCmdBits {
149 CmdReset = 0x10,
150 CmdRxEnb = 0x08,
151 CmdTxEnb = 0x04,
152 RxBufEmpty = 0x01,
153};
154
155/* C+ mode */
156enum CplusCmdBits {
6cadb320
FB		 157 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
158 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
159 CPlusRxEnb = 0x0002,
160 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 161};
162
163/* Interrupt register bits, using my own meaningful names. */
164enum IntrStatusBits {
165 PCIErr = 0x8000,
166 PCSTimeout = 0x4000,
167 RxFIFOOver = 0x40,
168 RxUnderrun = 0x20,
169 RxOverflow = 0x10,
170 TxErr = 0x08,
171 TxOK = 0x04,
172 RxErr = 0x02,
173 RxOK = 0x01,
174
175 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
176};
177
178enum TxStatusBits {
179 TxHostOwns = 0x2000,
180 TxUnderrun = 0x4000,
181 TxStatOK = 0x8000,
182 TxOutOfWindow = 0x20000000,
183 TxAborted = 0x40000000,
184 TxCarrierLost = 0x80000000,
185};
186enum RxStatusBits {
187 RxMulticast = 0x8000,
188 RxPhysical = 0x4000,
189 RxBroadcast = 0x2000,
190 RxBadSymbol = 0x0020,
191 RxRunt = 0x0010,
192 RxTooLong = 0x0008,
193 RxCRCErr = 0x0004,
194 RxBadAlign = 0x0002,
195 RxStatusOK = 0x0001,
196};
197
198/* Bits in RxConfig. */
199enum rx_mode_bits {
200 AcceptErr = 0x20,
201 AcceptRunt = 0x10,
202 AcceptBroadcast = 0x08,
203 AcceptMulticast = 0x04,
204 AcceptMyPhys = 0x02,
205 AcceptAllPhys = 0x01,
206};
207
208/* Bits in TxConfig. */
209enum tx_config_bits {
210
211 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
212 TxIFGShift = 24,
213 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
214 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
215 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
216 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
217
218 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
219 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
220 TxClearAbt = (1 << 0), /* Clear abort (WO) */
221 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
222 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
223
224 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
225};
226
227
228/* Transmit Status of All Descriptors (TSAD) Register */
229enum TSAD_bits {
230 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
231 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
232 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
233 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
234 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
235 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
236 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
237 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
238 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
239 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
240 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
241 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
242 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
243 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
244 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
245 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
246};
247
248
249/* Bits in Config1 */
250enum Config1Bits {
251 Cfg1_PM_Enable = 0x01,
252 Cfg1_VPD_Enable = 0x02,
253 Cfg1_PIO = 0x04,
254 Cfg1_MMIO = 0x08,
255 LWAKE = 0x10, /* not on 8139, 8139A */
256 Cfg1_Driver_Load = 0x20,
257 Cfg1_LED0 = 0x40,
258 Cfg1_LED1 = 0x80,
259 SLEEP = (1 << 1), /* only on 8139, 8139A */
260 PWRDN = (1 << 0), /* only on 8139, 8139A */
261};
262
263/* Bits in Config3 */
264enum Config3Bits {
265 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
266 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
267 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
268 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
269 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
270 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
271 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
272 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
273};
274
275/* Bits in Config4 */
276enum Config4Bits {
277 LWPTN = (1 << 2), /* not on 8139, 8139A */
278};
279
280/* Bits in Config5 */
281enum Config5Bits {
282 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
283 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
284 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
285 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
286 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
287 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
288 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
289};
290
291enum RxConfigBits {
292 /* rx fifo threshold */
293 RxCfgFIFOShift = 13,
294 RxCfgFIFONone = (7 << RxCfgFIFOShift),
295
296 /* Max DMA burst */
297 RxCfgDMAShift = 8,
298 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
299
300 /* rx ring buffer length */
301 RxCfgRcv8K = 0,
302 RxCfgRcv16K = (1 << 11),
303 RxCfgRcv32K = (1 << 12),
304 RxCfgRcv64K = (1 << 11) | (1 << 12),
305
306 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
307 RxNoWrap = (1 << 7),
308};
309
310/* Twister tuning parameters from RealTek.
311 Completely undocumented, but required to tune bad links on some boards. */
312/*
313enum CSCRBits {
314 CSCR_LinkOKBit = 0x0400,
315 CSCR_LinkChangeBit = 0x0800,
316 CSCR_LinkStatusBits = 0x0f000,
317 CSCR_LinkDownOffCmd = 0x003c0,
318 CSCR_LinkDownCmd = 0x0f3c0,
319*/
320enum CSCRBits {
5fafdf24 321 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 322 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
323 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
324 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 325 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 326 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
327 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
328 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
329 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
330};
331
332enum Cfg9346Bits {
333 Cfg9346_Lock = 0x00,
334 Cfg9346_Unlock = 0xC0,
335};
336
337typedef enum {
338 CH_8139 = 0,
339 CH_8139_K,
340 CH_8139A,
341 CH_8139A_G,
342 CH_8139B,
343 CH_8130,
344 CH_8139C,
345 CH_8100,
346 CH_8100B_8139D,
347 CH_8101,
c227f099 348} chip_t;
a41b2ff2
PB		 349
350enum chip_flags {
351 HasHltClk = (1 << 0),
352 HasLWake = (1 << 1),
353};
354
355#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
356 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
357#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
358
6cadb320
FB		 359#define RTL8139_PCI_REVID_8139 0x10
360#define RTL8139_PCI_REVID_8139CPLUS 0x20
361
362#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
363
a41b2ff2
PB		 364/* Size is 64 * 16bit words */
365#define EEPROM_9346_ADDR_BITS 6
366#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
367#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
368
369enum Chip9346Operation
370{
371 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
372 Chip9346_op_read = 0x80, /* 10 AAAAAA */
373 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
374 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
375 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
376 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
377 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
378};
379
380enum Chip9346Mode
381{
382 Chip9346_none = 0,
383 Chip9346_enter_command_mode,
384 Chip9346_read_command,
385 Chip9346_data_read, /* from output register */
386 Chip9346_data_write, /* to input register, then to contents at specified address */
387 Chip9346_data_write_all, /* to input register, then filling contents */
388};
389
390typedef struct EEprom9346
391{
392 uint16_t contents[EEPROM_9346_SIZE];
393 int mode;
394 uint32_t tick;
395 uint8_t address;
396 uint16_t input;
397 uint16_t output;
398
399 uint8_t eecs;
400 uint8_t eesk;
401 uint8_t eedi;
402 uint8_t eedo;
403} EEprom9346;
404
6cadb320
FB		 405typedef struct RTL8139TallyCounters
406{
407 /* Tally counters */
408 uint64_t TxOk;
409 uint64_t RxOk;
410 uint64_t TxERR;
411 uint32_t RxERR;
412 uint16_t MissPkt;
413 uint16_t FAE;
414 uint32_t Tx1Col;
415 uint32_t TxMCol;
416 uint64_t RxOkPhy;
417 uint64_t RxOkBrd;
418 uint32_t RxOkMul;
419 uint16_t TxAbt;
420 uint16_t TxUndrn;
421} RTL8139TallyCounters;
422
423/* Clears all tally counters */
424static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
425
426/* Writes tally counters to specified physical memory address */
c227f099 427static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
6cadb320 428
a41b2ff2 429typedef struct RTL8139State {
efd6dd45 430 PCIDevice dev;
a41b2ff2
PB		 431 uint8_t phys[8]; /* mac address */
432 uint8_t mult[8]; /* multicast mask array */
433
6cadb320 434 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 435 uint32_t TxAddr[4]; /* TxAddr0 */
436 uint32_t RxBuf; /* Receive buffer */
437 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
438 uint32_t RxBufPtr;
439 uint32_t RxBufAddr;
440
441 uint16_t IntrStatus;
442 uint16_t IntrMask;
443
444 uint32_t TxConfig;
445 uint32_t RxConfig;
446 uint32_t RxMissed;
447
448 uint16_t CSCR;
449
450 uint8_t Cfg9346;
451 uint8_t Config0;
452 uint8_t Config1;
453 uint8_t Config3;
454 uint8_t Config4;
455 uint8_t Config5;
456
457 uint8_t clock_enabled;
458 uint8_t bChipCmdState;
459
460 uint16_t MultiIntr;
461
462 uint16_t BasicModeCtrl;
463 uint16_t BasicModeStatus;
464 uint16_t NWayAdvert;
465 uint16_t NWayLPAR;
466 uint16_t NWayExpansion;
467
468 uint16_t CpCmd;
469 uint8_t TxThresh;
470
1673ad51 471 NICState *nic;
254111ec 472 NICConf conf;
a41b2ff2
PB		 473 int rtl8139_mmio_io_addr;
474
475 /* C ring mode */
476 uint32_t currTxDesc;
477
478 /* C+ mode */
2c3891ab
AL		 479 uint32_t cplus_enabled;
480
a41b2ff2
PB		 481 uint32_t currCPlusRxDesc;
482 uint32_t currCPlusTxDesc;
483
484 uint32_t RxRingAddrLO;
485 uint32_t RxRingAddrHI;
486
487 EEprom9346 eeprom;
6cadb320
FB		 488
489 uint32_t TCTR;
490 uint32_t TimerInt;
491 int64_t TCTR_base;
492
493 /* Tally counters */
494 RTL8139TallyCounters tally_counters;
495
496 /* Non-persistent data */
497 uint8_t *cplus_txbuffer;
498 int cplus_txbuffer_len;
499 int cplus_txbuffer_offset;
500
501 /* PCI interrupt timer */
502 QEMUTimer *timer;
05447803 503 int64_t TimerExpire;
6cadb320 504
c574ba5a
AW		 505 /* Support migration to/from old versions */
506 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 507} RTL8139State;
508
05447803
FZ		 509static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
510
9596ebb7 511static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 512{
6cadb320 513 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
a41b2ff2
PB		 514
515 switch (command & Chip9346_op_mask)
516 {
517 case Chip9346_op_read:
518 {
519 eeprom->address = command & EEPROM_9346_ADDR_MASK;
520 eeprom->output = eeprom->contents[eeprom->address];
521 eeprom->eedo = 0;
522 eeprom->tick = 0;
523 eeprom->mode = Chip9346_data_read;
6cadb320
FB		 524 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
525 eeprom->address, eeprom->output));
a41b2ff2
PB		 526 }
527 break;
528
529 case Chip9346_op_write:
530 {
531 eeprom->address = command & EEPROM_9346_ADDR_MASK;
532 eeprom->input = 0;
533 eeprom->tick = 0;
534 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
6cadb320
FB		 535 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
536 eeprom->address));
a41b2ff2
PB		 537 }
538 break;
539 default:
540 eeprom->mode = Chip9346_none;
541 switch (command & Chip9346_op_ext_mask)
542 {
543 case Chip9346_op_write_enable:
6cadb320 544 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
a41b2ff2
PB		 545 break;
546 case Chip9346_op_write_all:
6cadb320 547 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
a41b2ff2
PB		 548 break;
549 case Chip9346_op_write_disable:
6cadb320 550 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
a41b2ff2
PB		 551 break;
552 }
553 break;
554 }
555}
556
9596ebb7 557static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 558{
559 int bit = eeprom->eedi?1:0;
560
561 ++ eeprom->tick;
562
6cadb320 563 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 564
565 switch (eeprom->mode)
566 {
567 case Chip9346_enter_command_mode:
568 if (bit)
569 {
570 eeprom->mode = Chip9346_read_command;
571 eeprom->tick = 0;
572 eeprom->input = 0;
6cadb320 573 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
a41b2ff2
PB		 574 }
575 break;
576
577 case Chip9346_read_command:
578 eeprom->input = (eeprom->input << 1) | (bit & 1);
579 if (eeprom->tick == 8)
580 {
581 prom9346_decode_command(eeprom, eeprom->input & 0xff);
582 }
583 break;
584
585 case Chip9346_data_read:
586 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
587 eeprom->output <<= 1;
588 if (eeprom->tick == 16)
589 {
6cadb320
FB		 590#if 1
591 // the FreeBSD drivers (rl and re) don't explicitly toggle
592 // CS between reads (or does setting Cfg9346 to 0 count too?),
593 // so we need to enter wait-for-command state here
594 eeprom->mode = Chip9346_enter_command_mode;
595 eeprom->input = 0;
596 eeprom->tick = 0;
597
598 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
599#else
600 // original behaviour
a41b2ff2
PB		 601 ++eeprom->address;
602 eeprom->address &= EEPROM_9346_ADDR_MASK;
603 eeprom->output = eeprom->contents[eeprom->address];
604 eeprom->tick = 0;
605
6cadb320
FB		 606 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
607 eeprom->address, eeprom->output));
a41b2ff2
PB		 608#endif
609 }
610 break;
611
612 case Chip9346_data_write:
613 eeprom->input = (eeprom->input << 1) | (bit & 1);
614 if (eeprom->tick == 16)
615 {
6cadb320
FB		 616 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
617 eeprom->address, eeprom->input));
618
a41b2ff2
PB		 619 eeprom->contents[eeprom->address] = eeprom->input;
620 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
621 eeprom->tick = 0;
622 eeprom->input = 0;
623 }
624 break;
625
626 case Chip9346_data_write_all:
627 eeprom->input = (eeprom->input << 1) | (bit & 1);
628 if (eeprom->tick == 16)
629 {
630 int i;
631 for (i = 0; i < EEPROM_9346_SIZE; i++)
632 {
633 eeprom->contents[i] = eeprom->input;
634 }
6cadb320
FB		 635 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
636 eeprom->input));
637
a41b2ff2
PB		 638 eeprom->mode = Chip9346_enter_command_mode;
639 eeprom->tick = 0;
640 eeprom->input = 0;
641 }
642 break;
643
644 default:
645 break;
646 }
647}
648
9596ebb7 649static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 650{
651 EEprom9346 *eeprom = &s->eeprom;
652 if (!eeprom->eecs)
653 return 0;
654
655 return eeprom->eedo;
656}
657
9596ebb7
PB		 658/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
659static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 660{
661 EEprom9346 *eeprom = &s->eeprom;
662 uint8_t old_eecs = eeprom->eecs;
663 uint8_t old_eesk = eeprom->eesk;
664
665 eeprom->eecs = eecs;
666 eeprom->eesk = eesk;
667 eeprom->eedi = eedi;
668
6cadb320
FB		 669 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
670 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 671
672 if (!old_eecs && eecs)
673 {
674 /* Synchronize start */
675 eeprom->tick = 0;
676 eeprom->input = 0;
677 eeprom->output = 0;
678 eeprom->mode = Chip9346_enter_command_mode;
679
6cadb320 680 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
a41b2ff2
PB		 681 }
682
683 if (!eecs)
684 {
6cadb320 685 DEBUG_PRINT(("=== eeprom: end access\n"));
a41b2ff2
PB		 686 return;
687 }
688
689 if (!old_eesk && eesk)
690 {
691 /* SK front rules */
692 prom9346_shift_clock(eeprom);
693 }
694}
695
696static void rtl8139_update_irq(RTL8139State *s)
697{
698 int isr;
699 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 700
80a34d67
PB		 701 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
702 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
6cadb320 703
efd6dd45 704 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 705}
706
707#define POLYNOMIAL 0x04c11db6
708
709/* From FreeBSD */
710/* XXX: optimize */
711static int compute_mcast_idx(const uint8_t *ep)
712{
713 uint32_t crc;
714 int carry, i, j;
715 uint8_t b;
716
717 crc = 0xffffffff;
718 for (i = 0; i < 6; i++) {
719 b = *ep++;
720 for (j = 0; j < 8; j++) {
721 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
722 crc <<= 1;
723 b >>= 1;
724 if (carry)
725 crc = ((crc ^ POLYNOMIAL) | carry);
726 }
727 }
728 return (crc >> 26);
729}
730
731static int rtl8139_RxWrap(RTL8139State *s)
732{
733 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
734 return (s->RxConfig & (1 << 7));
735}
736
737static int rtl8139_receiver_enabled(RTL8139State *s)
738{
739 return s->bChipCmdState & CmdRxEnb;
740}
741
742static int rtl8139_transmitter_enabled(RTL8139State *s)
743{
744 return s->bChipCmdState & CmdTxEnb;
745}
746
747static int rtl8139_cp_receiver_enabled(RTL8139State *s)
748{
749 return s->CpCmd & CPlusRxEnb;
750}
751
752static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
753{
754 return s->CpCmd & CPlusTxEnb;
755}
756
757static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
758{
759 if (s->RxBufAddr + size > s->RxBufferSize)
760 {
761 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
762
763 /* write packet data */
ccf1d14a 764 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 765 {
6cadb320 766 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
a41b2ff2
PB		 767
768 if (size > wrapped)
769 {
770 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
771 buf, size-wrapped );
772 }
773
774 /* reset buffer pointer */
775 s->RxBufAddr = 0;
776
777 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
778 buf + (size-wrapped), wrapped );
779
780 s->RxBufAddr = wrapped;
781
782 return;
783 }
784 }
785
786 /* non-wrapping path or overwrapping enabled */
787 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
788
789 s->RxBufAddr += size;
790}
791
792#define MIN_BUF_SIZE 60
c227f099 793static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 794{
795#if TARGET_PHYS_ADDR_BITS > 32
c227f099 796 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 797#else
798 return low;
799#endif
800}
801
1673ad51 802static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 803{
1673ad51 804 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 805 int avail;
806
aa1f17c1 807 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 808 if (!s->clock_enabled)
809 return 1;
810 if (!rtl8139_receiver_enabled(s))
811 return 1;
812
813 if (rtl8139_cp_receiver_enabled(s)) {
814 /* ??? Flow control not implemented in c+ mode.
815 This is a hack to work around slirp deficiencies anyway. */
816 return 1;
817 } else {
818 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
819 s->RxBufferSize);
820 return (avail == 0 || avail >= 1514);
821 }
822}
823
1673ad51 824static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 825{
1673ad51 826 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
18dabfd1 827 /* size is the length of the buffer passed to the driver */
4f1c942b 828 int size = size_;
18dabfd1 829 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 830
831 uint32_t packet_header = 0;
832
18dabfd1 833 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 834 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 835 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
836
6cadb320 837 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
a41b2ff2
PB		 838
839 /* test if board clock is stopped */
840 if (!s->clock_enabled)
841 {
6cadb320 842 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
4f1c942b 843 return -1;
a41b2ff2
PB		 844 }
845
846 /* first check if receiver is enabled */
847
848 if (!rtl8139_receiver_enabled(s))
849 {
6cadb320 850 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
4f1c942b 851 return -1;
a41b2ff2
PB		 852 }
853
854 /* XXX: check this */
855 if (s->RxConfig & AcceptAllPhys) {
856 /* promiscuous: receive all */
6cadb320 857 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
a41b2ff2
PB		 858
859 } else {
860 if (!memcmp(buf, broadcast_macaddr, 6)) {
861 /* broadcast address */
862 if (!(s->RxConfig & AcceptBroadcast))
863 {
6cadb320
FB		 864 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
865
866 /* update tally counter */
867 ++s->tally_counters.RxERR;
868
4f1c942b 869 return size;
a41b2ff2
PB		 870 }
871
872 packet_header |= RxBroadcast;
873
6cadb320
FB		 874 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
875
876 /* update tally counter */
877 ++s->tally_counters.RxOkBrd;
878
a41b2ff2
PB		 879 } else if (buf[0] & 0x01) {
880 /* multicast */
881 if (!(s->RxConfig & AcceptMulticast))
882 {
6cadb320
FB		 883 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
884
885 /* update tally counter */
886 ++s->tally_counters.RxERR;
887
4f1c942b 888 return size;
a41b2ff2
PB		 889 }
890
891 int mcast_idx = compute_mcast_idx(buf);
892
893 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
894 {
6cadb320
FB		 895 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
896
897 /* update tally counter */
898 ++s->tally_counters.RxERR;
899
4f1c942b 900 return size;
a41b2ff2
PB		 901 }
902
903 packet_header |= RxMulticast;
904
6cadb320
FB		 905 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
906
907 /* update tally counter */
908 ++s->tally_counters.RxOkMul;
909
a41b2ff2 910 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 911 s->phys[1] == buf[1] &&
912 s->phys[2] == buf[2] &&
913 s->phys[3] == buf[3] &&
914 s->phys[4] == buf[4] &&
a41b2ff2
PB		 915 s->phys[5] == buf[5]) {
916 /* match */
917 if (!(s->RxConfig & AcceptMyPhys))
918 {
6cadb320
FB		 919 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
920
921 /* update tally counter */
922 ++s->tally_counters.RxERR;
923
4f1c942b 924 return size;
a41b2ff2
PB		 925 }
926
927 packet_header |= RxPhysical;
928
6cadb320
FB		 929 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
930
931 /* update tally counter */
932 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 933
934 } else {
935
6cadb320
FB		 936 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
937
938 /* update tally counter */
939 ++s->tally_counters.RxERR;
940
4f1c942b 941 return size;
a41b2ff2
PB		 942 }
943 }
944
18dabfd1
BP		 945 /* if too small buffer, then expand it
946 * Include some tailroom in case a vlan tag is later removed. */
947 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 948 memcpy(buf1, buf, size);
18dabfd1 949 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 950 buf = buf1;
18dabfd1
BP		 951 if (size < MIN_BUF_SIZE) {
952 size = MIN_BUF_SIZE;
953 }
a41b2ff2
PB		 954 }
955
956 if (rtl8139_cp_receiver_enabled(s))
957 {
6cadb320 958 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
a41b2ff2
PB		 959
960 /* begin C+ receiver mode */
961
962/* w0 ownership flag */
963#define CP_RX_OWN (1<<31)
964/* w0 end of ring flag */
965#define CP_RX_EOR (1<<30)
966/* w0 bits 0...12 : buffer size */
967#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
968/* w1 tag available flag */
969#define CP_RX_TAVA (1<<16)
970/* w1 bits 0...15 : VLAN tag */
971#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
972/* w2 low 32bit of Rx buffer ptr */
973/* w3 high 32bit of Rx buffer ptr */
974
975 int descriptor = s->currCPlusRxDesc;
c227f099 976 target_phys_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 977
978 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
979 cplus_rx_ring_desc += 16 * descriptor;
980
6cadb320
FB		 981 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
982 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
a41b2ff2
PB		 983
984 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
985
986 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
987 rxdw0 = le32_to_cpu(val);
988 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
989 rxdw1 = le32_to_cpu(val);
990 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
991 rxbufLO = le32_to_cpu(val);
992 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
993 rxbufHI = le32_to_cpu(val);
994
6cadb320 995 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 996 descriptor,
6cadb320 997 rxdw0, rxdw1, rxbufLO, rxbufHI));
a41b2ff2
PB		 998
999 if (!(rxdw0 & CP_RX_OWN))
1000 {
6cadb320
FB		 1001 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
1002
a41b2ff2
PB		 1003 s->IntrStatus |= RxOverflow;
1004 ++s->RxMissed;
6cadb320
FB		 1005
1006 /* update tally counter */
1007 ++s->tally_counters.RxERR;
1008 ++s->tally_counters.MissPkt;
1009
a41b2ff2 1010 rtl8139_update_irq(s);
4f1c942b 1011 return size_;
a41b2ff2
PB		 1012 }
1013
1014 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1015
18dabfd1
BP		 1016 /* write VLAN info to descriptor variables. */
1017 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1018 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1019 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1020 size -= VLAN_HLEN;
1021 /* if too small buffer, use the tailroom added duing expansion */
1022 if (size < MIN_BUF_SIZE) {
1023 size = MIN_BUF_SIZE;
1024 }
1025
1026 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1027 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1028 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1029 &dot1q_buf[ETHER_TYPE_LEN]);
1030
1031 DEBUG_PRINT(("RTL8139: C+ Rx mode : extracted vlan tag with tci: "
1032 "%u\n", be16_to_cpup((uint16_t *)
1033 &dot1q_buf[ETHER_TYPE_LEN])));
1034 } else {
1035 /* reset VLAN tag flag */
1036 rxdw1 &= ~CP_RX_TAVA;
1037 }
1038
6cadb320
FB		 1039 /* TODO: scatter the packet over available receive ring descriptors space */
1040
a41b2ff2
PB		 1041 if (size+4 > rx_space)
1042 {
6cadb320
FB		 1043 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1044 descriptor, rx_space, size));
1045
a41b2ff2
PB		 1046 s->IntrStatus |= RxOverflow;
1047 ++s->RxMissed;
6cadb320
FB		 1048
1049 /* update tally counter */
1050 ++s->tally_counters.RxERR;
1051 ++s->tally_counters.MissPkt;
1052
a41b2ff2 1053 rtl8139_update_irq(s);
4f1c942b 1054 return size_;
a41b2ff2
PB		 1055 }
1056
c227f099 1057 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1058
1059 /* receive/copy to target memory */
18dabfd1
BP		 1060 if (dot1q_buf) {
1061 cpu_physical_memory_write(rx_addr, buf, 2 * ETHER_ADDR_LEN);
1062 cpu_physical_memory_write(rx_addr + 2 * ETHER_ADDR_LEN,
1063 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1064 size - 2 * ETHER_ADDR_LEN);
1065 } else {
1066 cpu_physical_memory_write(rx_addr, buf, size);
1067 }
a41b2ff2 1068
6cadb320
FB		 1069 if (s->CpCmd & CPlusRxChkSum)
1070 {
1071 /* do some packet checksumming */
1072 }
1073
a41b2ff2 1074 /* write checksum */
18dabfd1 1075 val = cpu_to_le32(crc32(0, buf, size_));
a41b2ff2
PB		 1076 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1077
1078/* first segment of received packet flag */
1079#define CP_RX_STATUS_FS (1<<29)
1080/* last segment of received packet flag */
1081#define CP_RX_STATUS_LS (1<<28)
1082/* multicast packet flag */
1083#define CP_RX_STATUS_MAR (1<<26)
1084/* physical-matching packet flag */
1085#define CP_RX_STATUS_PAM (1<<25)
1086/* broadcast packet flag */
1087#define CP_RX_STATUS_BAR (1<<24)
1088/* runt packet flag */
1089#define CP_RX_STATUS_RUNT (1<<19)
1090/* crc error flag */
1091#define CP_RX_STATUS_CRC (1<<18)
1092/* IP checksum error flag */
1093#define CP_RX_STATUS_IPF (1<<15)
1094/* UDP checksum error flag */
1095#define CP_RX_STATUS_UDPF (1<<14)
1096/* TCP checksum error flag */
1097#define CP_RX_STATUS_TCPF (1<<13)
1098
1099 /* transfer ownership to target */
1100 rxdw0 &= ~CP_RX_OWN;
1101
1102 /* set first segment bit */
1103 rxdw0 |= CP_RX_STATUS_FS;
1104
1105 /* set last segment bit */
1106 rxdw0 |= CP_RX_STATUS_LS;
1107
1108 /* set received packet type flags */
1109 if (packet_header & RxBroadcast)
1110 rxdw0 |= CP_RX_STATUS_BAR;
1111 if (packet_header & RxMulticast)
1112 rxdw0 |= CP_RX_STATUS_MAR;
1113 if (packet_header & RxPhysical)
1114 rxdw0 |= CP_RX_STATUS_PAM;
1115
1116 /* set received size */
1117 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1118 rxdw0 |= (size+4);
1119
a41b2ff2
PB		 1120 /* update ring data */
1121 val = cpu_to_le32(rxdw0);
1122 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1123 val = cpu_to_le32(rxdw1);
1124 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1125
6cadb320
FB		 1126 /* update tally counter */
1127 ++s->tally_counters.RxOk;
1128
a41b2ff2
PB		 1129 /* seek to next Rx descriptor */
1130 if (rxdw0 & CP_RX_EOR)
1131 {
1132 s->currCPlusRxDesc = 0;
1133 }
1134 else
1135 {
1136 ++s->currCPlusRxDesc;
1137 }
1138
6cadb320 1139 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
a41b2ff2
PB		 1140
1141 }
1142 else
1143 {
6cadb320
FB		 1144 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1145
a41b2ff2
PB		 1146 /* begin ring receiver mode */
1147 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1148
1149 /* if receiver buffer is empty then avail == 0 */
1150
1151 if (avail != 0 && size + 8 >= avail)
1152 {
6cadb320
FB		 1153 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1154 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1155
a41b2ff2
PB		 1156 s->IntrStatus |= RxOverflow;
1157 ++s->RxMissed;
1158 rtl8139_update_irq(s);
4f1c942b 1159 return size_;
a41b2ff2
PB		 1160 }
1161
1162 packet_header |= RxStatusOK;
1163
1164 packet_header |= (((size+4) << 16) & 0xffff0000);
1165
1166 /* write header */
1167 uint32_t val = cpu_to_le32(packet_header);
1168
1169 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1170
1171 rtl8139_write_buffer(s, buf, size);
1172
1173 /* write checksum */
ccf1d14a 1174 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1175 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1176
1177 /* correct buffer write pointer */
1178 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1179
1180 /* now we can signal we have received something */
1181
6cadb320
FB		 1182 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1183 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 1184 }
1185
1186 s->IntrStatus |= RxOK;
6cadb320
FB		 1187
1188 if (do_interrupt)
1189 {
1190 rtl8139_update_irq(s);
1191 }
4f1c942b
MM		 1192
1193 return size_;
6cadb320
FB		 1194}
1195
1673ad51 1196static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1197{
1673ad51 1198 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1199}
1200
1201static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1202{
1203 s->RxBufferSize = bufferSize;
1204 s->RxBufPtr = 0;
1205 s->RxBufAddr = 0;
1206}
1207
7f23f812 1208static void rtl8139_reset(DeviceState *d)
a41b2ff2 1209{
7f23f812 1210 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1211 int i;
1212
1213 /* restore MAC address */
254111ec 1214 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1215
1216 /* reset interrupt mask */
1217 s->IntrStatus = 0;
1218 s->IntrMask = 0;
1219
1220 rtl8139_update_irq(s);
1221
a41b2ff2
PB		 1222 /* mark all status registers as owned by host */
1223 for (i = 0; i < 4; ++i)
1224 {
1225 s->TxStatus[i] = TxHostOwns;
1226 }
1227
1228 s->currTxDesc = 0;
1229 s->currCPlusRxDesc = 0;
1230 s->currCPlusTxDesc = 0;
1231
1232 s->RxRingAddrLO = 0;
1233 s->RxRingAddrHI = 0;
1234
1235 s->RxBuf = 0;
1236
1237 rtl8139_reset_rxring(s, 8192);
1238
1239 /* ACK the reset */
1240 s->TxConfig = 0;
1241
1242#if 0
1243// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1244 s->clock_enabled = 0;
1245#else
6cadb320 1246 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1247 s->clock_enabled = 1;
1248#endif
1249
1250 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1251
1252 /* set initial state data */
1253 s->Config0 = 0x0; /* No boot ROM */
1254 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1255 s->Config3 = 0x1; /* fast back-to-back compatible */
1256 s->Config5 = 0x0;
1257
5fafdf24 1258 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1259
1260 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1261 s->cplus_enabled = 0;
1262
a41b2ff2
PB		 1263
1264// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1265// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1266 s->BasicModeCtrl = 0x1000; // autonegotiation
1267
1268 s->BasicModeStatus = 0x7809;
1269 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1270 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1271 s->BasicModeStatus |= 0x0004; /* link is up */
1272
1273 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1274 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1275 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1276
1277 /* also reset timer and disable timer interrupt */
1278 s->TCTR = 0;
1279 s->TimerInt = 0;
1280 s->TCTR_base = 0;
1281
1282 /* reset tally counters */
1283 RTL8139TallyCounters_clear(&s->tally_counters);
1284}
1285
b1d8e52e 1286static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1287{
1288 counters->TxOk = 0;
1289 counters->RxOk = 0;
1290 counters->TxERR = 0;
1291 counters->RxERR = 0;
1292 counters->MissPkt = 0;
1293 counters->FAE = 0;
1294 counters->Tx1Col = 0;
1295 counters->TxMCol = 0;
1296 counters->RxOkPhy = 0;
1297 counters->RxOkBrd = 0;
1298 counters->RxOkMul = 0;
1299 counters->TxAbt = 0;
1300 counters->TxUndrn = 0;
1301}
1302
c227f099 1303static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
6cadb320
FB		 1304{
1305 uint16_t val16;
1306 uint32_t val32;
1307 uint64_t val64;
1308
1309 val64 = cpu_to_le64(tally_counters->TxOk);
1310 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1311
1312 val64 = cpu_to_le64(tally_counters->RxOk);
1313 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1314
1315 val64 = cpu_to_le64(tally_counters->TxERR);
1316 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1317
1318 val32 = cpu_to_le32(tally_counters->RxERR);
1319 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1320
1321 val16 = cpu_to_le16(tally_counters->MissPkt);
1322 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1323
1324 val16 = cpu_to_le16(tally_counters->FAE);
1325 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1326
1327 val32 = cpu_to_le32(tally_counters->Tx1Col);
1328 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1329
1330 val32 = cpu_to_le32(tally_counters->TxMCol);
1331 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1332
1333 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1334 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1335
1336 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1337 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1338
1339 val32 = cpu_to_le32(tally_counters->RxOkMul);
1340 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1341
1342 val16 = cpu_to_le16(tally_counters->TxAbt);
1343 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1344
1345 val16 = cpu_to_le16(tally_counters->TxUndrn);
1346 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1347}
1348
1349/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1350
1351static const VMStateDescription vmstate_tally_counters = {
1352 .name = "tally_counters",
1353 .version_id = 1,
1354 .minimum_version_id = 1,
1355 .minimum_version_id_old = 1,
1356 .fields = (VMStateField []) {
1357 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1358 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1359 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1360 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1361 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1362 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1363 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1364 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1365 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1366 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1367 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1368 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1369 VMSTATE_END_OF_LIST()
1370 }
1371};
a41b2ff2
PB		 1372
1373static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1374{
1375 val &= 0xff;
1376
6cadb320 1377 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
a41b2ff2
PB		 1378
1379 if (val & CmdReset)
1380 {
6cadb320 1381 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
7f23f812 1382 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1383 }
1384 if (val & CmdRxEnb)
1385 {
6cadb320 1386 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
718da2b9
FB		 1387
1388 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1389 }
1390 if (val & CmdTxEnb)
1391 {
6cadb320 1392 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
718da2b9
FB		 1393
1394 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1395 }
1396
1397 /* mask unwriteable bits */
1398 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1399
1400 /* Deassert reset pin before next read */
1401 val &= ~CmdReset;
1402
1403 s->bChipCmdState = val;
1404}
1405
1406static int rtl8139_RxBufferEmpty(RTL8139State *s)
1407{
1408 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1409
1410 if (unread != 0)
1411 {
6cadb320 1412 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
a41b2ff2
PB		 1413 return 0;
1414 }
1415
6cadb320 1416 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
a41b2ff2
PB		 1417
1418 return 1;
1419}
1420
1421static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1422{
1423 uint32_t ret = s->bChipCmdState;
1424
1425 if (rtl8139_RxBufferEmpty(s))
1426 ret |= RxBufEmpty;
1427
6cadb320 1428 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
a41b2ff2
PB		 1429
1430 return ret;
1431}
1432
1433static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1434{
1435 val &= 0xffff;
1436
6cadb320 1437 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
a41b2ff2 1438
2c3891ab
AL		 1439 s->cplus_enabled = 1;
1440
a41b2ff2
PB		 1441 /* mask unwriteable bits */
1442 val = SET_MASKED(val, 0xff84, s->CpCmd);
1443
1444 s->CpCmd = val;
1445}
1446
1447static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1448{
1449 uint32_t ret = s->CpCmd;
1450
6cadb320
FB		 1451 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1452
1453 return ret;
1454}
1455
1456static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1457{
1458 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1459}
1460
1461static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1462{
1463 uint32_t ret = 0;
1464
1465 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1466
1467 return ret;
1468}
1469
9596ebb7 1470static int rtl8139_config_writeable(RTL8139State *s)
a41b2ff2
PB		 1471{
1472 if (s->Cfg9346 & Cfg9346_Unlock)
1473 {
1474 return 1;
1475 }
1476
6cadb320 1477 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
a41b2ff2
PB		 1478
1479 return 0;
1480}
1481
1482static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1483{
1484 val &= 0xffff;
1485
6cadb320 1486 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1487
1488 /* mask unwriteable bits */
e3d7e843 1489 uint32_t mask = 0x4cff;
a41b2ff2
PB		 1490
1491 if (1 || !rtl8139_config_writeable(s))
1492 {
1493 /* Speed setting and autonegotiation enable bits are read-only */
1494 mask |= 0x3000;
1495 /* Duplex mode setting is read-only */
1496 mask |= 0x0100;
1497 }
1498
1499 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1500
1501 s->BasicModeCtrl = val;
1502}
1503
1504static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1505{
1506 uint32_t ret = s->BasicModeCtrl;
1507
6cadb320 1508 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1509
1510 return ret;
1511}
1512
1513static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1514{
1515 val &= 0xffff;
1516
6cadb320 1517 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1518
1519 /* mask unwriteable bits */
1520 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1521
1522 s->BasicModeStatus = val;
1523}
1524
1525static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1526{
1527 uint32_t ret = s->BasicModeStatus;
1528
6cadb320 1529 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1530
1531 return ret;
1532}
1533
1534static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1535{
1536 val &= 0xff;
1537
6cadb320 1538 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
a41b2ff2
PB		 1539
1540 /* mask unwriteable bits */
1541 val = SET_MASKED(val, 0x31, s->Cfg9346);
1542
1543 uint32_t opmode = val & 0xc0;
1544 uint32_t eeprom_val = val & 0xf;
1545
1546 if (opmode == 0x80) {
1547 /* eeprom access */
1548 int eecs = (eeprom_val & 0x08)?1:0;
1549 int eesk = (eeprom_val & 0x04)?1:0;
1550 int eedi = (eeprom_val & 0x02)?1:0;
1551 prom9346_set_wire(s, eecs, eesk, eedi);
1552 } else if (opmode == 0x40) {
1553 /* Reset. */
1554 val = 0;
7f23f812 1555 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1556 }
1557
1558 s->Cfg9346 = val;
1559}
1560
1561static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1562{
1563 uint32_t ret = s->Cfg9346;
1564
1565 uint32_t opmode = ret & 0xc0;
1566
1567 if (opmode == 0x80)
1568 {
1569 /* eeprom access */
1570 int eedo = prom9346_get_wire(s);
1571 if (eedo)
1572 {
1573 ret |= 0x01;
1574 }
1575 else
1576 {
1577 ret &= ~0x01;
1578 }
1579 }
1580
6cadb320 1581 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
a41b2ff2
PB		 1582
1583 return ret;
1584}
1585
1586static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1587{
1588 val &= 0xff;
1589
6cadb320 1590 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
a41b2ff2
PB		 1591
1592 if (!rtl8139_config_writeable(s))
1593 return;
1594
1595 /* mask unwriteable bits */
1596 val = SET_MASKED(val, 0xf8, s->Config0);
1597
1598 s->Config0 = val;
1599}
1600
1601static uint32_t rtl8139_Config0_read(RTL8139State *s)
1602{
1603 uint32_t ret = s->Config0;
1604
6cadb320 1605 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
a41b2ff2
PB		 1606
1607 return ret;
1608}
1609
1610static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1611{
1612 val &= 0xff;
1613
6cadb320 1614 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
a41b2ff2
PB		 1615
1616 if (!rtl8139_config_writeable(s))
1617 return;
1618
1619 /* mask unwriteable bits */
1620 val = SET_MASKED(val, 0xC, s->Config1);
1621
1622 s->Config1 = val;
1623}
1624
1625static uint32_t rtl8139_Config1_read(RTL8139State *s)
1626{
1627 uint32_t ret = s->Config1;
1628
6cadb320 1629 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
a41b2ff2
PB		 1630
1631 return ret;
1632}
1633
1634static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1635{
1636 val &= 0xff;
1637
6cadb320 1638 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
a41b2ff2
PB		 1639
1640 if (!rtl8139_config_writeable(s))
1641 return;
1642
1643 /* mask unwriteable bits */
1644 val = SET_MASKED(val, 0x8F, s->Config3);
1645
1646 s->Config3 = val;
1647}
1648
1649static uint32_t rtl8139_Config3_read(RTL8139State *s)
1650{
1651 uint32_t ret = s->Config3;
1652
6cadb320 1653 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
a41b2ff2
PB		 1654
1655 return ret;
1656}
1657
1658static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1659{
1660 val &= 0xff;
1661
6cadb320 1662 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
a41b2ff2
PB		 1663
1664 if (!rtl8139_config_writeable(s))
1665 return;
1666
1667 /* mask unwriteable bits */
1668 val = SET_MASKED(val, 0x0a, s->Config4);
1669
1670 s->Config4 = val;
1671}
1672
1673static uint32_t rtl8139_Config4_read(RTL8139State *s)
1674{
1675 uint32_t ret = s->Config4;
1676
6cadb320 1677 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
a41b2ff2
PB		 1678
1679 return ret;
1680}
1681
1682static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1683{
1684 val &= 0xff;
1685
6cadb320 1686 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
a41b2ff2
PB		 1687
1688 /* mask unwriteable bits */
1689 val = SET_MASKED(val, 0x80, s->Config5);
1690
1691 s->Config5 = val;
1692}
1693
1694static uint32_t rtl8139_Config5_read(RTL8139State *s)
1695{
1696 uint32_t ret = s->Config5;
1697
6cadb320 1698 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
a41b2ff2
PB		 1699
1700 return ret;
1701}
1702
1703static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1704{
1705 if (!rtl8139_transmitter_enabled(s))
1706 {
6cadb320 1707 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1708 return;
1709 }
1710
6cadb320 1711 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1712
1713 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1714
1715 s->TxConfig = val;
1716}
1717
1718static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1719{
6cadb320
FB		 1720 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1721
1722 uint32_t tc = s->TxConfig;
1723 tc &= 0xFFFFFF00;
1724 tc |= (val & 0x000000FF);
1725 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1726}
1727
1728static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1729{
1730 uint32_t ret = s->TxConfig;
1731
6cadb320 1732 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
a41b2ff2
PB		 1733
1734 return ret;
1735}
1736
1737static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1738{
6cadb320 1739 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1740
1741 /* mask unwriteable bits */
1742 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1743
1744 s->RxConfig = val;
1745
1746 /* reset buffer size and read/write pointers */
1747 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1748
6cadb320 1749 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
a41b2ff2
PB		 1750}
1751
1752static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1753{
1754 uint32_t ret = s->RxConfig;
1755
6cadb320 1756 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
a41b2ff2
PB		 1757
1758 return ret;
1759}
1760
bf6b87a8
BP		 1761static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1762 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1763{
bf6b87a8
BP		 1764 struct iovec *iov = NULL;
1765
718da2b9
FB		 1766 if (!size)
1767 {
1768 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1769 return;
1770 }
1771
bf6b87a8
BP		 1772 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1773 iov = (struct iovec[3]) {
1774 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1775 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1776 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1777 .iov_len = size - ETHER_ADDR_LEN * 2 },
1778 };
1779 }
1780
718da2b9
FB		 1781 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1782 {
bf6b87a8
BP		 1783 size_t buf2_size;
1784 uint8_t *buf2;
1785
1786 if (iov) {
1787 buf2_size = iov_size(iov, 3);
1788 buf2 = qemu_malloc(buf2_size);
1789 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1790 buf = buf2;
1791 }
1792
718da2b9 1793 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1673ad51 1794 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
bf6b87a8
BP		 1795
1796 if (iov) {
1797 qemu_free(buf2);
1798 }
718da2b9
FB		 1799 }
1800 else
1801 {
bf6b87a8
BP		 1802 if (iov) {
1803 qemu_sendv_packet(&s->nic->nc, iov, 3);
1804 } else {
1805 qemu_send_packet(&s->nic->nc, buf, size);
1806 }
718da2b9
FB		 1807 }
1808}
1809
a41b2ff2
PB		 1810static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1811{
1812 if (!rtl8139_transmitter_enabled(s))
1813 {
6cadb320
FB		 1814 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1815 descriptor));
a41b2ff2
PB		 1816 return 0;
1817 }
1818
1819 if (s->TxStatus[descriptor] & TxHostOwns)
1820 {
6cadb320
FB		 1821 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1822 descriptor, s->TxStatus[descriptor]));
a41b2ff2
PB		 1823 return 0;
1824 }
1825
6cadb320 1826 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
a41b2ff2
PB		 1827
1828 int txsize = s->TxStatus[descriptor] & 0x1fff;
1829 uint8_t txbuffer[0x2000];
1830
6cadb320
FB		 1831 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1832 txsize, s->TxAddr[descriptor]));
a41b2ff2 1833
6cadb320 1834 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1835
1836 /* Mark descriptor as transferred */
1837 s->TxStatus[descriptor] |= TxHostOwns;
1838 s->TxStatus[descriptor] |= TxStatOK;
1839
bf6b87a8 1840 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320
FB		 1841
1842 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
a41b2ff2
PB		 1843
1844 /* update interrupt */
1845 s->IntrStatus |= TxOK;
1846 rtl8139_update_irq(s);
1847
1848 return 1;
1849}
1850
718da2b9
FB		 1851/* structures and macros for task offloading */
1852typedef struct ip_header
1853{
1854 uint8_t ip_ver_len; /* version and header length */
1855 uint8_t ip_tos; /* type of service */
1856 uint16_t ip_len; /* total length */
1857 uint16_t ip_id; /* identification */
1858 uint16_t ip_off; /* fragment offset field */
1859 uint8_t ip_ttl; /* time to live */
1860 uint8_t ip_p; /* protocol */
1861 uint16_t ip_sum; /* checksum */
1862 uint32_t ip_src,ip_dst; /* source and dest address */
1863} ip_header;
1864
1865#define IP_HEADER_VERSION_4 4
1866#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1867#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1868
1869typedef struct tcp_header
1870{
1871 uint16_t th_sport; /* source port */
1872 uint16_t th_dport; /* destination port */
1873 uint32_t th_seq; /* sequence number */
1874 uint32_t th_ack; /* acknowledgement number */
1875 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1876 uint16_t th_win; /* window */
1877 uint16_t th_sum; /* checksum */
1878 uint16_t th_urp; /* urgent pointer */
1879} tcp_header;
1880
1881typedef struct udp_header
1882{
1883 uint16_t uh_sport; /* source port */
1884 uint16_t uh_dport; /* destination port */
1885 uint16_t uh_ulen; /* udp length */
1886 uint16_t uh_sum; /* udp checksum */
1887} udp_header;
1888
1889typedef struct ip_pseudo_header
1890{
1891 uint32_t ip_src;
1892 uint32_t ip_dst;
1893 uint8_t zeros;
1894 uint8_t ip_proto;
1895 uint16_t ip_payload;
1896} ip_pseudo_header;
1897
1898#define IP_PROTO_TCP 6
1899#define IP_PROTO_UDP 17
1900
1901#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1902#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1903#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1904
1905#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1906
1907#define TCP_FLAG_FIN 0x01
1908#define TCP_FLAG_PUSH 0x08
1909
1910/* produces ones' complement sum of data */
1911static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1912{
1913 uint32_t result = 0;
1914
1915 for (; len > 1; data+=2, len-=2)
1916 {
1917 result += *(uint16_t*)data;
1918 }
1919
1920 /* add the remainder byte */
1921 if (len)
1922 {
1923 uint8_t odd[2] = {*data, 0};
1924 result += *(uint16_t*)odd;
1925 }
1926
1927 while (result>>16)
1928 result = (result & 0xffff) + (result >> 16);
1929
1930 return result;
1931}
1932
1933static uint16_t ip_checksum(void *data, size_t len)
1934{
1935 return ~ones_complement_sum((uint8_t*)data, len);
1936}
1937
a41b2ff2
PB		 1938static int rtl8139_cplus_transmit_one(RTL8139State *s)
1939{
1940 if (!rtl8139_transmitter_enabled(s))
1941 {
6cadb320 1942 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
a41b2ff2
PB		 1943 return 0;
1944 }
1945
1946 if (!rtl8139_cp_transmitter_enabled(s))
1947 {
6cadb320 1948 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
a41b2ff2
PB		 1949 return 0 ;
1950 }
1951
1952 int descriptor = s->currCPlusTxDesc;
1953
c227f099 1954 target_phys_addr_t cplus_tx_ring_desc =
a41b2ff2
PB		 1955 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1956
1957 /* Normal priority ring */
1958 cplus_tx_ring_desc += 16 * descriptor;
1959
6cadb320
FB		 1960 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1961 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
a41b2ff2
PB		 1962
1963 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1964
1965 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1966 txdw0 = le32_to_cpu(val);
1967 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1968 txdw1 = le32_to_cpu(val);
1969 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1970 txbufLO = le32_to_cpu(val);
1971 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1972 txbufHI = le32_to_cpu(val);
1973
6cadb320 1974 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 1975 descriptor,
6cadb320 1976 txdw0, txdw1, txbufLO, txbufHI));
a41b2ff2
PB		 1977
1978/* w0 ownership flag */
1979#define CP_TX_OWN (1<<31)
1980/* w0 end of ring flag */
1981#define CP_TX_EOR (1<<30)
1982/* first segment of received packet flag */
1983#define CP_TX_FS (1<<29)
1984/* last segment of received packet flag */
1985#define CP_TX_LS (1<<28)
1986/* large send packet flag */
1987#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1988/* large send MSS mask, bits 16...25 */
1989#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1990
a41b2ff2
PB		 1991/* IP checksum offload flag */
1992#define CP_TX_IPCS (1<<18)
1993/* UDP checksum offload flag */
1994#define CP_TX_UDPCS (1<<17)
1995/* TCP checksum offload flag */
1996#define CP_TX_TCPCS (1<<16)
1997
1998/* w0 bits 0...15 : buffer size */
1999#define CP_TX_BUFFER_SIZE (1<<16)
2000#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 2001/* w1 add tag flag */
2002#define CP_TX_TAGC (1<<17)
2003/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 2004#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2005/* w2 low 32bit of Rx buffer ptr */
2006/* w3 high 32bit of Rx buffer ptr */
2007
2008/* set after transmission */
2009/* FIFO underrun flag */
2010#define CP_TX_STATUS_UNF (1<<25)
2011/* transmit error summary flag, valid if set any of three below */
2012#define CP_TX_STATUS_TES (1<<23)
2013/* out-of-window collision flag */
2014#define CP_TX_STATUS_OWC (1<<22)
2015/* link failure flag */
2016#define CP_TX_STATUS_LNKF (1<<21)
2017/* excessive collisions flag */
2018#define CP_TX_STATUS_EXC (1<<20)
2019
2020 if (!(txdw0 & CP_TX_OWN))
2021 {
6cadb320 2022 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
a41b2ff2
PB		 2023 return 0 ;
2024 }
2025
6cadb320
FB		 2026 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
2027
2028 if (txdw0 & CP_TX_FS)
2029 {
2030 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
2031
2032 /* reset internal buffer offset */
2033 s->cplus_txbuffer_offset = 0;
2034 }
a41b2ff2
PB		 2035
2036 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
c227f099 2037 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 2038
6cadb320
FB		 2039 /* make sure we have enough space to assemble the packet */
2040 if (!s->cplus_txbuffer)
2041 {
2042 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2bc6f59b 2043 s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
6cadb320 2044 s->cplus_txbuffer_offset = 0;
718da2b9
FB		 2045
2046 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
6cadb320
FB		 2047 }
2048
2049 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2050 {
2051 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2137b4cc 2052 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2053
6cadb320
FB		 2054 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2055 }
2056
2057 if (!s->cplus_txbuffer)
2058 {
2059 /* out of memory */
a41b2ff2 2060
6cadb320
FB		 2061 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2062
2063 /* update tally counter */
2064 ++s->tally_counters.TxERR;
2065 ++s->tally_counters.TxAbt;
2066
2067 return 0;
2068 }
2069
2070 /* append more data to the packet */
2071
2072 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2073 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2074
2075 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2076 s->cplus_txbuffer_offset += txsize;
2077
2078 /* seek to next Rx descriptor */
2079 if (txdw0 & CP_TX_EOR)
2080 {
2081 s->currCPlusTxDesc = 0;
2082 }
2083 else
2084 {
2085 ++s->currCPlusTxDesc;
2086 if (s->currCPlusTxDesc >= 64)
2087 s->currCPlusTxDesc = 0;
2088 }
a41b2ff2
PB		 2089
2090 /* transfer ownership to target */
2091 txdw0 &= ~CP_RX_OWN;
2092
2093 /* reset error indicator bits */
2094 txdw0 &= ~CP_TX_STATUS_UNF;
2095 txdw0 &= ~CP_TX_STATUS_TES;
2096 txdw0 &= ~CP_TX_STATUS_OWC;
2097 txdw0 &= ~CP_TX_STATUS_LNKF;
2098 txdw0 &= ~CP_TX_STATUS_EXC;
2099
2100 /* update ring data */
2101 val = cpu_to_le32(txdw0);
2102 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2103
6cadb320
FB		 2104 /* Now decide if descriptor being processed is holding the last segment of packet */
2105 if (txdw0 & CP_TX_LS)
a41b2ff2 2106 {
bf6b87a8
BP		 2107 uint8_t dot1q_buffer_space[VLAN_HLEN];
2108 uint16_t *dot1q_buffer;
2109
6cadb320
FB		 2110 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2111
2112 /* can transfer fully assembled packet */
2113
2114 uint8_t *saved_buffer = s->cplus_txbuffer;
2115 int saved_size = s->cplus_txbuffer_offset;
2116 int saved_buffer_len = s->cplus_txbuffer_len;
2117
bf6b87a8
BP		 2118 /* create vlan tag */
2119 if (txdw1 & CP_TX_TAGC) {
2120 /* the vlan tag is in BE byte order in the descriptor
2121 * BE + le_to_cpu() + ~swap()~ = cpu */
2122 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : inserting vlan tag with "
2123 "tci: %u\n", bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)));
2124
2125 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2126 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2127 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2128 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2129 } else {
2130 dot1q_buffer = NULL;
2131 }
2132
6cadb320
FB		 2133 /* reset the card space to protect from recursive call */
2134 s->cplus_txbuffer = NULL;
2135 s->cplus_txbuffer_offset = 0;
2136 s->cplus_txbuffer_len = 0;
2137
718da2b9 2138 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320
FB		 2139 {
2140 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2141
6cadb320 2142 /* ip packet header */
660f11be 2143 ip_header *ip = NULL;
6cadb320 2144 int hlen = 0;
718da2b9
FB		 2145 uint8_t ip_protocol = 0;
2146 uint16_t ip_data_len = 0;
6cadb320 2147
660f11be 2148 uint8_t *eth_payload_data = NULL;
718da2b9 2149 size_t eth_payload_len = 0;
6cadb320 2150
718da2b9 2151 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2152 if (proto == ETH_P_IP)
2153 {
2154 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2155
2156 /* not aligned */
718da2b9
FB		 2157 eth_payload_data = saved_buffer + ETH_HLEN;
2158 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2159
718da2b9 2160 ip = (ip_header*)eth_payload_data;
6cadb320 2161
718da2b9
FB		 2162 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2163 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
6cadb320
FB		 2164 ip = NULL;
2165 } else {
718da2b9
FB		 2166 hlen = IP_HEADER_LENGTH(ip);
2167 ip_protocol = ip->ip_p;
2168 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2169 }
2170 }
2171
2172 if (ip)
2173 {
2174 if (txdw0 & CP_TX_IPCS)
2175 {
2176 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2177
718da2b9 2178 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2179 /* bad packet header len */
2180 /* or packet too short */
2181 }
2182 else
2183 {
2184 ip->ip_sum = 0;
718da2b9 2185 ip->ip_sum = ip_checksum(ip, hlen);
6cadb320
FB		 2186 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2187 }
2188 }
2189
718da2b9 2190 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2191 {
718da2b9
FB		 2192#if defined (DEBUG_RTL8139)
2193 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2194#endif
2195 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2196 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
6cadb320 2197
718da2b9
FB		 2198 int tcp_send_offset = 0;
2199 int send_count = 0;
6cadb320
FB		 2200
2201 /* maximum IP header length is 60 bytes */
2202 uint8_t saved_ip_header[60];
6cadb320 2203
718da2b9
FB		 2204 /* save IP header template; data area is used in tcp checksum calculation */
2205 memcpy(saved_ip_header, eth_payload_data, hlen);
2206
2207 /* a placeholder for checksum calculation routine in tcp case */
2208 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2209 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2210
2211 /* pointer to TCP header */
2212 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2213
2214 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2215
2216 /* ETH_MTU = ip header len + tcp header len + payload */
2217 int tcp_data_len = ip_data_len - tcp_hlen;
2218 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2219
2220 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2221 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2222
2223 /* note the cycle below overwrites IP header data,
2224 but restores it from saved_ip_header before sending packet */
2225
2226 int is_last_frame = 0;
2227
2228 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2229 {
2230 uint16_t chunk_size = tcp_chunk_size;
2231
2232 /* check if this is the last frame */
2233 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2234 {
2235 is_last_frame = 1;
2236 chunk_size = tcp_data_len - tcp_send_offset;
2237 }
2238
2239 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2240
2241 /* add 4 TCP pseudoheader fields */
2242 /* copy IP source and destination fields */
2243 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2244
2245 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2246
2247 if (tcp_send_offset)
2248 {
2249 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2250 }
2251
2252 /* keep PUSH and FIN flags only for the last frame */
2253 if (!is_last_frame)
2254 {
2255 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2256 }
6cadb320 2257
718da2b9
FB		 2258 /* recalculate TCP checksum */
2259 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2260 p_tcpip_hdr->zeros = 0;
2261 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2262 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2263
2264 p_tcp_hdr->th_sum = 0;
2265
2266 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2267 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2268
2269 p_tcp_hdr->th_sum = tcp_checksum;
2270
2271 /* restore IP header */
2272 memcpy(eth_payload_data, saved_ip_header, hlen);
2273
2274 /* set IP data length and recalculate IP checksum */
2275 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2276
2277 /* increment IP id for subsequent frames */
2278 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2279
2280 ip->ip_sum = 0;
2281 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2282 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2283
2284 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2285 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
bf6b87a8
BP		 2286 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2287 0, (uint8_t *) dot1q_buffer);
718da2b9
FB		 2288
2289 /* add transferred count to TCP sequence number */
2290 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2291 ++send_count;
2292 }
2293
2294 /* Stop sending this frame */
2295 saved_size = 0;
2296 }
2297 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2298 {
2299 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2300
2301 /* maximum IP header length is 60 bytes */
2302 uint8_t saved_ip_header[60];
2303 memcpy(saved_ip_header, eth_payload_data, hlen);
2304
2305 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2306 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2307
2308 /* add 4 TCP pseudoheader fields */
2309 /* copy IP source and destination fields */
718da2b9 2310 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2311
718da2b9 2312 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320
FB		 2313 {
2314 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2315
718da2b9
FB		 2316 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2317 p_tcpip_hdr->zeros = 0;
2318 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2319 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2320
718da2b9 2321 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2322
2323 p_tcp_hdr->th_sum = 0;
2324
718da2b9 2325 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2326 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2327
2328 p_tcp_hdr->th_sum = tcp_checksum;
2329 }
718da2b9 2330 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320
FB		 2331 {
2332 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2333
718da2b9
FB		 2334 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2335 p_udpip_hdr->zeros = 0;
2336 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2337 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2338
718da2b9 2339 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2340
6cadb320
FB		 2341 p_udp_hdr->uh_sum = 0;
2342
718da2b9 2343 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2344 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2345
6cadb320
FB		 2346 p_udp_hdr->uh_sum = udp_checksum;
2347 }
2348
2349 /* restore IP header */
718da2b9 2350 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2351 }
2352 }
2353 }
2354
2355 /* update tally counter */
2356 ++s->tally_counters.TxOk;
2357
2358 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2359
bf6b87a8
BP		 2360 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2361 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2362
2363 /* restore card space if there was no recursion and reset offset */
2364 if (!s->cplus_txbuffer)
2365 {
2366 s->cplus_txbuffer = saved_buffer;
2367 s->cplus_txbuffer_len = saved_buffer_len;
2368 s->cplus_txbuffer_offset = 0;
2369 }
2370 else
2371 {
2bc6f59b 2372 qemu_free(saved_buffer);
6cadb320 2373 }
a41b2ff2
PB		 2374 }
2375 else
2376 {
6cadb320 2377 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
a41b2ff2
PB		 2378 }
2379
a41b2ff2
PB		 2380 return 1;
2381}
2382
2383static void rtl8139_cplus_transmit(RTL8139State *s)
2384{
2385 int txcount = 0;
2386
2387 while (rtl8139_cplus_transmit_one(s))
2388 {
2389 ++txcount;
2390 }
2391
2392 /* Mark transfer completed */
2393 if (!txcount)
2394 {
6cadb320
FB		 2395 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2396 s->currCPlusTxDesc));
a41b2ff2
PB		 2397 }
2398 else
2399 {
2400 /* update interrupt status */
2401 s->IntrStatus |= TxOK;
2402 rtl8139_update_irq(s);
2403 }
2404}
2405
2406static void rtl8139_transmit(RTL8139State *s)
2407{
2408 int descriptor = s->currTxDesc, txcount = 0;
2409
2410 /*while*/
2411 if (rtl8139_transmit_one(s, descriptor))
2412 {
2413 ++s->currTxDesc;
2414 s->currTxDesc %= 4;
2415 ++txcount;
2416 }
2417
2418 /* Mark transfer completed */
2419 if (!txcount)
2420 {
6cadb320 2421 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
a41b2ff2
PB		 2422 }
2423}
2424
2425static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2426{
2427
2428 int descriptor = txRegOffset/4;
6cadb320
FB		 2429
2430 /* handle C+ transmit mode register configuration */
2431
2c3891ab 2432 if (s->cplus_enabled)
6cadb320
FB		 2433 {
2434 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2435
2436 /* handle Dump Tally Counters command */
2437 s->TxStatus[descriptor] = val;
2438
2439 if (descriptor == 0 && (val & 0x8))
2440 {
c227f099 2441 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2442
2443 /* dump tally counters to specified memory location */
2444 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2445
2446 /* mark dump completed */
2447 s->TxStatus[0] &= ~0x8;
2448 }
2449
2450 return;
2451 }
2452
2453 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
a41b2ff2
PB		 2454
2455 /* mask only reserved bits */
2456 val &= ~0xff00c000; /* these bits are reset on write */
2457 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2458
2459 s->TxStatus[descriptor] = val;
2460
2461 /* attempt to start transmission */
2462 rtl8139_transmit(s);
2463}
2464
2465static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2466{
2467 uint32_t ret = s->TxStatus[txRegOffset/4];
2468
6cadb320 2469 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
a41b2ff2
PB		 2470
2471 return ret;
2472}
2473
2474static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2475{
2476 uint16_t ret = 0;
2477
2478 /* Simulate TSAD, it is read only anyway */
2479
2480 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2481 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2482 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2483 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2484
2485 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2486 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2487 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2488 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2489
a41b2ff2
PB		 2490 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2491 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2492 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2493 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2494
a41b2ff2
PB		 2495 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2496 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2497 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2498 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2499
a41b2ff2 2500
6cadb320 2501 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
a41b2ff2
PB		 2502
2503 return ret;
2504}
2505
2506static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2507{
2508 uint16_t ret = s->CSCR;
2509
6cadb320 2510 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
a41b2ff2
PB		 2511
2512 return ret;
2513}
2514
2515static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2516{
6cadb320 2517 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
a41b2ff2 2518
290a0933 2519 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2520}
2521
2522static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2523{
290a0933 2524 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2525
6cadb320 2526 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
a41b2ff2
PB		 2527
2528 return ret;
2529}
2530
2531static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2532{
6cadb320 2533 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
a41b2ff2
PB		 2534
2535 /* this value is off by 16 */
2536 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2537
6cadb320
FB		 2538 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2539 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 2540}
2541
2542static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2543{
2544 /* this value is off by 16 */
2545 uint32_t ret = s->RxBufPtr - 0x10;
2546
6cadb320
FB		 2547 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2548
2549 return ret;
2550}
2551
2552static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2553{
2554 /* this value is NOT off by 16 */
2555 uint32_t ret = s->RxBufAddr;
2556
2557 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
a41b2ff2
PB		 2558
2559 return ret;
2560}
2561
2562static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2563{
6cadb320 2564 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
a41b2ff2
PB		 2565
2566 s->RxBuf = val;
2567
2568 /* may need to reset rxring here */
2569}
2570
2571static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2572{
2573 uint32_t ret = s->RxBuf;
2574
6cadb320 2575 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
a41b2ff2
PB		 2576
2577 return ret;
2578}
2579
2580static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2581{
6cadb320 2582 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2583
2584 /* mask unwriteable bits */
2585 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2586
2587 s->IntrMask = val;
2588
74475455 2589 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2590 rtl8139_update_irq(s);
05447803 2591
a41b2ff2
PB		 2592}
2593
2594static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2595{
2596 uint32_t ret = s->IntrMask;
2597
6cadb320 2598 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2599
2600 return ret;
2601}
2602
2603static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2604{
6cadb320 2605 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2606
2607#if 0
2608
2609 /* writing to ISR has no effect */
2610
2611 return;
2612
2613#else
2614 uint16_t newStatus = s->IntrStatus & ~val;
2615
2616 /* mask unwriteable bits */
2617 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2618
2619 /* writing 1 to interrupt status register bit clears it */
2620 s->IntrStatus = 0;
2621 rtl8139_update_irq(s);
2622
2623 s->IntrStatus = newStatus;
05447803
FZ		 2624 /*
2625 * Computing if we miss an interrupt here is not that correct but
2626 * considered that we should have had already an interrupt
2627 * and probably emulated is slower is better to assume this resetting was
2628 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2629 */
74475455 2630 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2631 rtl8139_update_irq(s);
05447803 2632
a41b2ff2
PB		 2633#endif
2634}
2635
2636static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2637{
74475455 2638 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2639
a41b2ff2
PB		 2640 uint32_t ret = s->IntrStatus;
2641
6cadb320 2642 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2643
2644#if 0
2645
2646 /* reading ISR clears all interrupts */
2647 s->IntrStatus = 0;
2648
2649 rtl8139_update_irq(s);
2650
2651#endif
2652
2653 return ret;
2654}
2655
2656static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2657{
6cadb320 2658 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2659
2660 /* mask unwriteable bits */
2661 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2662
2663 s->MultiIntr = val;
2664}
2665
2666static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2667{
2668 uint32_t ret = s->MultiIntr;
2669
6cadb320 2670 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2671
2672 return ret;
2673}
2674
2675static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2676{
2677 RTL8139State *s = opaque;
2678
2679 addr &= 0xff;
2680
2681 switch (addr)
2682 {
2683 case MAC0 ... MAC0+5:
2684 s->phys[addr - MAC0] = val;
2685 break;
2686 case MAC0+6 ... MAC0+7:
2687 /* reserved */
2688 break;
2689 case MAR0 ... MAR0+7:
2690 s->mult[addr - MAR0] = val;
2691 break;
2692 case ChipCmd:
2693 rtl8139_ChipCmd_write(s, val);
2694 break;
2695 case Cfg9346:
2696 rtl8139_Cfg9346_write(s, val);
2697 break;
2698 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2699 rtl8139_TxConfig_writeb(s, val);
2700 break;
2701 case Config0:
2702 rtl8139_Config0_write(s, val);
2703 break;
2704 case Config1:
2705 rtl8139_Config1_write(s, val);
2706 break;
2707 case Config3:
2708 rtl8139_Config3_write(s, val);
2709 break;
2710 case Config4:
2711 rtl8139_Config4_write(s, val);
2712 break;
2713 case Config5:
2714 rtl8139_Config5_write(s, val);
2715 break;
2716 case MediaStatus:
2717 /* ignore */
6cadb320 2718 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
a41b2ff2
PB		 2719 break;
2720
2721 case HltClk:
6cadb320 2722 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
a41b2ff2
PB		 2723 if (val == 'R')
2724 {
2725 s->clock_enabled = 1;
2726 }
2727 else if (val == 'H')
2728 {
2729 s->clock_enabled = 0;
2730 }
2731 break;
2732
2733 case TxThresh:
6cadb320 2734 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2735 s->TxThresh = val;
2736 break;
2737
2738 case TxPoll:
6cadb320 2739 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2740 if (val & (1 << 7))
2741 {
6cadb320 2742 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
a41b2ff2
PB		 2743 //rtl8139_cplus_transmit(s);
2744 }
2745 if (val & (1 << 6))
2746 {
6cadb320 2747 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
a41b2ff2
PB		 2748 rtl8139_cplus_transmit(s);
2749 }
2750
2751 break;
2752
2753 default:
6cadb320 2754 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
a41b2ff2
PB		 2755 break;
2756 }
2757}
2758
2759static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2760{
2761 RTL8139State *s = opaque;
2762
2763 addr &= 0xfe;
2764
2765 switch (addr)
2766 {
2767 case IntrMask:
2768 rtl8139_IntrMask_write(s, val);
2769 break;
2770
2771 case IntrStatus:
2772 rtl8139_IntrStatus_write(s, val);
2773 break;
2774
2775 case MultiIntr:
2776 rtl8139_MultiIntr_write(s, val);
2777 break;
2778
2779 case RxBufPtr:
2780 rtl8139_RxBufPtr_write(s, val);
2781 break;
2782
2783 case BasicModeCtrl:
2784 rtl8139_BasicModeCtrl_write(s, val);
2785 break;
2786 case BasicModeStatus:
2787 rtl8139_BasicModeStatus_write(s, val);
2788 break;
2789 case NWayAdvert:
6cadb320 2790 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2791 s->NWayAdvert = val;
2792 break;
2793 case NWayLPAR:
6cadb320 2794 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2795 break;
2796 case NWayExpansion:
6cadb320 2797 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2798 s->NWayExpansion = val;
2799 break;
2800
2801 case CpCmd:
2802 rtl8139_CpCmd_write(s, val);
2803 break;
2804
6cadb320
FB		 2805 case IntrMitigate:
2806 rtl8139_IntrMitigate_write(s, val);
2807 break;
2808
a41b2ff2 2809 default:
6cadb320 2810 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
a41b2ff2 2811
a41b2ff2
PB		 2812 rtl8139_io_writeb(opaque, addr, val & 0xff);
2813 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2814 break;
2815 }
2816}
2817
05447803
FZ		 2818static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2819{
2820 int64_t pci_time, next_time;
2821 uint32_t low_pci;
2822
2823 DEBUG_PRINT(("RTL8139: entered rtl8139_set_next_tctr_time\n"));
2824
2825 if (s->TimerExpire && current_time >= s->TimerExpire) {
2826 s->IntrStatus |= PCSTimeout;
2827 rtl8139_update_irq(s);
2828 }
2829
2830 /* Set QEMU timer only if needed that is
2831 * - TimerInt <> 0 (we have a timer)
2832 * - mask = 1 (we want an interrupt timer)
2833 * - irq = 0 (irq is not already active)
2834 * If any of above change we need to compute timer again
2835 * Also we must check if timer is passed without QEMU timer
2836 */
2837 s->TimerExpire = 0;
2838 if (!s->TimerInt) {
2839 return;
2840 }
2841
2842 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2843 get_ticks_per_sec());
2844 low_pci = pci_time & 0xffffffff;
2845 pci_time = pci_time - low_pci + s->TimerInt;
2846 if (low_pci >= s->TimerInt) {
2847 pci_time += 0x100000000LL;
2848 }
2849 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2850 PCI_FREQUENCY);
2851 s->TimerExpire = next_time;
2852
2853 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2854 qemu_mod_timer(s->timer, next_time);
2855 }
2856}
2857
a41b2ff2
PB		 2858static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2859{
2860 RTL8139State *s = opaque;
2861
2862 addr &= 0xfc;
2863
2864 switch (addr)
2865 {
2866 case RxMissed:
6cadb320 2867 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
a41b2ff2
PB		 2868 s->RxMissed = 0;
2869 break;
2870
2871 case TxConfig:
2872 rtl8139_TxConfig_write(s, val);
2873 break;
2874
2875 case RxConfig:
2876 rtl8139_RxConfig_write(s, val);
2877 break;
2878
2879 case TxStatus0 ... TxStatus0+4*4-1:
2880 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2881 break;
2882
2883 case TxAddr0 ... TxAddr0+4*4-1:
2884 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2885 break;
2886
2887 case RxBuf:
2888 rtl8139_RxBuf_write(s, val);
2889 break;
2890
2891 case RxRingAddrLO:
6cadb320 2892 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
a41b2ff2
PB		 2893 s->RxRingAddrLO = val;
2894 break;
2895
2896 case RxRingAddrHI:
6cadb320 2897 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
a41b2ff2
PB		 2898 s->RxRingAddrHI = val;
2899 break;
2900
6cadb320
FB		 2901 case Timer:
2902 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
74475455 2903 s->TCTR_base = qemu_get_clock_ns(vm_clock);
05447803 2904 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2905 break;
2906
2907 case FlashReg:
2908 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
05447803
FZ		 2909 if (s->TimerInt != val) {
2910 s->TimerInt = val;
74475455 2911 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2912 }
6cadb320
FB		 2913 break;
2914
a41b2ff2 2915 default:
6cadb320 2916 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
a41b2ff2
PB		 2917 rtl8139_io_writeb(opaque, addr, val & 0xff);
2918 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2919 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2920 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2921 break;
2922 }
2923}
2924
2925static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2926{
2927 RTL8139State *s = opaque;
2928 int ret;
2929
2930 addr &= 0xff;
2931
2932 switch (addr)
2933 {
2934 case MAC0 ... MAC0+5:
2935 ret = s->phys[addr - MAC0];
2936 break;
2937 case MAC0+6 ... MAC0+7:
2938 ret = 0;
2939 break;
2940 case MAR0 ... MAR0+7:
2941 ret = s->mult[addr - MAR0];
2942 break;
2943 case ChipCmd:
2944 ret = rtl8139_ChipCmd_read(s);
2945 break;
2946 case Cfg9346:
2947 ret = rtl8139_Cfg9346_read(s);
2948 break;
2949 case Config0:
2950 ret = rtl8139_Config0_read(s);
2951 break;
2952 case Config1:
2953 ret = rtl8139_Config1_read(s);
2954 break;
2955 case Config3:
2956 ret = rtl8139_Config3_read(s);
2957 break;
2958 case Config4:
2959 ret = rtl8139_Config4_read(s);
2960 break;
2961 case Config5:
2962 ret = rtl8139_Config5_read(s);
2963 break;
2964
2965 case MediaStatus:
2966 ret = 0xd0;
6cadb320 2967 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
a41b2ff2
PB		 2968 break;
2969
2970 case HltClk:
2971 ret = s->clock_enabled;
6cadb320 2972 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
a41b2ff2
PB		 2973 break;
2974
2975 case PCIRevisionID:
6cadb320
FB		 2976 ret = RTL8139_PCI_REVID;
2977 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
a41b2ff2
PB		 2978 break;
2979
2980 case TxThresh:
2981 ret = s->TxThresh;
6cadb320 2982 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2983 break;
2984
2985 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2986 ret = s->TxConfig >> 24;
6cadb320 2987 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2988 break;
2989
2990 default:
6cadb320 2991 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
a41b2ff2
PB		 2992 ret = 0;
2993 break;
2994 }
2995
2996 return ret;
2997}
2998
2999static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3000{
3001 RTL8139State *s = opaque;
3002 uint32_t ret;
3003
3004 addr &= 0xfe; /* mask lower bit */
3005
3006 switch (addr)
3007 {
3008 case IntrMask:
3009 ret = rtl8139_IntrMask_read(s);
3010 break;
3011
3012 case IntrStatus:
3013 ret = rtl8139_IntrStatus_read(s);
3014 break;
3015
3016 case MultiIntr:
3017 ret = rtl8139_MultiIntr_read(s);
3018 break;
3019
3020 case RxBufPtr:
3021 ret = rtl8139_RxBufPtr_read(s);
3022 break;
3023
6cadb320
FB		 3024 case RxBufAddr:
3025 ret = rtl8139_RxBufAddr_read(s);
3026 break;
3027
a41b2ff2
PB		 3028 case BasicModeCtrl:
3029 ret = rtl8139_BasicModeCtrl_read(s);
3030 break;
3031 case BasicModeStatus:
3032 ret = rtl8139_BasicModeStatus_read(s);
3033 break;
3034 case NWayAdvert:
3035 ret = s->NWayAdvert;
6cadb320 3036 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 3037 break;
3038 case NWayLPAR:
3039 ret = s->NWayLPAR;
6cadb320 3040 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 3041 break;
3042 case NWayExpansion:
3043 ret = s->NWayExpansion;
6cadb320 3044 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 3045 break;
3046
3047 case CpCmd:
3048 ret = rtl8139_CpCmd_read(s);
3049 break;
3050
6cadb320
FB		 3051 case IntrMitigate:
3052 ret = rtl8139_IntrMitigate_read(s);
3053 break;
3054
a41b2ff2
PB		 3055 case TxSummary:
3056 ret = rtl8139_TSAD_read(s);
3057 break;
3058
3059 case CSCR:
3060 ret = rtl8139_CSCR_read(s);
3061 break;
3062
3063 default:
6cadb320 3064 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
a41b2ff2 3065
a41b2ff2
PB		 3066 ret = rtl8139_io_readb(opaque, addr);
3067 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3068
6cadb320 3069 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
a41b2ff2
PB		 3070 break;
3071 }
3072
3073 return ret;
3074}
3075
3076static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3077{
3078 RTL8139State *s = opaque;
3079 uint32_t ret;
3080
3081 addr &= 0xfc; /* also mask low 2 bits */
3082
3083 switch (addr)
3084 {
3085 case RxMissed:
3086 ret = s->RxMissed;
3087
6cadb320 3088 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
a41b2ff2
PB		 3089 break;
3090
3091 case TxConfig:
3092 ret = rtl8139_TxConfig_read(s);
3093 break;
3094
3095 case RxConfig:
3096 ret = rtl8139_RxConfig_read(s);
3097 break;
3098
3099 case TxStatus0 ... TxStatus0+4*4-1:
3100 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3101 break;
3102
3103 case TxAddr0 ... TxAddr0+4*4-1:
3104 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3105 break;
3106
3107 case RxBuf:
3108 ret = rtl8139_RxBuf_read(s);
3109 break;
3110
3111 case RxRingAddrLO:
3112 ret = s->RxRingAddrLO;
6cadb320 3113 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
a41b2ff2
PB		 3114 break;
3115
3116 case RxRingAddrHI:
3117 ret = s->RxRingAddrHI;
6cadb320
FB		 3118 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3119 break;
3120
3121 case Timer:
74475455 3122 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
05447803 3123 PCI_FREQUENCY, get_ticks_per_sec());
6cadb320
FB		 3124 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3125 break;
3126
3127 case FlashReg:
3128 ret = s->TimerInt;
3129 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
a41b2ff2
PB		 3130 break;
3131
3132 default:
6cadb320 3133 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
a41b2ff2 3134
a41b2ff2
PB		 3135 ret = rtl8139_io_readb(opaque, addr);
3136 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3137 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3138 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3139
6cadb320 3140 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
a41b2ff2
PB		 3141 break;
3142 }
3143
3144 return ret;
3145}
3146
3147/* */
3148
3149static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3150{
3151 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3152}
3153
3154static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3155{
3156 rtl8139_io_writew(opaque, addr & 0xFF, val);
3157}
3158
3159static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3160{
3161 rtl8139_io_writel(opaque, addr & 0xFF, val);
3162}
3163
3164static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3165{
3166 return rtl8139_io_readb(opaque, addr & 0xFF);
3167}
3168
3169static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3170{
3171 return rtl8139_io_readw(opaque, addr & 0xFF);
3172}
3173
3174static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3175{
3176 return rtl8139_io_readl(opaque, addr & 0xFF);
3177}
3178
3179/* */
3180
c227f099 3181static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3182{
3183 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3184}
3185
c227f099 3186static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3187{
3188 rtl8139_io_writew(opaque, addr & 0xFF, val);
3189}
3190
c227f099 3191static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3192{
3193 rtl8139_io_writel(opaque, addr & 0xFF, val);
3194}
3195
c227f099 3196static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3197{
3198 return rtl8139_io_readb(opaque, addr & 0xFF);
3199}
3200
c227f099 3201static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3202{
5fedc612 3203 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3204 return val;
a41b2ff2
PB		 3205}
3206
c227f099 3207static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3208{
5fedc612 3209 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3210 return val;
a41b2ff2
PB		 3211}
3212
060110c3 3213static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3214{
6597ebbb 3215 RTL8139State* s = opaque;
74475455 3216 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
060110c3 3217 if (version_id < 4) {
2c3891ab
AL		 3218 s->cplus_enabled = s->CpCmd != 0;
3219 }
3220
a41b2ff2
PB		 3221 return 0;
3222}
3223
c574ba5a
AW		 3224static bool rtl8139_hotplug_ready_needed(void *opaque)
3225{
3226 return qdev_machine_modified();
3227}
3228
3229static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3230 .name = "rtl8139/hotplug_ready",
3231 .version_id = 1,
3232 .minimum_version_id = 1,
3233 .minimum_version_id_old = 1,
3234 .fields = (VMStateField []) {
3235 VMSTATE_END_OF_LIST()
3236 }
3237};
3238
05447803
FZ		 3239static void rtl8139_pre_save(void *opaque)
3240{
3241 RTL8139State* s = opaque;
74475455 3242 int64_t current_time = qemu_get_clock_ns(vm_clock);
05447803
FZ		 3243
3244 /* set IntrStatus correctly */
3245 rtl8139_set_next_tctr_time(s, current_time);
3246 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3247 get_ticks_per_sec());
c574ba5a 3248 s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr;
05447803
FZ		 3249}
3250
060110c3
JQ		 3251static const VMStateDescription vmstate_rtl8139 = {
3252 .name = "rtl8139",
3253 .version_id = 4,
3254 .minimum_version_id = 3,
3255 .minimum_version_id_old = 3,
3256 .post_load = rtl8139_post_load,
05447803 3257 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3258 .fields = (VMStateField []) {
3259 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3260 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3261 VMSTATE_BUFFER(mult, RTL8139State),
3262 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3263 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3264
3265 VMSTATE_UINT32(RxBuf, RTL8139State),
3266 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3267 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3268 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3269
3270 VMSTATE_UINT16(IntrStatus, RTL8139State),
3271 VMSTATE_UINT16(IntrMask, RTL8139State),
3272
3273 VMSTATE_UINT32(TxConfig, RTL8139State),
3274 VMSTATE_UINT32(RxConfig, RTL8139State),
3275 VMSTATE_UINT32(RxMissed, RTL8139State),
3276 VMSTATE_UINT16(CSCR, RTL8139State),
3277
3278 VMSTATE_UINT8(Cfg9346, RTL8139State),
3279 VMSTATE_UINT8(Config0, RTL8139State),
3280 VMSTATE_UINT8(Config1, RTL8139State),
3281 VMSTATE_UINT8(Config3, RTL8139State),
3282 VMSTATE_UINT8(Config4, RTL8139State),
3283 VMSTATE_UINT8(Config5, RTL8139State),
3284
3285 VMSTATE_UINT8(clock_enabled, RTL8139State),
3286 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3287
3288 VMSTATE_UINT16(MultiIntr, RTL8139State),
3289
3290 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3291 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3292 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3293 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3294 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3295
3296 VMSTATE_UINT16(CpCmd, RTL8139State),
3297 VMSTATE_UINT8(TxThresh, RTL8139State),
3298
3299 VMSTATE_UNUSED(4),
3300 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3301 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3302
3303 VMSTATE_UINT32(currTxDesc, RTL8139State),
3304 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3305 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3306 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3307 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3308
3309 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3310 VMSTATE_INT32(eeprom.mode, RTL8139State),
3311 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3312 VMSTATE_UINT8(eeprom.address, RTL8139State),
3313 VMSTATE_UINT16(eeprom.input, RTL8139State),
3314 VMSTATE_UINT16(eeprom.output, RTL8139State),
3315
3316 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3317 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3318 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3319 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3320
3321 VMSTATE_UINT32(TCTR, RTL8139State),
3322 VMSTATE_UINT32(TimerInt, RTL8139State),
3323 VMSTATE_INT64(TCTR_base, RTL8139State),
3324
3325 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3326 vmstate_tally_counters, RTL8139TallyCounters),
3327
3328 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3329 VMSTATE_END_OF_LIST()
c574ba5a
AW		 3330 },
3331 .subsections = (VMStateSubsection []) {
3332 {
3333 .vmsd = &vmstate_rtl8139_hotplug_ready,
3334 .needed = rtl8139_hotplug_ready_needed,
3335 }, {
3336 /* empty */
3337 }
060110c3
JQ		 3338 }
3339};
3340
a41b2ff2
PB		 3341/***********************************************************/
3342/* PCI RTL8139 definitions */
3343
5fafdf24 3344static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
6e355d90 3345 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3346{
efd6dd45 3347 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3348
3349 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3350}
3351
5fafdf24 3352static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
6e355d90 3353 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3354{
efd6dd45 3355 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3356
3357 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3358 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3359
3360 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3361 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3362
3363 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3364 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3365}
3366
d60efc6b 3367static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
a41b2ff2
PB		 3368 rtl8139_mmio_readb,
3369 rtl8139_mmio_readw,
3370 rtl8139_mmio_readl,
3371};
3372
d60efc6b 3373static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
a41b2ff2
PB		 3374 rtl8139_mmio_writeb,
3375 rtl8139_mmio_writew,
3376 rtl8139_mmio_writel,
3377};
3378
6cadb320
FB		 3379static void rtl8139_timer(void *opaque)
3380{
3381 RTL8139State *s = opaque;
3382
6cadb320
FB		 3383 if (!s->clock_enabled)
3384 {
3385 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3386 return;
3387 }
3388
05447803
FZ		 3389 s->IntrStatus |= PCSTimeout;
3390 rtl8139_update_irq(s);
74475455 3391 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
6cadb320 3392}
6cadb320 3393
1673ad51 3394static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3395{
1673ad51 3396 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3397
1673ad51 3398 s->nic = NULL;
254111ec
GH		 3399}
3400
3401static int pci_rtl8139_uninit(PCIDevice *dev)
3402{
3403 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3404
3405 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
b946a153
AL		 3406 if (s->cplus_txbuffer) {
3407 qemu_free(s->cplus_txbuffer);
3408 s->cplus_txbuffer = NULL;
3409 }
b946a153
AL		 3410 qemu_del_timer(s->timer);
3411 qemu_free_timer(s->timer);
1673ad51 3412 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3413 return 0;
3414}
3415
1673ad51
MM		 3416static NetClientInfo net_rtl8139_info = {
3417 .type = NET_CLIENT_TYPE_NIC,
3418 .size = sizeof(NICState),
3419 .can_receive = rtl8139_can_receive,
3420 .receive = rtl8139_receive,
3421 .cleanup = rtl8139_cleanup,
3422};
3423
81a322d4 3424static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3425{
efd6dd45 3426 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3427 uint8_t *pci_conf;
3b46e624 3428
efd6dd45 3429 pci_conf = s->dev.config;
deb54399
AL		 3430 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3431 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
0b5b3547 3432 pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
173a543b 3433 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
0b5b3547
MT		 3434 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
3435 /* TODO: start of capability list, but no capability
3436 * list bit in status register, and offset 0xdc seems unused. */
3437 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3438
a41b2ff2
PB		 3439 /* I/O handler for memory-mapped I/O */
3440 s->rtl8139_mmio_io_addr =
2507c12a 3441 cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
5cf7a3ca 3442 DEVICE_LITTLE_ENDIAN);
a41b2ff2 3443
efd6dd45 3444 pci_register_bar(&s->dev, 0, 0x100,
0392a017 3445 PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
a41b2ff2 3446
efd6dd45 3447 pci_register_bar(&s->dev, 1, 0x100,
0392a017 3448 PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map);
a41b2ff2 3449
254111ec 3450 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3451
7165448a
WD		 3452 /* prepare eeprom */
3453 s->eeprom.contents[0] = 0x8129;
3454#if 1
3455 /* PCI vendor and device ID should be mirrored here */
3456 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3457 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3458#endif
3459 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3460 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3461 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3462
1673ad51
MM		 3463 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3464 dev->qdev.info->name, dev->qdev.id, s);
3465 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3466
3467 s->cplus_txbuffer = NULL;
3468 s->cplus_txbuffer_len = 0;
3469 s->cplus_txbuffer_offset = 0;
3b46e624 3470
05447803 3471 s->TimerExpire = 0;
74475455
PB		 3472 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3473 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
1ca4d09a
GN		 3474
3475 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3476
81a322d4 3477 return 0;
a41b2ff2 3478}
9d07d757 3479
0aab0d3a 3480static PCIDeviceInfo rtl8139_info = {
f82de8f0
GH		 3481 .qdev.name = "rtl8139",
3482 .qdev.size = sizeof(RTL8139State),
3483 .qdev.reset = rtl8139_reset,
be73cfe2 3484 .qdev.vmsd = &vmstate_rtl8139,
f82de8f0 3485 .init = pci_rtl8139_init,
e3936fa5 3486 .exit = pci_rtl8139_uninit,
8c52c8f3 3487 .romfile = "pxe-rtl8139.bin",
254111ec
GH		 3488 .qdev.props = (Property[]) {
3489 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3490 DEFINE_PROP_END_OF_LIST(),
3491 }
0aab0d3a
GH		 3492};
3493
9d07d757
PB		 3494static void rtl8139_register_devices(void)
3495{
0aab0d3a 3496 pci_qdev_register(&rtl8139_info);
9d07d757
PB		 3497}
3498
3499device_init(rtl8139_register_devices)
Qemu copy for testing