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net: add return value to packet receive handler
[qemu.git] / hw / rtl8139.c
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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
a41b2ff2
PB		 44 */
45
87ecb68b
PB		 46#include "hw.h"
47#include "pci.h"
48#include "qemu-timer.h"
49#include "net.h"
a41b2ff2 50
a41b2ff2
PB		 51/* debug RTL8139 card */
52//#define DEBUG_RTL8139 1
53
6cadb320
FB		 54#define PCI_FREQUENCY 33000000L
55
a41b2ff2
PB		 56/* debug RTL8139 card C+ mode only */
57//#define DEBUG_RTL8139CP 1
58
ccf1d14a
TS		 59/* Calculate CRCs properly on Rx packets */
60#define RTL8139_CALCULATE_RXCRC 1
a41b2ff2 61
6cadb320
FB		 62/* Uncomment to enable on-board timer interrupts */
63//#define RTL8139_ONBOARD_TIMER 1
a41b2ff2
PB		 64
65#if defined(RTL8139_CALCULATE_RXCRC)
66/* For crc32 */
67#include <zlib.h>
68#endif
69
70#define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73/* arg % size for size which is a power of 2 */
74#define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
6cadb320
FB		 77#if defined (DEBUG_RTL8139)
78# define DEBUG_PRINT(x) do { printf x ; } while (0)
79#else
80# define DEBUG_PRINT(x)
81#endif
82
a41b2ff2
PB		 83/* Symbolic offsets to registers. */
84enum RTL8139_registers {
85 MAC0 = 0, /* Ethernet hardware address. */
86 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 87 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
88 /* Dump Tally Conter control register(64bit). C+ mode only */
89 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 90 RxBuf = 0x30,
91 ChipCmd = 0x37,
92 RxBufPtr = 0x38,
93 RxBufAddr = 0x3A,
94 IntrMask = 0x3C,
95 IntrStatus = 0x3E,
96 TxConfig = 0x40,
97 RxConfig = 0x44,
98 Timer = 0x48, /* A general-purpose counter. */
99 RxMissed = 0x4C, /* 24 bits valid, write clears. */
100 Cfg9346 = 0x50,
101 Config0 = 0x51,
102 Config1 = 0x52,
103 FlashReg = 0x54,
104 MediaStatus = 0x58,
105 Config3 = 0x59,
106 Config4 = 0x5A, /* absent on RTL-8139A */
107 HltClk = 0x5B,
108 MultiIntr = 0x5C,
109 PCIRevisionID = 0x5E,
110 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
111 BasicModeCtrl = 0x62,
112 BasicModeStatus = 0x64,
113 NWayAdvert = 0x66,
114 NWayLPAR = 0x68,
115 NWayExpansion = 0x6A,
116 /* Undocumented registers, but required for proper operation. */
117 FIFOTMS = 0x70, /* FIFO Control and test. */
118 CSCR = 0x74, /* Chip Status and Configuration Register. */
119 PARA78 = 0x78,
120 PARA7c = 0x7c, /* Magic transceiver parameter register. */
121 Config5 = 0xD8, /* absent on RTL-8139A */
122 /* C+ mode */
123 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
124 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
125 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
126 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
127 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
128 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
129 TxThresh = 0xEC, /* Early Tx threshold */
130};
131
132enum ClearBitMasks {
133 MultiIntrClear = 0xF000,
134 ChipCmdClear = 0xE2,
135 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
136};
137
138enum ChipCmdBits {
139 CmdReset = 0x10,
140 CmdRxEnb = 0x08,
141 CmdTxEnb = 0x04,
142 RxBufEmpty = 0x01,
143};
144
145/* C+ mode */
146enum CplusCmdBits {
6cadb320
FB		 147 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
148 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
149 CPlusRxEnb = 0x0002,
150 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 151};
152
153/* Interrupt register bits, using my own meaningful names. */
154enum IntrStatusBits {
155 PCIErr = 0x8000,
156 PCSTimeout = 0x4000,
157 RxFIFOOver = 0x40,
158 RxUnderrun = 0x20,
159 RxOverflow = 0x10,
160 TxErr = 0x08,
161 TxOK = 0x04,
162 RxErr = 0x02,
163 RxOK = 0x01,
164
165 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
166};
167
168enum TxStatusBits {
169 TxHostOwns = 0x2000,
170 TxUnderrun = 0x4000,
171 TxStatOK = 0x8000,
172 TxOutOfWindow = 0x20000000,
173 TxAborted = 0x40000000,
174 TxCarrierLost = 0x80000000,
175};
176enum RxStatusBits {
177 RxMulticast = 0x8000,
178 RxPhysical = 0x4000,
179 RxBroadcast = 0x2000,
180 RxBadSymbol = 0x0020,
181 RxRunt = 0x0010,
182 RxTooLong = 0x0008,
183 RxCRCErr = 0x0004,
184 RxBadAlign = 0x0002,
185 RxStatusOK = 0x0001,
186};
187
188/* Bits in RxConfig. */
189enum rx_mode_bits {
190 AcceptErr = 0x20,
191 AcceptRunt = 0x10,
192 AcceptBroadcast = 0x08,
193 AcceptMulticast = 0x04,
194 AcceptMyPhys = 0x02,
195 AcceptAllPhys = 0x01,
196};
197
198/* Bits in TxConfig. */
199enum tx_config_bits {
200
201 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
202 TxIFGShift = 24,
203 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
204 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
205 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
206 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
207
208 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
209 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
210 TxClearAbt = (1 << 0), /* Clear abort (WO) */
211 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
212 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
213
214 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
215};
216
217
218/* Transmit Status of All Descriptors (TSAD) Register */
219enum TSAD_bits {
220 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
221 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
222 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
223 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
224 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
225 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
226 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
227 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
228 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
229 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
230 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
231 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
232 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
233 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
234 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
235 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
236};
237
238
239/* Bits in Config1 */
240enum Config1Bits {
241 Cfg1_PM_Enable = 0x01,
242 Cfg1_VPD_Enable = 0x02,
243 Cfg1_PIO = 0x04,
244 Cfg1_MMIO = 0x08,
245 LWAKE = 0x10, /* not on 8139, 8139A */
246 Cfg1_Driver_Load = 0x20,
247 Cfg1_LED0 = 0x40,
248 Cfg1_LED1 = 0x80,
249 SLEEP = (1 << 1), /* only on 8139, 8139A */
250 PWRDN = (1 << 0), /* only on 8139, 8139A */
251};
252
253/* Bits in Config3 */
254enum Config3Bits {
255 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
256 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
257 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
258 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
259 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
260 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
261 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
262 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
263};
264
265/* Bits in Config4 */
266enum Config4Bits {
267 LWPTN = (1 << 2), /* not on 8139, 8139A */
268};
269
270/* Bits in Config5 */
271enum Config5Bits {
272 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
273 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
274 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
275 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
276 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
277 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
278 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
279};
280
281enum RxConfigBits {
282 /* rx fifo threshold */
283 RxCfgFIFOShift = 13,
284 RxCfgFIFONone = (7 << RxCfgFIFOShift),
285
286 /* Max DMA burst */
287 RxCfgDMAShift = 8,
288 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
289
290 /* rx ring buffer length */
291 RxCfgRcv8K = 0,
292 RxCfgRcv16K = (1 << 11),
293 RxCfgRcv32K = (1 << 12),
294 RxCfgRcv64K = (1 << 11) | (1 << 12),
295
296 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
297 RxNoWrap = (1 << 7),
298};
299
300/* Twister tuning parameters from RealTek.
301 Completely undocumented, but required to tune bad links on some boards. */
302/*
303enum CSCRBits {
304 CSCR_LinkOKBit = 0x0400,
305 CSCR_LinkChangeBit = 0x0800,
306 CSCR_LinkStatusBits = 0x0f000,
307 CSCR_LinkDownOffCmd = 0x003c0,
308 CSCR_LinkDownCmd = 0x0f3c0,
309*/
310enum CSCRBits {
5fafdf24 311 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 312 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
313 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
314 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 315 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 316 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
317 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
318 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
319 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
320};
321
322enum Cfg9346Bits {
323 Cfg9346_Lock = 0x00,
324 Cfg9346_Unlock = 0xC0,
325};
326
327typedef enum {
328 CH_8139 = 0,
329 CH_8139_K,
330 CH_8139A,
331 CH_8139A_G,
332 CH_8139B,
333 CH_8130,
334 CH_8139C,
335 CH_8100,
336 CH_8100B_8139D,
337 CH_8101,
338} chip_t;
339
340enum chip_flags {
341 HasHltClk = (1 << 0),
342 HasLWake = (1 << 1),
343};
344
345#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
346 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
347#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
348
6cadb320
FB		 349#define RTL8139_PCI_REVID_8139 0x10
350#define RTL8139_PCI_REVID_8139CPLUS 0x20
351
352#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
353
a41b2ff2
PB		 354/* Size is 64 * 16bit words */
355#define EEPROM_9346_ADDR_BITS 6
356#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
357#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
358
359enum Chip9346Operation
360{
361 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
362 Chip9346_op_read = 0x80, /* 10 AAAAAA */
363 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
364 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
365 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
366 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
367 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
368};
369
370enum Chip9346Mode
371{
372 Chip9346_none = 0,
373 Chip9346_enter_command_mode,
374 Chip9346_read_command,
375 Chip9346_data_read, /* from output register */
376 Chip9346_data_write, /* to input register, then to contents at specified address */
377 Chip9346_data_write_all, /* to input register, then filling contents */
378};
379
380typedef struct EEprom9346
381{
382 uint16_t contents[EEPROM_9346_SIZE];
383 int mode;
384 uint32_t tick;
385 uint8_t address;
386 uint16_t input;
387 uint16_t output;
388
389 uint8_t eecs;
390 uint8_t eesk;
391 uint8_t eedi;
392 uint8_t eedo;
393} EEprom9346;
394
6cadb320
FB		 395typedef struct RTL8139TallyCounters
396{
397 /* Tally counters */
398 uint64_t TxOk;
399 uint64_t RxOk;
400 uint64_t TxERR;
401 uint32_t RxERR;
402 uint16_t MissPkt;
403 uint16_t FAE;
404 uint32_t Tx1Col;
405 uint32_t TxMCol;
406 uint64_t RxOkPhy;
407 uint64_t RxOkBrd;
408 uint32_t RxOkMul;
409 uint16_t TxAbt;
410 uint16_t TxUndrn;
411} RTL8139TallyCounters;
412
413/* Clears all tally counters */
414static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
415
416/* Writes tally counters to specified physical memory address */
417static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
418
419/* Loads values of tally counters from VM state file */
420static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
421
422/* Saves values of tally counters to VM state file */
423static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
424
a41b2ff2
PB		 425typedef struct RTL8139State {
426 uint8_t phys[8]; /* mac address */
427 uint8_t mult[8]; /* multicast mask array */
428
6cadb320 429 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 430 uint32_t TxAddr[4]; /* TxAddr0 */
431 uint32_t RxBuf; /* Receive buffer */
432 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
433 uint32_t RxBufPtr;
434 uint32_t RxBufAddr;
435
436 uint16_t IntrStatus;
437 uint16_t IntrMask;
438
439 uint32_t TxConfig;
440 uint32_t RxConfig;
441 uint32_t RxMissed;
442
443 uint16_t CSCR;
444
445 uint8_t Cfg9346;
446 uint8_t Config0;
447 uint8_t Config1;
448 uint8_t Config3;
449 uint8_t Config4;
450 uint8_t Config5;
451
452 uint8_t clock_enabled;
453 uint8_t bChipCmdState;
454
455 uint16_t MultiIntr;
456
457 uint16_t BasicModeCtrl;
458 uint16_t BasicModeStatus;
459 uint16_t NWayAdvert;
460 uint16_t NWayLPAR;
461 uint16_t NWayExpansion;
462
463 uint16_t CpCmd;
464 uint8_t TxThresh;
465
a41b2ff2
PB		 466 PCIDevice *pci_dev;
467 VLANClientState *vc;
468 uint8_t macaddr[6];
469 int rtl8139_mmio_io_addr;
470
471 /* C ring mode */
472 uint32_t currTxDesc;
473
474 /* C+ mode */
2c3891ab
AL		 475 uint32_t cplus_enabled;
476
a41b2ff2
PB		 477 uint32_t currCPlusRxDesc;
478 uint32_t currCPlusTxDesc;
479
480 uint32_t RxRingAddrLO;
481 uint32_t RxRingAddrHI;
482
483 EEprom9346 eeprom;
6cadb320
FB		 484
485 uint32_t TCTR;
486 uint32_t TimerInt;
487 int64_t TCTR_base;
488
489 /* Tally counters */
490 RTL8139TallyCounters tally_counters;
491
492 /* Non-persistent data */
493 uint8_t *cplus_txbuffer;
494 int cplus_txbuffer_len;
495 int cplus_txbuffer_offset;
496
497 /* PCI interrupt timer */
498 QEMUTimer *timer;
499
a41b2ff2
PB		 500} RTL8139State;
501
9596ebb7 502static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 503{
6cadb320 504 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
a41b2ff2
PB		 505
506 switch (command & Chip9346_op_mask)
507 {
508 case Chip9346_op_read:
509 {
510 eeprom->address = command & EEPROM_9346_ADDR_MASK;
511 eeprom->output = eeprom->contents[eeprom->address];
512 eeprom->eedo = 0;
513 eeprom->tick = 0;
514 eeprom->mode = Chip9346_data_read;
6cadb320
FB		 515 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
516 eeprom->address, eeprom->output));
a41b2ff2
PB		 517 }
518 break;
519
520 case Chip9346_op_write:
521 {
522 eeprom->address = command & EEPROM_9346_ADDR_MASK;
523 eeprom->input = 0;
524 eeprom->tick = 0;
525 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
6cadb320
FB		 526 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
527 eeprom->address));
a41b2ff2
PB		 528 }
529 break;
530 default:
531 eeprom->mode = Chip9346_none;
532 switch (command & Chip9346_op_ext_mask)
533 {
534 case Chip9346_op_write_enable:
6cadb320 535 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
a41b2ff2
PB		 536 break;
537 case Chip9346_op_write_all:
6cadb320 538 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
a41b2ff2
PB		 539 break;
540 case Chip9346_op_write_disable:
6cadb320 541 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
a41b2ff2
PB		 542 break;
543 }
544 break;
545 }
546}
547
9596ebb7 548static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 549{
550 int bit = eeprom->eedi?1:0;
551
552 ++ eeprom->tick;
553
6cadb320 554 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 555
556 switch (eeprom->mode)
557 {
558 case Chip9346_enter_command_mode:
559 if (bit)
560 {
561 eeprom->mode = Chip9346_read_command;
562 eeprom->tick = 0;
563 eeprom->input = 0;
6cadb320 564 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
a41b2ff2
PB		 565 }
566 break;
567
568 case Chip9346_read_command:
569 eeprom->input = (eeprom->input << 1) | (bit & 1);
570 if (eeprom->tick == 8)
571 {
572 prom9346_decode_command(eeprom, eeprom->input & 0xff);
573 }
574 break;
575
576 case Chip9346_data_read:
577 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
578 eeprom->output <<= 1;
579 if (eeprom->tick == 16)
580 {
6cadb320
FB		 581#if 1
582 // the FreeBSD drivers (rl and re) don't explicitly toggle
583 // CS between reads (or does setting Cfg9346 to 0 count too?),
584 // so we need to enter wait-for-command state here
585 eeprom->mode = Chip9346_enter_command_mode;
586 eeprom->input = 0;
587 eeprom->tick = 0;
588
589 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
590#else
591 // original behaviour
a41b2ff2
PB		 592 ++eeprom->address;
593 eeprom->address &= EEPROM_9346_ADDR_MASK;
594 eeprom->output = eeprom->contents[eeprom->address];
595 eeprom->tick = 0;
596
6cadb320
FB		 597 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
598 eeprom->address, eeprom->output));
a41b2ff2
PB		 599#endif
600 }
601 break;
602
603 case Chip9346_data_write:
604 eeprom->input = (eeprom->input << 1) | (bit & 1);
605 if (eeprom->tick == 16)
606 {
6cadb320
FB		 607 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
608 eeprom->address, eeprom->input));
609
a41b2ff2
PB		 610 eeprom->contents[eeprom->address] = eeprom->input;
611 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
612 eeprom->tick = 0;
613 eeprom->input = 0;
614 }
615 break;
616
617 case Chip9346_data_write_all:
618 eeprom->input = (eeprom->input << 1) | (bit & 1);
619 if (eeprom->tick == 16)
620 {
621 int i;
622 for (i = 0; i < EEPROM_9346_SIZE; i++)
623 {
624 eeprom->contents[i] = eeprom->input;
625 }
6cadb320
FB		 626 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
627 eeprom->input));
628
a41b2ff2
PB		 629 eeprom->mode = Chip9346_enter_command_mode;
630 eeprom->tick = 0;
631 eeprom->input = 0;
632 }
633 break;
634
635 default:
636 break;
637 }
638}
639
9596ebb7 640static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 641{
642 EEprom9346 *eeprom = &s->eeprom;
643 if (!eeprom->eecs)
644 return 0;
645
646 return eeprom->eedo;
647}
648
9596ebb7
PB		 649/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
650static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 651{
652 EEprom9346 *eeprom = &s->eeprom;
653 uint8_t old_eecs = eeprom->eecs;
654 uint8_t old_eesk = eeprom->eesk;
655
656 eeprom->eecs = eecs;
657 eeprom->eesk = eesk;
658 eeprom->eedi = eedi;
659
6cadb320
FB		 660 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
661 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 662
663 if (!old_eecs && eecs)
664 {
665 /* Synchronize start */
666 eeprom->tick = 0;
667 eeprom->input = 0;
668 eeprom->output = 0;
669 eeprom->mode = Chip9346_enter_command_mode;
670
6cadb320 671 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
a41b2ff2
PB		 672 }
673
674 if (!eecs)
675 {
6cadb320 676 DEBUG_PRINT(("=== eeprom: end access\n"));
a41b2ff2
PB		 677 return;
678 }
679
680 if (!old_eesk && eesk)
681 {
682 /* SK front rules */
683 prom9346_shift_clock(eeprom);
684 }
685}
686
687static void rtl8139_update_irq(RTL8139State *s)
688{
689 int isr;
690 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 691
80a34d67
PB		 692 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
693 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
6cadb320 694
d537cf6c 695 qemu_set_irq(s->pci_dev->irq[0], (isr != 0));
a41b2ff2
PB		 696}
697
698#define POLYNOMIAL 0x04c11db6
699
700/* From FreeBSD */
701/* XXX: optimize */
702static int compute_mcast_idx(const uint8_t *ep)
703{
704 uint32_t crc;
705 int carry, i, j;
706 uint8_t b;
707
708 crc = 0xffffffff;
709 for (i = 0; i < 6; i++) {
710 b = *ep++;
711 for (j = 0; j < 8; j++) {
712 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
713 crc <<= 1;
714 b >>= 1;
715 if (carry)
716 crc = ((crc ^ POLYNOMIAL) | carry);
717 }
718 }
719 return (crc >> 26);
720}
721
722static int rtl8139_RxWrap(RTL8139State *s)
723{
724 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
725 return (s->RxConfig & (1 << 7));
726}
727
728static int rtl8139_receiver_enabled(RTL8139State *s)
729{
730 return s->bChipCmdState & CmdRxEnb;
731}
732
733static int rtl8139_transmitter_enabled(RTL8139State *s)
734{
735 return s->bChipCmdState & CmdTxEnb;
736}
737
738static int rtl8139_cp_receiver_enabled(RTL8139State *s)
739{
740 return s->CpCmd & CPlusRxEnb;
741}
742
743static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
744{
745 return s->CpCmd & CPlusTxEnb;
746}
747
748static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
749{
750 if (s->RxBufAddr + size > s->RxBufferSize)
751 {
752 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
753
754 /* write packet data */
ccf1d14a 755 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 756 {
6cadb320 757 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
a41b2ff2
PB		 758
759 if (size > wrapped)
760 {
761 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
762 buf, size-wrapped );
763 }
764
765 /* reset buffer pointer */
766 s->RxBufAddr = 0;
767
768 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
769 buf + (size-wrapped), wrapped );
770
771 s->RxBufAddr = wrapped;
772
773 return;
774 }
775 }
776
777 /* non-wrapping path or overwrapping enabled */
778 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
779
780 s->RxBufAddr += size;
781}
782
783#define MIN_BUF_SIZE 60
784static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
785{
786#if TARGET_PHYS_ADDR_BITS > 32
787 return low | ((target_phys_addr_t)high << 32);
788#else
789 return low;
790#endif
791}
792
e3f5ec2b 793static int rtl8139_can_receive(VLANClientState *vc)
a41b2ff2 794{
e3f5ec2b 795 RTL8139State *s = vc->opaque;
a41b2ff2
PB		 796 int avail;
797
aa1f17c1 798 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 799 if (!s->clock_enabled)
800 return 1;
801 if (!rtl8139_receiver_enabled(s))
802 return 1;
803
804 if (rtl8139_cp_receiver_enabled(s)) {
805 /* ??? Flow control not implemented in c+ mode.
806 This is a hack to work around slirp deficiencies anyway. */
807 return 1;
808 } else {
809 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
810 s->RxBufferSize);
811 return (avail == 0 || avail >= 1514);
812 }
813}
814
4f1c942b 815static ssize_t rtl8139_do_receive(VLANClientState *vc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 816{
e3f5ec2b 817 RTL8139State *s = vc->opaque;
4f1c942b 818 int size = size_;
a41b2ff2
PB		 819
820 uint32_t packet_header = 0;
821
822 uint8_t buf1[60];
5fafdf24 823 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 824 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
825
6cadb320 826 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
a41b2ff2
PB		 827
828 /* test if board clock is stopped */
829 if (!s->clock_enabled)
830 {
6cadb320 831 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
4f1c942b 832 return -1;
a41b2ff2
PB		 833 }
834
835 /* first check if receiver is enabled */
836
837 if (!rtl8139_receiver_enabled(s))
838 {
6cadb320 839 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
4f1c942b 840 return -1;
a41b2ff2
PB		 841 }
842
843 /* XXX: check this */
844 if (s->RxConfig & AcceptAllPhys) {
845 /* promiscuous: receive all */
6cadb320 846 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
a41b2ff2
PB		 847
848 } else {
849 if (!memcmp(buf, broadcast_macaddr, 6)) {
850 /* broadcast address */
851 if (!(s->RxConfig & AcceptBroadcast))
852 {
6cadb320
FB		 853 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
854
855 /* update tally counter */
856 ++s->tally_counters.RxERR;
857
4f1c942b 858 return size;
a41b2ff2
PB		 859 }
860
861 packet_header |= RxBroadcast;
862
6cadb320
FB		 863 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
864
865 /* update tally counter */
866 ++s->tally_counters.RxOkBrd;
867
a41b2ff2
PB		 868 } else if (buf[0] & 0x01) {
869 /* multicast */
870 if (!(s->RxConfig & AcceptMulticast))
871 {
6cadb320
FB		 872 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
873
874 /* update tally counter */
875 ++s->tally_counters.RxERR;
876
4f1c942b 877 return size;
a41b2ff2
PB		 878 }
879
880 int mcast_idx = compute_mcast_idx(buf);
881
882 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
883 {
6cadb320
FB		 884 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
885
886 /* update tally counter */
887 ++s->tally_counters.RxERR;
888
4f1c942b 889 return size;
a41b2ff2
PB		 890 }
891
892 packet_header |= RxMulticast;
893
6cadb320
FB		 894 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
895
896 /* update tally counter */
897 ++s->tally_counters.RxOkMul;
898
a41b2ff2 899 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 900 s->phys[1] == buf[1] &&
901 s->phys[2] == buf[2] &&
902 s->phys[3] == buf[3] &&
903 s->phys[4] == buf[4] &&
a41b2ff2
PB		 904 s->phys[5] == buf[5]) {
905 /* match */
906 if (!(s->RxConfig & AcceptMyPhys))
907 {
6cadb320
FB		 908 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
909
910 /* update tally counter */
911 ++s->tally_counters.RxERR;
912
4f1c942b 913 return size;
a41b2ff2
PB		 914 }
915
916 packet_header |= RxPhysical;
917
6cadb320
FB		 918 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
919
920 /* update tally counter */
921 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 922
923 } else {
924
6cadb320
FB		 925 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
926
927 /* update tally counter */
928 ++s->tally_counters.RxERR;
929
4f1c942b 930 return size;
a41b2ff2
PB		 931 }
932 }
933
934 /* if too small buffer, then expand it */
935 if (size < MIN_BUF_SIZE) {
936 memcpy(buf1, buf, size);
937 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
938 buf = buf1;
939 size = MIN_BUF_SIZE;
940 }
941
942 if (rtl8139_cp_receiver_enabled(s))
943 {
6cadb320 944 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
a41b2ff2
PB		 945
946 /* begin C+ receiver mode */
947
948/* w0 ownership flag */
949#define CP_RX_OWN (1<<31)
950/* w0 end of ring flag */
951#define CP_RX_EOR (1<<30)
952/* w0 bits 0...12 : buffer size */
953#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
954/* w1 tag available flag */
955#define CP_RX_TAVA (1<<16)
956/* w1 bits 0...15 : VLAN tag */
957#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
958/* w2 low 32bit of Rx buffer ptr */
959/* w3 high 32bit of Rx buffer ptr */
960
961 int descriptor = s->currCPlusRxDesc;
962 target_phys_addr_t cplus_rx_ring_desc;
963
964 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
965 cplus_rx_ring_desc += 16 * descriptor;
966
6cadb320
FB		 967 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
968 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
a41b2ff2
PB		 969
970 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
971
972 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
973 rxdw0 = le32_to_cpu(val);
974 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
975 rxdw1 = le32_to_cpu(val);
976 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
977 rxbufLO = le32_to_cpu(val);
978 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
979 rxbufHI = le32_to_cpu(val);
980
6cadb320 981 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 982 descriptor,
6cadb320 983 rxdw0, rxdw1, rxbufLO, rxbufHI));
a41b2ff2
PB		 984
985 if (!(rxdw0 & CP_RX_OWN))
986 {
6cadb320
FB		 987 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
988
a41b2ff2
PB		 989 s->IntrStatus |= RxOverflow;
990 ++s->RxMissed;
6cadb320
FB		 991
992 /* update tally counter */
993 ++s->tally_counters.RxERR;
994 ++s->tally_counters.MissPkt;
995
a41b2ff2 996 rtl8139_update_irq(s);
4f1c942b 997 return size_;
a41b2ff2
PB		 998 }
999
1000 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1001
6cadb320
FB		 1002 /* TODO: scatter the packet over available receive ring descriptors space */
1003
a41b2ff2
PB		 1004 if (size+4 > rx_space)
1005 {
6cadb320
FB		 1006 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1007 descriptor, rx_space, size));
1008
a41b2ff2
PB		 1009 s->IntrStatus |= RxOverflow;
1010 ++s->RxMissed;
6cadb320
FB		 1011
1012 /* update tally counter */
1013 ++s->tally_counters.RxERR;
1014 ++s->tally_counters.MissPkt;
1015
a41b2ff2 1016 rtl8139_update_irq(s);
4f1c942b 1017 return size_;
a41b2ff2
PB		 1018 }
1019
1020 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1021
1022 /* receive/copy to target memory */
1023 cpu_physical_memory_write( rx_addr, buf, size );
1024
6cadb320
FB		 1025 if (s->CpCmd & CPlusRxChkSum)
1026 {
1027 /* do some packet checksumming */
1028 }
1029
a41b2ff2
PB		 1030 /* write checksum */
1031#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1032 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1033#else
1034 val = 0;
1035#endif
1036 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1037
1038/* first segment of received packet flag */
1039#define CP_RX_STATUS_FS (1<<29)
1040/* last segment of received packet flag */
1041#define CP_RX_STATUS_LS (1<<28)
1042/* multicast packet flag */
1043#define CP_RX_STATUS_MAR (1<<26)
1044/* physical-matching packet flag */
1045#define CP_RX_STATUS_PAM (1<<25)
1046/* broadcast packet flag */
1047#define CP_RX_STATUS_BAR (1<<24)
1048/* runt packet flag */
1049#define CP_RX_STATUS_RUNT (1<<19)
1050/* crc error flag */
1051#define CP_RX_STATUS_CRC (1<<18)
1052/* IP checksum error flag */
1053#define CP_RX_STATUS_IPF (1<<15)
1054/* UDP checksum error flag */
1055#define CP_RX_STATUS_UDPF (1<<14)
1056/* TCP checksum error flag */
1057#define CP_RX_STATUS_TCPF (1<<13)
1058
1059 /* transfer ownership to target */
1060 rxdw0 &= ~CP_RX_OWN;
1061
1062 /* set first segment bit */
1063 rxdw0 |= CP_RX_STATUS_FS;
1064
1065 /* set last segment bit */
1066 rxdw0 |= CP_RX_STATUS_LS;
1067
1068 /* set received packet type flags */
1069 if (packet_header & RxBroadcast)
1070 rxdw0 |= CP_RX_STATUS_BAR;
1071 if (packet_header & RxMulticast)
1072 rxdw0 |= CP_RX_STATUS_MAR;
1073 if (packet_header & RxPhysical)
1074 rxdw0 |= CP_RX_STATUS_PAM;
1075
1076 /* set received size */
1077 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1078 rxdw0 |= (size+4);
1079
1080 /* reset VLAN tag flag */
1081 rxdw1 &= ~CP_RX_TAVA;
1082
1083 /* update ring data */
1084 val = cpu_to_le32(rxdw0);
1085 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1086 val = cpu_to_le32(rxdw1);
1087 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1088
6cadb320
FB		 1089 /* update tally counter */
1090 ++s->tally_counters.RxOk;
1091
a41b2ff2
PB		 1092 /* seek to next Rx descriptor */
1093 if (rxdw0 & CP_RX_EOR)
1094 {
1095 s->currCPlusRxDesc = 0;
1096 }
1097 else
1098 {
1099 ++s->currCPlusRxDesc;
1100 }
1101
6cadb320 1102 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
a41b2ff2
PB		 1103
1104 }
1105 else
1106 {
6cadb320
FB		 1107 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1108
a41b2ff2
PB		 1109 /* begin ring receiver mode */
1110 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1111
1112 /* if receiver buffer is empty then avail == 0 */
1113
1114 if (avail != 0 && size + 8 >= avail)
1115 {
6cadb320
FB		 1116 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1117 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1118
a41b2ff2
PB		 1119 s->IntrStatus |= RxOverflow;
1120 ++s->RxMissed;
1121 rtl8139_update_irq(s);
4f1c942b 1122 return size_;
a41b2ff2
PB		 1123 }
1124
1125 packet_header |= RxStatusOK;
1126
1127 packet_header |= (((size+4) << 16) & 0xffff0000);
1128
1129 /* write header */
1130 uint32_t val = cpu_to_le32(packet_header);
1131
1132 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1133
1134 rtl8139_write_buffer(s, buf, size);
1135
1136 /* write checksum */
1137#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1138 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1139#else
1140 val = 0;
1141#endif
1142
1143 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1144
1145 /* correct buffer write pointer */
1146 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1147
1148 /* now we can signal we have received something */
1149
6cadb320
FB		 1150 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1151 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 1152 }
1153
1154 s->IntrStatus |= RxOK;
6cadb320
FB		 1155
1156 if (do_interrupt)
1157 {
1158 rtl8139_update_irq(s);
1159 }
4f1c942b
MM		 1160
1161 return size_;
6cadb320
FB		 1162}
1163
4f1c942b 1164static ssize_t rtl8139_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
6cadb320 1165{
4f1c942b 1166 return rtl8139_do_receive(vc, buf, size, 1);
a41b2ff2
PB		 1167}
1168
1169static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1170{
1171 s->RxBufferSize = bufferSize;
1172 s->RxBufPtr = 0;
1173 s->RxBufAddr = 0;
1174}
1175
1176static void rtl8139_reset(RTL8139State *s)
1177{
1178 int i;
1179
1180 /* restore MAC address */
1181 memcpy(s->phys, s->macaddr, 6);
1182
1183 /* reset interrupt mask */
1184 s->IntrStatus = 0;
1185 s->IntrMask = 0;
1186
1187 rtl8139_update_irq(s);
1188
1189 /* prepare eeprom */
1190 s->eeprom.contents[0] = 0x8129;
6cadb320
FB		 1191#if 1
1192 // PCI vendor and device ID should be mirrored here
deb54399
AL		 1193 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
1194 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
6cadb320 1195#endif
290a0933
TS		 1196
1197 s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8;
1198 s->eeprom.contents[8] = s->macaddr[2] | s->macaddr[3] << 8;
1199 s->eeprom.contents[9] = s->macaddr[4] | s->macaddr[5] << 8;
a41b2ff2
PB		 1200
1201 /* mark all status registers as owned by host */
1202 for (i = 0; i < 4; ++i)
1203 {
1204 s->TxStatus[i] = TxHostOwns;
1205 }
1206
1207 s->currTxDesc = 0;
1208 s->currCPlusRxDesc = 0;
1209 s->currCPlusTxDesc = 0;
1210
1211 s->RxRingAddrLO = 0;
1212 s->RxRingAddrHI = 0;
1213
1214 s->RxBuf = 0;
1215
1216 rtl8139_reset_rxring(s, 8192);
1217
1218 /* ACK the reset */
1219 s->TxConfig = 0;
1220
1221#if 0
1222// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1223 s->clock_enabled = 0;
1224#else
6cadb320 1225 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1226 s->clock_enabled = 1;
1227#endif
1228
1229 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1230
1231 /* set initial state data */
1232 s->Config0 = 0x0; /* No boot ROM */
1233 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1234 s->Config3 = 0x1; /* fast back-to-back compatible */
1235 s->Config5 = 0x0;
1236
5fafdf24 1237 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1238
1239 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1240 s->cplus_enabled = 0;
1241
a41b2ff2
PB		 1242
1243// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1244// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1245 s->BasicModeCtrl = 0x1000; // autonegotiation
1246
1247 s->BasicModeStatus = 0x7809;
1248 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1249 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1250 s->BasicModeStatus |= 0x0004; /* link is up */
1251
1252 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1253 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1254 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1255
1256 /* also reset timer and disable timer interrupt */
1257 s->TCTR = 0;
1258 s->TimerInt = 0;
1259 s->TCTR_base = 0;
1260
1261 /* reset tally counters */
1262 RTL8139TallyCounters_clear(&s->tally_counters);
1263}
1264
b1d8e52e 1265static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1266{
1267 counters->TxOk = 0;
1268 counters->RxOk = 0;
1269 counters->TxERR = 0;
1270 counters->RxERR = 0;
1271 counters->MissPkt = 0;
1272 counters->FAE = 0;
1273 counters->Tx1Col = 0;
1274 counters->TxMCol = 0;
1275 counters->RxOkPhy = 0;
1276 counters->RxOkBrd = 0;
1277 counters->RxOkMul = 0;
1278 counters->TxAbt = 0;
1279 counters->TxUndrn = 0;
1280}
1281
1282static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1283{
1284 uint16_t val16;
1285 uint32_t val32;
1286 uint64_t val64;
1287
1288 val64 = cpu_to_le64(tally_counters->TxOk);
1289 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1290
1291 val64 = cpu_to_le64(tally_counters->RxOk);
1292 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1293
1294 val64 = cpu_to_le64(tally_counters->TxERR);
1295 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1296
1297 val32 = cpu_to_le32(tally_counters->RxERR);
1298 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1299
1300 val16 = cpu_to_le16(tally_counters->MissPkt);
1301 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1302
1303 val16 = cpu_to_le16(tally_counters->FAE);
1304 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1305
1306 val32 = cpu_to_le32(tally_counters->Tx1Col);
1307 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1308
1309 val32 = cpu_to_le32(tally_counters->TxMCol);
1310 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1311
1312 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1313 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1314
1315 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1316 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1317
1318 val32 = cpu_to_le32(tally_counters->RxOkMul);
1319 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1320
1321 val16 = cpu_to_le16(tally_counters->TxAbt);
1322 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1323
1324 val16 = cpu_to_le16(tally_counters->TxUndrn);
1325 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1326}
1327
1328/* Loads values of tally counters from VM state file */
1329static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1330{
1331 qemu_get_be64s(f, &tally_counters->TxOk);
1332 qemu_get_be64s(f, &tally_counters->RxOk);
1333 qemu_get_be64s(f, &tally_counters->TxERR);
1334 qemu_get_be32s(f, &tally_counters->RxERR);
1335 qemu_get_be16s(f, &tally_counters->MissPkt);
1336 qemu_get_be16s(f, &tally_counters->FAE);
1337 qemu_get_be32s(f, &tally_counters->Tx1Col);
1338 qemu_get_be32s(f, &tally_counters->TxMCol);
1339 qemu_get_be64s(f, &tally_counters->RxOkPhy);
1340 qemu_get_be64s(f, &tally_counters->RxOkBrd);
1341 qemu_get_be32s(f, &tally_counters->RxOkMul);
1342 qemu_get_be16s(f, &tally_counters->TxAbt);
1343 qemu_get_be16s(f, &tally_counters->TxUndrn);
1344}
1345
1346/* Saves values of tally counters to VM state file */
1347static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1348{
1349 qemu_put_be64s(f, &tally_counters->TxOk);
1350 qemu_put_be64s(f, &tally_counters->RxOk);
1351 qemu_put_be64s(f, &tally_counters->TxERR);
1352 qemu_put_be32s(f, &tally_counters->RxERR);
1353 qemu_put_be16s(f, &tally_counters->MissPkt);
1354 qemu_put_be16s(f, &tally_counters->FAE);
1355 qemu_put_be32s(f, &tally_counters->Tx1Col);
1356 qemu_put_be32s(f, &tally_counters->TxMCol);
1357 qemu_put_be64s(f, &tally_counters->RxOkPhy);
1358 qemu_put_be64s(f, &tally_counters->RxOkBrd);
1359 qemu_put_be32s(f, &tally_counters->RxOkMul);
1360 qemu_put_be16s(f, &tally_counters->TxAbt);
1361 qemu_put_be16s(f, &tally_counters->TxUndrn);
a41b2ff2
PB		 1362}
1363
1364static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1365{
1366 val &= 0xff;
1367
6cadb320 1368 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
a41b2ff2
PB		 1369
1370 if (val & CmdReset)
1371 {
6cadb320 1372 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
a41b2ff2
PB		 1373 rtl8139_reset(s);
1374 }
1375 if (val & CmdRxEnb)
1376 {
6cadb320 1377 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
718da2b9
FB		 1378
1379 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1380 }
1381 if (val & CmdTxEnb)
1382 {
6cadb320 1383 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
718da2b9
FB		 1384
1385 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1386 }
1387
1388 /* mask unwriteable bits */
1389 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1390
1391 /* Deassert reset pin before next read */
1392 val &= ~CmdReset;
1393
1394 s->bChipCmdState = val;
1395}
1396
1397static int rtl8139_RxBufferEmpty(RTL8139State *s)
1398{
1399 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1400
1401 if (unread != 0)
1402 {
6cadb320 1403 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
a41b2ff2
PB		 1404 return 0;
1405 }
1406
6cadb320 1407 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
a41b2ff2
PB		 1408
1409 return 1;
1410}
1411
1412static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1413{
1414 uint32_t ret = s->bChipCmdState;
1415
1416 if (rtl8139_RxBufferEmpty(s))
1417 ret |= RxBufEmpty;
1418
6cadb320 1419 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
a41b2ff2
PB		 1420
1421 return ret;
1422}
1423
1424static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1425{
1426 val &= 0xffff;
1427
6cadb320 1428 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
a41b2ff2 1429
2c3891ab
AL		 1430 s->cplus_enabled = 1;
1431
a41b2ff2
PB		 1432 /* mask unwriteable bits */
1433 val = SET_MASKED(val, 0xff84, s->CpCmd);
1434
1435 s->CpCmd = val;
1436}
1437
1438static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1439{
1440 uint32_t ret = s->CpCmd;
1441
6cadb320
FB		 1442 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1443
1444 return ret;
1445}
1446
1447static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1448{
1449 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1450}
1451
1452static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1453{
1454 uint32_t ret = 0;
1455
1456 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1457
1458 return ret;
1459}
1460
9596ebb7 1461static int rtl8139_config_writeable(RTL8139State *s)
a41b2ff2
PB		 1462{
1463 if (s->Cfg9346 & Cfg9346_Unlock)
1464 {
1465 return 1;
1466 }
1467
6cadb320 1468 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
a41b2ff2
PB		 1469
1470 return 0;
1471}
1472
1473static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1474{
1475 val &= 0xffff;
1476
6cadb320 1477 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1478
1479 /* mask unwriteable bits */
e3d7e843 1480 uint32_t mask = 0x4cff;
a41b2ff2
PB		 1481
1482 if (1 || !rtl8139_config_writeable(s))
1483 {
1484 /* Speed setting and autonegotiation enable bits are read-only */
1485 mask |= 0x3000;
1486 /* Duplex mode setting is read-only */
1487 mask |= 0x0100;
1488 }
1489
1490 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1491
1492 s->BasicModeCtrl = val;
1493}
1494
1495static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1496{
1497 uint32_t ret = s->BasicModeCtrl;
1498
6cadb320 1499 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1500
1501 return ret;
1502}
1503
1504static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1505{
1506 val &= 0xffff;
1507
6cadb320 1508 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1509
1510 /* mask unwriteable bits */
1511 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1512
1513 s->BasicModeStatus = val;
1514}
1515
1516static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1517{
1518 uint32_t ret = s->BasicModeStatus;
1519
6cadb320 1520 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1521
1522 return ret;
1523}
1524
1525static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1526{
1527 val &= 0xff;
1528
6cadb320 1529 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
a41b2ff2
PB		 1530
1531 /* mask unwriteable bits */
1532 val = SET_MASKED(val, 0x31, s->Cfg9346);
1533
1534 uint32_t opmode = val & 0xc0;
1535 uint32_t eeprom_val = val & 0xf;
1536
1537 if (opmode == 0x80) {
1538 /* eeprom access */
1539 int eecs = (eeprom_val & 0x08)?1:0;
1540 int eesk = (eeprom_val & 0x04)?1:0;
1541 int eedi = (eeprom_val & 0x02)?1:0;
1542 prom9346_set_wire(s, eecs, eesk, eedi);
1543 } else if (opmode == 0x40) {
1544 /* Reset. */
1545 val = 0;
1546 rtl8139_reset(s);
1547 }
1548
1549 s->Cfg9346 = val;
1550}
1551
1552static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1553{
1554 uint32_t ret = s->Cfg9346;
1555
1556 uint32_t opmode = ret & 0xc0;
1557
1558 if (opmode == 0x80)
1559 {
1560 /* eeprom access */
1561 int eedo = prom9346_get_wire(s);
1562 if (eedo)
1563 {
1564 ret |= 0x01;
1565 }
1566 else
1567 {
1568 ret &= ~0x01;
1569 }
1570 }
1571
6cadb320 1572 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
a41b2ff2
PB		 1573
1574 return ret;
1575}
1576
1577static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1578{
1579 val &= 0xff;
1580
6cadb320 1581 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
a41b2ff2
PB		 1582
1583 if (!rtl8139_config_writeable(s))
1584 return;
1585
1586 /* mask unwriteable bits */
1587 val = SET_MASKED(val, 0xf8, s->Config0);
1588
1589 s->Config0 = val;
1590}
1591
1592static uint32_t rtl8139_Config0_read(RTL8139State *s)
1593{
1594 uint32_t ret = s->Config0;
1595
6cadb320 1596 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
a41b2ff2
PB		 1597
1598 return ret;
1599}
1600
1601static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1602{
1603 val &= 0xff;
1604
6cadb320 1605 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
a41b2ff2
PB		 1606
1607 if (!rtl8139_config_writeable(s))
1608 return;
1609
1610 /* mask unwriteable bits */
1611 val = SET_MASKED(val, 0xC, s->Config1);
1612
1613 s->Config1 = val;
1614}
1615
1616static uint32_t rtl8139_Config1_read(RTL8139State *s)
1617{
1618 uint32_t ret = s->Config1;
1619
6cadb320 1620 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
a41b2ff2
PB		 1621
1622 return ret;
1623}
1624
1625static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1626{
1627 val &= 0xff;
1628
6cadb320 1629 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
a41b2ff2
PB		 1630
1631 if (!rtl8139_config_writeable(s))
1632 return;
1633
1634 /* mask unwriteable bits */
1635 val = SET_MASKED(val, 0x8F, s->Config3);
1636
1637 s->Config3 = val;
1638}
1639
1640static uint32_t rtl8139_Config3_read(RTL8139State *s)
1641{
1642 uint32_t ret = s->Config3;
1643
6cadb320 1644 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
a41b2ff2
PB		 1645
1646 return ret;
1647}
1648
1649static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1650{
1651 val &= 0xff;
1652
6cadb320 1653 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
a41b2ff2
PB		 1654
1655 if (!rtl8139_config_writeable(s))
1656 return;
1657
1658 /* mask unwriteable bits */
1659 val = SET_MASKED(val, 0x0a, s->Config4);
1660
1661 s->Config4 = val;
1662}
1663
1664static uint32_t rtl8139_Config4_read(RTL8139State *s)
1665{
1666 uint32_t ret = s->Config4;
1667
6cadb320 1668 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
a41b2ff2
PB		 1669
1670 return ret;
1671}
1672
1673static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1674{
1675 val &= 0xff;
1676
6cadb320 1677 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
a41b2ff2
PB		 1678
1679 /* mask unwriteable bits */
1680 val = SET_MASKED(val, 0x80, s->Config5);
1681
1682 s->Config5 = val;
1683}
1684
1685static uint32_t rtl8139_Config5_read(RTL8139State *s)
1686{
1687 uint32_t ret = s->Config5;
1688
6cadb320 1689 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
a41b2ff2
PB		 1690
1691 return ret;
1692}
1693
1694static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1695{
1696 if (!rtl8139_transmitter_enabled(s))
1697 {
6cadb320 1698 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1699 return;
1700 }
1701
6cadb320 1702 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1703
1704 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1705
1706 s->TxConfig = val;
1707}
1708
1709static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1710{
6cadb320
FB		 1711 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1712
1713 uint32_t tc = s->TxConfig;
1714 tc &= 0xFFFFFF00;
1715 tc |= (val & 0x000000FF);
1716 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1717}
1718
1719static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1720{
1721 uint32_t ret = s->TxConfig;
1722
6cadb320 1723 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
a41b2ff2
PB		 1724
1725 return ret;
1726}
1727
1728static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1729{
6cadb320 1730 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1731
1732 /* mask unwriteable bits */
1733 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1734
1735 s->RxConfig = val;
1736
1737 /* reset buffer size and read/write pointers */
1738 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1739
6cadb320 1740 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
a41b2ff2
PB		 1741}
1742
1743static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1744{
1745 uint32_t ret = s->RxConfig;
1746
6cadb320 1747 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
a41b2ff2
PB		 1748
1749 return ret;
1750}
1751
718da2b9
FB		 1752static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1753{
1754 if (!size)
1755 {
1756 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1757 return;
1758 }
1759
1760 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1761 {
1762 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
e3f5ec2b 1763 rtl8139_do_receive(s->vc, buf, size, do_interrupt);
718da2b9
FB		 1764 }
1765 else
1766 {
1767 qemu_send_packet(s->vc, buf, size);
1768 }
1769}
1770
a41b2ff2
PB		 1771static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1772{
1773 if (!rtl8139_transmitter_enabled(s))
1774 {
6cadb320
FB		 1775 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1776 descriptor));
a41b2ff2
PB		 1777 return 0;
1778 }
1779
1780 if (s->TxStatus[descriptor] & TxHostOwns)
1781 {
6cadb320
FB		 1782 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1783 descriptor, s->TxStatus[descriptor]));
a41b2ff2
PB		 1784 return 0;
1785 }
1786
6cadb320 1787 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
a41b2ff2
PB		 1788
1789 int txsize = s->TxStatus[descriptor] & 0x1fff;
1790 uint8_t txbuffer[0x2000];
1791
6cadb320
FB		 1792 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1793 txsize, s->TxAddr[descriptor]));
a41b2ff2 1794
6cadb320 1795 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1796
1797 /* Mark descriptor as transferred */
1798 s->TxStatus[descriptor] |= TxHostOwns;
1799 s->TxStatus[descriptor] |= TxStatOK;
1800
718da2b9 1801 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
6cadb320
FB		 1802
1803 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
a41b2ff2
PB		 1804
1805 /* update interrupt */
1806 s->IntrStatus |= TxOK;
1807 rtl8139_update_irq(s);
1808
1809 return 1;
1810}
1811
718da2b9
FB		 1812/* structures and macros for task offloading */
1813typedef struct ip_header
1814{
1815 uint8_t ip_ver_len; /* version and header length */
1816 uint8_t ip_tos; /* type of service */
1817 uint16_t ip_len; /* total length */
1818 uint16_t ip_id; /* identification */
1819 uint16_t ip_off; /* fragment offset field */
1820 uint8_t ip_ttl; /* time to live */
1821 uint8_t ip_p; /* protocol */
1822 uint16_t ip_sum; /* checksum */
1823 uint32_t ip_src,ip_dst; /* source and dest address */
1824} ip_header;
1825
1826#define IP_HEADER_VERSION_4 4
1827#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1828#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1829
1830typedef struct tcp_header
1831{
1832 uint16_t th_sport; /* source port */
1833 uint16_t th_dport; /* destination port */
1834 uint32_t th_seq; /* sequence number */
1835 uint32_t th_ack; /* acknowledgement number */
1836 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1837 uint16_t th_win; /* window */
1838 uint16_t th_sum; /* checksum */
1839 uint16_t th_urp; /* urgent pointer */
1840} tcp_header;
1841
1842typedef struct udp_header
1843{
1844 uint16_t uh_sport; /* source port */
1845 uint16_t uh_dport; /* destination port */
1846 uint16_t uh_ulen; /* udp length */
1847 uint16_t uh_sum; /* udp checksum */
1848} udp_header;
1849
1850typedef struct ip_pseudo_header
1851{
1852 uint32_t ip_src;
1853 uint32_t ip_dst;
1854 uint8_t zeros;
1855 uint8_t ip_proto;
1856 uint16_t ip_payload;
1857} ip_pseudo_header;
1858
1859#define IP_PROTO_TCP 6
1860#define IP_PROTO_UDP 17
1861
1862#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1863#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1864#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1865
1866#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1867
1868#define TCP_FLAG_FIN 0x01
1869#define TCP_FLAG_PUSH 0x08
1870
1871/* produces ones' complement sum of data */
1872static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1873{
1874 uint32_t result = 0;
1875
1876 for (; len > 1; data+=2, len-=2)
1877 {
1878 result += *(uint16_t*)data;
1879 }
1880
1881 /* add the remainder byte */
1882 if (len)
1883 {
1884 uint8_t odd[2] = {*data, 0};
1885 result += *(uint16_t*)odd;
1886 }
1887
1888 while (result>>16)
1889 result = (result & 0xffff) + (result >> 16);
1890
1891 return result;
1892}
1893
1894static uint16_t ip_checksum(void *data, size_t len)
1895{
1896 return ~ones_complement_sum((uint8_t*)data, len);
1897}
1898
a41b2ff2
PB		 1899static int rtl8139_cplus_transmit_one(RTL8139State *s)
1900{
1901 if (!rtl8139_transmitter_enabled(s))
1902 {
6cadb320 1903 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
a41b2ff2
PB		 1904 return 0;
1905 }
1906
1907 if (!rtl8139_cp_transmitter_enabled(s))
1908 {
6cadb320 1909 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
a41b2ff2
PB		 1910 return 0 ;
1911 }
1912
1913 int descriptor = s->currCPlusTxDesc;
1914
1915 target_phys_addr_t cplus_tx_ring_desc =
1916 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1917
1918 /* Normal priority ring */
1919 cplus_tx_ring_desc += 16 * descriptor;
1920
6cadb320
FB		 1921 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1922 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
a41b2ff2
PB		 1923
1924 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1925
1926 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1927 txdw0 = le32_to_cpu(val);
1928 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1929 txdw1 = le32_to_cpu(val);
1930 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1931 txbufLO = le32_to_cpu(val);
1932 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1933 txbufHI = le32_to_cpu(val);
1934
6cadb320 1935 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 1936 descriptor,
6cadb320 1937 txdw0, txdw1, txbufLO, txbufHI));
a41b2ff2
PB		 1938
1939/* w0 ownership flag */
1940#define CP_TX_OWN (1<<31)
1941/* w0 end of ring flag */
1942#define CP_TX_EOR (1<<30)
1943/* first segment of received packet flag */
1944#define CP_TX_FS (1<<29)
1945/* last segment of received packet flag */
1946#define CP_TX_LS (1<<28)
1947/* large send packet flag */
1948#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1949/* large send MSS mask, bits 16...25 */
1950#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1951
a41b2ff2
PB		 1952/* IP checksum offload flag */
1953#define CP_TX_IPCS (1<<18)
1954/* UDP checksum offload flag */
1955#define CP_TX_UDPCS (1<<17)
1956/* TCP checksum offload flag */
1957#define CP_TX_TCPCS (1<<16)
1958
1959/* w0 bits 0...15 : buffer size */
1960#define CP_TX_BUFFER_SIZE (1<<16)
1961#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1962/* w1 tag available flag */
1963#define CP_RX_TAGC (1<<17)
1964/* w1 bits 0...15 : VLAN tag */
1965#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1966/* w2 low 32bit of Rx buffer ptr */
1967/* w3 high 32bit of Rx buffer ptr */
1968
1969/* set after transmission */
1970/* FIFO underrun flag */
1971#define CP_TX_STATUS_UNF (1<<25)
1972/* transmit error summary flag, valid if set any of three below */
1973#define CP_TX_STATUS_TES (1<<23)
1974/* out-of-window collision flag */
1975#define CP_TX_STATUS_OWC (1<<22)
1976/* link failure flag */
1977#define CP_TX_STATUS_LNKF (1<<21)
1978/* excessive collisions flag */
1979#define CP_TX_STATUS_EXC (1<<20)
1980
1981 if (!(txdw0 & CP_TX_OWN))
1982 {
6cadb320 1983 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
a41b2ff2
PB		 1984 return 0 ;
1985 }
1986
6cadb320
FB		 1987 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1988
1989 if (txdw0 & CP_TX_FS)
1990 {
1991 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1992
1993 /* reset internal buffer offset */
1994 s->cplus_txbuffer_offset = 0;
1995 }
a41b2ff2
PB		 1996
1997 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1998 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1999
6cadb320
FB		 2000 /* make sure we have enough space to assemble the packet */
2001 if (!s->cplus_txbuffer)
2002 {
2003 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2004 s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
2005 s->cplus_txbuffer_offset = 0;
718da2b9
FB		 2006
2007 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
6cadb320
FB		 2008 }
2009
2010 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2011 {
2012 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2137b4cc 2013 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2014
6cadb320
FB		 2015 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2016 }
2017
2018 if (!s->cplus_txbuffer)
2019 {
2020 /* out of memory */
a41b2ff2 2021
6cadb320
FB		 2022 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2023
2024 /* update tally counter */
2025 ++s->tally_counters.TxERR;
2026 ++s->tally_counters.TxAbt;
2027
2028 return 0;
2029 }
2030
2031 /* append more data to the packet */
2032
2033 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2034 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2035
2036 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2037 s->cplus_txbuffer_offset += txsize;
2038
2039 /* seek to next Rx descriptor */
2040 if (txdw0 & CP_TX_EOR)
2041 {
2042 s->currCPlusTxDesc = 0;
2043 }
2044 else
2045 {
2046 ++s->currCPlusTxDesc;
2047 if (s->currCPlusTxDesc >= 64)
2048 s->currCPlusTxDesc = 0;
2049 }
a41b2ff2
PB		 2050
2051 /* transfer ownership to target */
2052 txdw0 &= ~CP_RX_OWN;
2053
2054 /* reset error indicator bits */
2055 txdw0 &= ~CP_TX_STATUS_UNF;
2056 txdw0 &= ~CP_TX_STATUS_TES;
2057 txdw0 &= ~CP_TX_STATUS_OWC;
2058 txdw0 &= ~CP_TX_STATUS_LNKF;
2059 txdw0 &= ~CP_TX_STATUS_EXC;
2060
2061 /* update ring data */
2062 val = cpu_to_le32(txdw0);
2063 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2064// val = cpu_to_le32(txdw1);
2065// cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2066
6cadb320
FB		 2067 /* Now decide if descriptor being processed is holding the last segment of packet */
2068 if (txdw0 & CP_TX_LS)
a41b2ff2 2069 {
6cadb320
FB		 2070 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2071
2072 /* can transfer fully assembled packet */
2073
2074 uint8_t *saved_buffer = s->cplus_txbuffer;
2075 int saved_size = s->cplus_txbuffer_offset;
2076 int saved_buffer_len = s->cplus_txbuffer_len;
2077
2078 /* reset the card space to protect from recursive call */
2079 s->cplus_txbuffer = NULL;
2080 s->cplus_txbuffer_offset = 0;
2081 s->cplus_txbuffer_len = 0;
2082
718da2b9 2083 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320
FB		 2084 {
2085 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2086
2087 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2088 #define ETH_HLEN 14
718da2b9 2089 #define ETH_MTU 1500
6cadb320
FB		 2090
2091 /* ip packet header */
718da2b9 2092 ip_header *ip = 0;
6cadb320 2093 int hlen = 0;
718da2b9
FB		 2094 uint8_t ip_protocol = 0;
2095 uint16_t ip_data_len = 0;
6cadb320 2096
718da2b9
FB		 2097 uint8_t *eth_payload_data = 0;
2098 size_t eth_payload_len = 0;
6cadb320 2099
718da2b9 2100 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2101 if (proto == ETH_P_IP)
2102 {
2103 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2104
2105 /* not aligned */
718da2b9
FB		 2106 eth_payload_data = saved_buffer + ETH_HLEN;
2107 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2108
718da2b9 2109 ip = (ip_header*)eth_payload_data;
6cadb320 2110
718da2b9
FB		 2111 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2112 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
6cadb320
FB		 2113 ip = NULL;
2114 } else {
718da2b9
FB		 2115 hlen = IP_HEADER_LENGTH(ip);
2116 ip_protocol = ip->ip_p;
2117 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2118 }
2119 }
2120
2121 if (ip)
2122 {
2123 if (txdw0 & CP_TX_IPCS)
2124 {
2125 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2126
718da2b9 2127 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2128 /* bad packet header len */
2129 /* or packet too short */
2130 }
2131 else
2132 {
2133 ip->ip_sum = 0;
718da2b9 2134 ip->ip_sum = ip_checksum(ip, hlen);
6cadb320
FB		 2135 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2136 }
2137 }
2138
718da2b9 2139 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2140 {
718da2b9
FB		 2141#if defined (DEBUG_RTL8139)
2142 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2143#endif
2144 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2145 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
6cadb320 2146
718da2b9
FB		 2147 int tcp_send_offset = 0;
2148 int send_count = 0;
6cadb320
FB		 2149
2150 /* maximum IP header length is 60 bytes */
2151 uint8_t saved_ip_header[60];
6cadb320 2152
718da2b9
FB		 2153 /* save IP header template; data area is used in tcp checksum calculation */
2154 memcpy(saved_ip_header, eth_payload_data, hlen);
2155
2156 /* a placeholder for checksum calculation routine in tcp case */
2157 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2158 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2159
2160 /* pointer to TCP header */
2161 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2162
2163 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2164
2165 /* ETH_MTU = ip header len + tcp header len + payload */
2166 int tcp_data_len = ip_data_len - tcp_hlen;
2167 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2168
2169 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2170 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2171
2172 /* note the cycle below overwrites IP header data,
2173 but restores it from saved_ip_header before sending packet */
2174
2175 int is_last_frame = 0;
2176
2177 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2178 {
2179 uint16_t chunk_size = tcp_chunk_size;
2180
2181 /* check if this is the last frame */
2182 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2183 {
2184 is_last_frame = 1;
2185 chunk_size = tcp_data_len - tcp_send_offset;
2186 }
2187
2188 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2189
2190 /* add 4 TCP pseudoheader fields */
2191 /* copy IP source and destination fields */
2192 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2193
2194 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2195
2196 if (tcp_send_offset)
2197 {
2198 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2199 }
2200
2201 /* keep PUSH and FIN flags only for the last frame */
2202 if (!is_last_frame)
2203 {
2204 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2205 }
6cadb320 2206
718da2b9
FB		 2207 /* recalculate TCP checksum */
2208 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2209 p_tcpip_hdr->zeros = 0;
2210 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2211 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2212
2213 p_tcp_hdr->th_sum = 0;
2214
2215 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2216 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2217
2218 p_tcp_hdr->th_sum = tcp_checksum;
2219
2220 /* restore IP header */
2221 memcpy(eth_payload_data, saved_ip_header, hlen);
2222
2223 /* set IP data length and recalculate IP checksum */
2224 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2225
2226 /* increment IP id for subsequent frames */
2227 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2228
2229 ip->ip_sum = 0;
2230 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2231 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2232
2233 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2234 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2235 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2236
2237 /* add transferred count to TCP sequence number */
2238 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2239 ++send_count;
2240 }
2241
2242 /* Stop sending this frame */
2243 saved_size = 0;
2244 }
2245 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2246 {
2247 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2248
2249 /* maximum IP header length is 60 bytes */
2250 uint8_t saved_ip_header[60];
2251 memcpy(saved_ip_header, eth_payload_data, hlen);
2252
2253 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2254 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2255
2256 /* add 4 TCP pseudoheader fields */
2257 /* copy IP source and destination fields */
718da2b9 2258 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2259
718da2b9 2260 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320
FB		 2261 {
2262 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2263
718da2b9
FB		 2264 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2265 p_tcpip_hdr->zeros = 0;
2266 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2267 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2268
718da2b9 2269 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2270
2271 p_tcp_hdr->th_sum = 0;
2272
718da2b9 2273 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2274 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2275
2276 p_tcp_hdr->th_sum = tcp_checksum;
2277 }
718da2b9 2278 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320
FB		 2279 {
2280 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2281
718da2b9
FB		 2282 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2283 p_udpip_hdr->zeros = 0;
2284 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2285 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2286
718da2b9 2287 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2288
6cadb320
FB		 2289 p_udp_hdr->uh_sum = 0;
2290
718da2b9 2291 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2292 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2293
6cadb320
FB		 2294 p_udp_hdr->uh_sum = udp_checksum;
2295 }
2296
2297 /* restore IP header */
718da2b9 2298 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2299 }
2300 }
2301 }
2302
2303 /* update tally counter */
2304 ++s->tally_counters.TxOk;
2305
2306 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2307
718da2b9 2308 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
6cadb320
FB		 2309
2310 /* restore card space if there was no recursion and reset offset */
2311 if (!s->cplus_txbuffer)
2312 {
2313 s->cplus_txbuffer = saved_buffer;
2314 s->cplus_txbuffer_len = saved_buffer_len;
2315 s->cplus_txbuffer_offset = 0;
2316 }
2317 else
2318 {
2319 free(saved_buffer);
2320 }
a41b2ff2
PB		 2321 }
2322 else
2323 {
6cadb320 2324 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
a41b2ff2
PB		 2325 }
2326
a41b2ff2
PB		 2327 return 1;
2328}
2329
2330static void rtl8139_cplus_transmit(RTL8139State *s)
2331{
2332 int txcount = 0;
2333
2334 while (rtl8139_cplus_transmit_one(s))
2335 {
2336 ++txcount;
2337 }
2338
2339 /* Mark transfer completed */
2340 if (!txcount)
2341 {
6cadb320
FB		 2342 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2343 s->currCPlusTxDesc));
a41b2ff2
PB		 2344 }
2345 else
2346 {
2347 /* update interrupt status */
2348 s->IntrStatus |= TxOK;
2349 rtl8139_update_irq(s);
2350 }
2351}
2352
2353static void rtl8139_transmit(RTL8139State *s)
2354{
2355 int descriptor = s->currTxDesc, txcount = 0;
2356
2357 /*while*/
2358 if (rtl8139_transmit_one(s, descriptor))
2359 {
2360 ++s->currTxDesc;
2361 s->currTxDesc %= 4;
2362 ++txcount;
2363 }
2364
2365 /* Mark transfer completed */
2366 if (!txcount)
2367 {
6cadb320 2368 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
a41b2ff2
PB		 2369 }
2370}
2371
2372static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2373{
2374
2375 int descriptor = txRegOffset/4;
6cadb320
FB		 2376
2377 /* handle C+ transmit mode register configuration */
2378
2c3891ab 2379 if (s->cplus_enabled)
6cadb320
FB		 2380 {
2381 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2382
2383 /* handle Dump Tally Counters command */
2384 s->TxStatus[descriptor] = val;
2385
2386 if (descriptor == 0 && (val & 0x8))
2387 {
2388 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2389
2390 /* dump tally counters to specified memory location */
2391 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2392
2393 /* mark dump completed */
2394 s->TxStatus[0] &= ~0x8;
2395 }
2396
2397 return;
2398 }
2399
2400 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
a41b2ff2
PB		 2401
2402 /* mask only reserved bits */
2403 val &= ~0xff00c000; /* these bits are reset on write */
2404 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2405
2406 s->TxStatus[descriptor] = val;
2407
2408 /* attempt to start transmission */
2409 rtl8139_transmit(s);
2410}
2411
2412static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2413{
2414 uint32_t ret = s->TxStatus[txRegOffset/4];
2415
6cadb320 2416 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
a41b2ff2
PB		 2417
2418 return ret;
2419}
2420
2421static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2422{
2423 uint16_t ret = 0;
2424
2425 /* Simulate TSAD, it is read only anyway */
2426
2427 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2428 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2429 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2430 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2431
2432 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2433 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2434 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2435 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2436
a41b2ff2
PB		 2437 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2438 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2439 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2440 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2441
a41b2ff2
PB		 2442 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2443 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2444 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2445 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2446
a41b2ff2 2447
6cadb320 2448 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
a41b2ff2
PB		 2449
2450 return ret;
2451}
2452
2453static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2454{
2455 uint16_t ret = s->CSCR;
2456
6cadb320 2457 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
a41b2ff2
PB		 2458
2459 return ret;
2460}
2461
2462static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2463{
6cadb320 2464 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
a41b2ff2 2465
290a0933 2466 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2467}
2468
2469static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2470{
290a0933 2471 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2472
6cadb320 2473 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
a41b2ff2
PB		 2474
2475 return ret;
2476}
2477
2478static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2479{
6cadb320 2480 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
a41b2ff2
PB		 2481
2482 /* this value is off by 16 */
2483 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2484
6cadb320
FB		 2485 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2486 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 2487}
2488
2489static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2490{
2491 /* this value is off by 16 */
2492 uint32_t ret = s->RxBufPtr - 0x10;
2493
6cadb320
FB		 2494 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2495
2496 return ret;
2497}
2498
2499static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2500{
2501 /* this value is NOT off by 16 */
2502 uint32_t ret = s->RxBufAddr;
2503
2504 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
a41b2ff2
PB		 2505
2506 return ret;
2507}
2508
2509static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2510{
6cadb320 2511 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
a41b2ff2
PB		 2512
2513 s->RxBuf = val;
2514
2515 /* may need to reset rxring here */
2516}
2517
2518static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2519{
2520 uint32_t ret = s->RxBuf;
2521
6cadb320 2522 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
a41b2ff2
PB		 2523
2524 return ret;
2525}
2526
2527static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2528{
6cadb320 2529 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2530
2531 /* mask unwriteable bits */
2532 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2533
2534 s->IntrMask = val;
2535
2536 rtl8139_update_irq(s);
2537}
2538
2539static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2540{
2541 uint32_t ret = s->IntrMask;
2542
6cadb320 2543 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2544
2545 return ret;
2546}
2547
2548static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2549{
6cadb320 2550 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2551
2552#if 0
2553
2554 /* writing to ISR has no effect */
2555
2556 return;
2557
2558#else
2559 uint16_t newStatus = s->IntrStatus & ~val;
2560
2561 /* mask unwriteable bits */
2562 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2563
2564 /* writing 1 to interrupt status register bit clears it */
2565 s->IntrStatus = 0;
2566 rtl8139_update_irq(s);
2567
2568 s->IntrStatus = newStatus;
2569 rtl8139_update_irq(s);
2570#endif
2571}
2572
2573static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2574{
2575 uint32_t ret = s->IntrStatus;
2576
6cadb320 2577 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2578
2579#if 0
2580
2581 /* reading ISR clears all interrupts */
2582 s->IntrStatus = 0;
2583
2584 rtl8139_update_irq(s);
2585
2586#endif
2587
2588 return ret;
2589}
2590
2591static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2592{
6cadb320 2593 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2594
2595 /* mask unwriteable bits */
2596 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2597
2598 s->MultiIntr = val;
2599}
2600
2601static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2602{
2603 uint32_t ret = s->MultiIntr;
2604
6cadb320 2605 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2606
2607 return ret;
2608}
2609
2610static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2611{
2612 RTL8139State *s = opaque;
2613
2614 addr &= 0xff;
2615
2616 switch (addr)
2617 {
2618 case MAC0 ... MAC0+5:
2619 s->phys[addr - MAC0] = val;
2620 break;
2621 case MAC0+6 ... MAC0+7:
2622 /* reserved */
2623 break;
2624 case MAR0 ... MAR0+7:
2625 s->mult[addr - MAR0] = val;
2626 break;
2627 case ChipCmd:
2628 rtl8139_ChipCmd_write(s, val);
2629 break;
2630 case Cfg9346:
2631 rtl8139_Cfg9346_write(s, val);
2632 break;
2633 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2634 rtl8139_TxConfig_writeb(s, val);
2635 break;
2636 case Config0:
2637 rtl8139_Config0_write(s, val);
2638 break;
2639 case Config1:
2640 rtl8139_Config1_write(s, val);
2641 break;
2642 case Config3:
2643 rtl8139_Config3_write(s, val);
2644 break;
2645 case Config4:
2646 rtl8139_Config4_write(s, val);
2647 break;
2648 case Config5:
2649 rtl8139_Config5_write(s, val);
2650 break;
2651 case MediaStatus:
2652 /* ignore */
6cadb320 2653 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
a41b2ff2
PB		 2654 break;
2655
2656 case HltClk:
6cadb320 2657 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
a41b2ff2
PB		 2658 if (val == 'R')
2659 {
2660 s->clock_enabled = 1;
2661 }
2662 else if (val == 'H')
2663 {
2664 s->clock_enabled = 0;
2665 }
2666 break;
2667
2668 case TxThresh:
6cadb320 2669 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2670 s->TxThresh = val;
2671 break;
2672
2673 case TxPoll:
6cadb320 2674 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2675 if (val & (1 << 7))
2676 {
6cadb320 2677 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
a41b2ff2
PB		 2678 //rtl8139_cplus_transmit(s);
2679 }
2680 if (val & (1 << 6))
2681 {
6cadb320 2682 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
a41b2ff2
PB		 2683 rtl8139_cplus_transmit(s);
2684 }
2685
2686 break;
2687
2688 default:
6cadb320 2689 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
a41b2ff2
PB		 2690 break;
2691 }
2692}
2693
2694static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2695{
2696 RTL8139State *s = opaque;
2697
2698 addr &= 0xfe;
2699
2700 switch (addr)
2701 {
2702 case IntrMask:
2703 rtl8139_IntrMask_write(s, val);
2704 break;
2705
2706 case IntrStatus:
2707 rtl8139_IntrStatus_write(s, val);
2708 break;
2709
2710 case MultiIntr:
2711 rtl8139_MultiIntr_write(s, val);
2712 break;
2713
2714 case RxBufPtr:
2715 rtl8139_RxBufPtr_write(s, val);
2716 break;
2717
2718 case BasicModeCtrl:
2719 rtl8139_BasicModeCtrl_write(s, val);
2720 break;
2721 case BasicModeStatus:
2722 rtl8139_BasicModeStatus_write(s, val);
2723 break;
2724 case NWayAdvert:
6cadb320 2725 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2726 s->NWayAdvert = val;
2727 break;
2728 case NWayLPAR:
6cadb320 2729 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2730 break;
2731 case NWayExpansion:
6cadb320 2732 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2733 s->NWayExpansion = val;
2734 break;
2735
2736 case CpCmd:
2737 rtl8139_CpCmd_write(s, val);
2738 break;
2739
6cadb320
FB		 2740 case IntrMitigate:
2741 rtl8139_IntrMitigate_write(s, val);
2742 break;
2743
a41b2ff2 2744 default:
6cadb320 2745 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
a41b2ff2 2746
a41b2ff2
PB		 2747 rtl8139_io_writeb(opaque, addr, val & 0xff);
2748 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2749 break;
2750 }
2751}
2752
2753static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2754{
2755 RTL8139State *s = opaque;
2756
2757 addr &= 0xfc;
2758
2759 switch (addr)
2760 {
2761 case RxMissed:
6cadb320 2762 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
a41b2ff2
PB		 2763 s->RxMissed = 0;
2764 break;
2765
2766 case TxConfig:
2767 rtl8139_TxConfig_write(s, val);
2768 break;
2769
2770 case RxConfig:
2771 rtl8139_RxConfig_write(s, val);
2772 break;
2773
2774 case TxStatus0 ... TxStatus0+4*4-1:
2775 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2776 break;
2777
2778 case TxAddr0 ... TxAddr0+4*4-1:
2779 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2780 break;
2781
2782 case RxBuf:
2783 rtl8139_RxBuf_write(s, val);
2784 break;
2785
2786 case RxRingAddrLO:
6cadb320 2787 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
a41b2ff2
PB		 2788 s->RxRingAddrLO = val;
2789 break;
2790
2791 case RxRingAddrHI:
6cadb320 2792 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
a41b2ff2
PB		 2793 s->RxRingAddrHI = val;
2794 break;
2795
6cadb320
FB		 2796 case Timer:
2797 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2798 s->TCTR = 0;
2799 s->TCTR_base = qemu_get_clock(vm_clock);
2800 break;
2801
2802 case FlashReg:
2803 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2804 s->TimerInt = val;
2805 break;
2806
a41b2ff2 2807 default:
6cadb320 2808 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
a41b2ff2
PB		 2809 rtl8139_io_writeb(opaque, addr, val & 0xff);
2810 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2811 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2812 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2813 break;
2814 }
2815}
2816
2817static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2818{
2819 RTL8139State *s = opaque;
2820 int ret;
2821
2822 addr &= 0xff;
2823
2824 switch (addr)
2825 {
2826 case MAC0 ... MAC0+5:
2827 ret = s->phys[addr - MAC0];
2828 break;
2829 case MAC0+6 ... MAC0+7:
2830 ret = 0;
2831 break;
2832 case MAR0 ... MAR0+7:
2833 ret = s->mult[addr - MAR0];
2834 break;
2835 case ChipCmd:
2836 ret = rtl8139_ChipCmd_read(s);
2837 break;
2838 case Cfg9346:
2839 ret = rtl8139_Cfg9346_read(s);
2840 break;
2841 case Config0:
2842 ret = rtl8139_Config0_read(s);
2843 break;
2844 case Config1:
2845 ret = rtl8139_Config1_read(s);
2846 break;
2847 case Config3:
2848 ret = rtl8139_Config3_read(s);
2849 break;
2850 case Config4:
2851 ret = rtl8139_Config4_read(s);
2852 break;
2853 case Config5:
2854 ret = rtl8139_Config5_read(s);
2855 break;
2856
2857 case MediaStatus:
2858 ret = 0xd0;
6cadb320 2859 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
a41b2ff2
PB		 2860 break;
2861
2862 case HltClk:
2863 ret = s->clock_enabled;
6cadb320 2864 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
a41b2ff2
PB		 2865 break;
2866
2867 case PCIRevisionID:
6cadb320
FB		 2868 ret = RTL8139_PCI_REVID;
2869 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
a41b2ff2
PB		 2870 break;
2871
2872 case TxThresh:
2873 ret = s->TxThresh;
6cadb320 2874 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2875 break;
2876
2877 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2878 ret = s->TxConfig >> 24;
6cadb320 2879 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2880 break;
2881
2882 default:
6cadb320 2883 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
a41b2ff2
PB		 2884 ret = 0;
2885 break;
2886 }
2887
2888 return ret;
2889}
2890
2891static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2892{
2893 RTL8139State *s = opaque;
2894 uint32_t ret;
2895
2896 addr &= 0xfe; /* mask lower bit */
2897
2898 switch (addr)
2899 {
2900 case IntrMask:
2901 ret = rtl8139_IntrMask_read(s);
2902 break;
2903
2904 case IntrStatus:
2905 ret = rtl8139_IntrStatus_read(s);
2906 break;
2907
2908 case MultiIntr:
2909 ret = rtl8139_MultiIntr_read(s);
2910 break;
2911
2912 case RxBufPtr:
2913 ret = rtl8139_RxBufPtr_read(s);
2914 break;
2915
6cadb320
FB		 2916 case RxBufAddr:
2917 ret = rtl8139_RxBufAddr_read(s);
2918 break;
2919
a41b2ff2
PB		 2920 case BasicModeCtrl:
2921 ret = rtl8139_BasicModeCtrl_read(s);
2922 break;
2923 case BasicModeStatus:
2924 ret = rtl8139_BasicModeStatus_read(s);
2925 break;
2926 case NWayAdvert:
2927 ret = s->NWayAdvert;
6cadb320 2928 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2929 break;
2930 case NWayLPAR:
2931 ret = s->NWayLPAR;
6cadb320 2932 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2933 break;
2934 case NWayExpansion:
2935 ret = s->NWayExpansion;
6cadb320 2936 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2937 break;
2938
2939 case CpCmd:
2940 ret = rtl8139_CpCmd_read(s);
2941 break;
2942
6cadb320
FB		 2943 case IntrMitigate:
2944 ret = rtl8139_IntrMitigate_read(s);
2945 break;
2946
a41b2ff2
PB		 2947 case TxSummary:
2948 ret = rtl8139_TSAD_read(s);
2949 break;
2950
2951 case CSCR:
2952 ret = rtl8139_CSCR_read(s);
2953 break;
2954
2955 default:
6cadb320 2956 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
a41b2ff2 2957
a41b2ff2
PB		 2958 ret = rtl8139_io_readb(opaque, addr);
2959 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 2960
6cadb320 2961 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
a41b2ff2
PB		 2962 break;
2963 }
2964
2965 return ret;
2966}
2967
2968static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2969{
2970 RTL8139State *s = opaque;
2971 uint32_t ret;
2972
2973 addr &= 0xfc; /* also mask low 2 bits */
2974
2975 switch (addr)
2976 {
2977 case RxMissed:
2978 ret = s->RxMissed;
2979
6cadb320 2980 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
a41b2ff2
PB		 2981 break;
2982
2983 case TxConfig:
2984 ret = rtl8139_TxConfig_read(s);
2985 break;
2986
2987 case RxConfig:
2988 ret = rtl8139_RxConfig_read(s);
2989 break;
2990
2991 case TxStatus0 ... TxStatus0+4*4-1:
2992 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
2993 break;
2994
2995 case TxAddr0 ... TxAddr0+4*4-1:
2996 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
2997 break;
2998
2999 case RxBuf:
3000 ret = rtl8139_RxBuf_read(s);
3001 break;
3002
3003 case RxRingAddrLO:
3004 ret = s->RxRingAddrLO;
6cadb320 3005 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
a41b2ff2
PB		 3006 break;
3007
3008 case RxRingAddrHI:
3009 ret = s->RxRingAddrHI;
6cadb320
FB		 3010 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3011 break;
3012
3013 case Timer:
3014 ret = s->TCTR;
3015 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3016 break;
3017
3018 case FlashReg:
3019 ret = s->TimerInt;
3020 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
a41b2ff2
PB		 3021 break;
3022
3023 default:
6cadb320 3024 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
a41b2ff2 3025
a41b2ff2
PB		 3026 ret = rtl8139_io_readb(opaque, addr);
3027 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3028 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3029 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3030
6cadb320 3031 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
a41b2ff2
PB		 3032 break;
3033 }
3034
3035 return ret;
3036}
3037
3038/* */
3039
3040static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3041{
3042 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3043}
3044
3045static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3046{
3047 rtl8139_io_writew(opaque, addr & 0xFF, val);
3048}
3049
3050static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3051{
3052 rtl8139_io_writel(opaque, addr & 0xFF, val);
3053}
3054
3055static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3056{
3057 return rtl8139_io_readb(opaque, addr & 0xFF);
3058}
3059
3060static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3061{
3062 return rtl8139_io_readw(opaque, addr & 0xFF);
3063}
3064
3065static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3066{
3067 return rtl8139_io_readl(opaque, addr & 0xFF);
3068}
3069
3070/* */
3071
3072static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3073{
3074 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3075}
3076
3077static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3078{
5fedc612
AJ		 3079#ifdef TARGET_WORDS_BIGENDIAN
3080 val = bswap16(val);
3081#endif
a41b2ff2
PB		 3082 rtl8139_io_writew(opaque, addr & 0xFF, val);
3083}
3084
3085static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3086{
5fedc612
AJ		 3087#ifdef TARGET_WORDS_BIGENDIAN
3088 val = bswap32(val);
3089#endif
a41b2ff2
PB		 3090 rtl8139_io_writel(opaque, addr & 0xFF, val);
3091}
3092
3093static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3094{
3095 return rtl8139_io_readb(opaque, addr & 0xFF);
3096}
3097
3098static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3099{
5fedc612
AJ		 3100 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3101#ifdef TARGET_WORDS_BIGENDIAN
3102 val = bswap16(val);
3103#endif
3104 return val;
a41b2ff2
PB		 3105}
3106
3107static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3108{
5fedc612
AJ		 3109 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3110#ifdef TARGET_WORDS_BIGENDIAN
3111 val = bswap32(val);
3112#endif
3113 return val;
a41b2ff2
PB		 3114}
3115
3116/* */
3117
3118static void rtl8139_save(QEMUFile* f,void* opaque)
3119{
3120 RTL8139State* s=(RTL8139State*)opaque;
60fe76f3 3121 unsigned int i;
a41b2ff2 3122
1941d19c
FB		 3123 pci_device_save(s->pci_dev, f);
3124
a41b2ff2
PB		 3125 qemu_put_buffer(f, s->phys, 6);
3126 qemu_put_buffer(f, s->mult, 8);
3127
3128 for (i=0; i<4; ++i)
3129 {
3130 qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3131 }
3132 for (i=0; i<4; ++i)
3133 {
3134 qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3135 }
3136
3137 qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
3138 qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3139 qemu_put_be32s(f, &s->RxBufPtr);
3140 qemu_put_be32s(f, &s->RxBufAddr);
3141
3142 qemu_put_be16s(f, &s->IntrStatus);
3143 qemu_put_be16s(f, &s->IntrMask);
3144
3145 qemu_put_be32s(f, &s->TxConfig);
3146 qemu_put_be32s(f, &s->RxConfig);
3147 qemu_put_be32s(f, &s->RxMissed);
3148 qemu_put_be16s(f, &s->CSCR);
3149
3150 qemu_put_8s(f, &s->Cfg9346);
3151 qemu_put_8s(f, &s->Config0);
3152 qemu_put_8s(f, &s->Config1);
3153 qemu_put_8s(f, &s->Config3);
3154 qemu_put_8s(f, &s->Config4);
3155 qemu_put_8s(f, &s->Config5);
3156
3157 qemu_put_8s(f, &s->clock_enabled);
3158 qemu_put_8s(f, &s->bChipCmdState);
3159
3160 qemu_put_be16s(f, &s->MultiIntr);
3161
3162 qemu_put_be16s(f, &s->BasicModeCtrl);
3163 qemu_put_be16s(f, &s->BasicModeStatus);
3164 qemu_put_be16s(f, &s->NWayAdvert);
3165 qemu_put_be16s(f, &s->NWayLPAR);
3166 qemu_put_be16s(f, &s->NWayExpansion);
3167
3168 qemu_put_be16s(f, &s->CpCmd);
3169 qemu_put_8s(f, &s->TxThresh);
3170
80a34d67
PB		 3171 i = 0;
3172 qemu_put_be32s(f, &i); /* unused. */
a41b2ff2 3173 qemu_put_buffer(f, s->macaddr, 6);
bee8d684 3174 qemu_put_be32(f, s->rtl8139_mmio_io_addr);
a41b2ff2
PB		 3175
3176 qemu_put_be32s(f, &s->currTxDesc);
3177 qemu_put_be32s(f, &s->currCPlusRxDesc);
3178 qemu_put_be32s(f, &s->currCPlusTxDesc);
3179 qemu_put_be32s(f, &s->RxRingAddrLO);
3180 qemu_put_be32s(f, &s->RxRingAddrHI);
3181
3182 for (i=0; i<EEPROM_9346_SIZE; ++i)
3183 {
3184 qemu_put_be16s(f, &s->eeprom.contents[i]);
3185 }
bee8d684 3186 qemu_put_be32(f, s->eeprom.mode);
a41b2ff2
PB		 3187 qemu_put_be32s(f, &s->eeprom.tick);
3188 qemu_put_8s(f, &s->eeprom.address);
3189 qemu_put_be16s(f, &s->eeprom.input);
3190 qemu_put_be16s(f, &s->eeprom.output);
3191
3192 qemu_put_8s(f, &s->eeprom.eecs);
3193 qemu_put_8s(f, &s->eeprom.eesk);
3194 qemu_put_8s(f, &s->eeprom.eedi);
3195 qemu_put_8s(f, &s->eeprom.eedo);
6cadb320
FB		 3196
3197 qemu_put_be32s(f, &s->TCTR);
3198 qemu_put_be32s(f, &s->TimerInt);
bee8d684 3199 qemu_put_be64(f, s->TCTR_base);
6cadb320
FB		 3200
3201 RTL8139TallyCounters_save(f, &s->tally_counters);
2c3891ab
AL		 3202
3203 qemu_put_be32s(f, &s->cplus_enabled);
a41b2ff2
PB		 3204}
3205
3206static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
3207{
3208 RTL8139State* s=(RTL8139State*)opaque;
60fe76f3
TS		 3209 unsigned int i;
3210 int ret;
a41b2ff2 3211
6cadb320 3212 /* just 2 versions for now */
2c3891ab 3213 if (version_id > 4)
a41b2ff2
PB		 3214 return -EINVAL;
3215
1941d19c
FB		 3216 if (version_id >= 3) {
3217 ret = pci_device_load(s->pci_dev, f);
3218 if (ret < 0)
3219 return ret;
3220 }
3221
6cadb320 3222 /* saved since version 1 */
a41b2ff2
PB		 3223 qemu_get_buffer(f, s->phys, 6);
3224 qemu_get_buffer(f, s->mult, 8);
3225
3226 for (i=0; i<4; ++i)
3227 {
3228 qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3229 }
3230 for (i=0; i<4; ++i)
3231 {
3232 qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3233 }
3234
3235 qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
3236 qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3237 qemu_get_be32s(f, &s->RxBufPtr);
3238 qemu_get_be32s(f, &s->RxBufAddr);
3239
3240 qemu_get_be16s(f, &s->IntrStatus);
3241 qemu_get_be16s(f, &s->IntrMask);
3242
3243 qemu_get_be32s(f, &s->TxConfig);
3244 qemu_get_be32s(f, &s->RxConfig);
3245 qemu_get_be32s(f, &s->RxMissed);
3246 qemu_get_be16s(f, &s->CSCR);
3247
3248 qemu_get_8s(f, &s->Cfg9346);
3249 qemu_get_8s(f, &s->Config0);
3250 qemu_get_8s(f, &s->Config1);
3251 qemu_get_8s(f, &s->Config3);
3252 qemu_get_8s(f, &s->Config4);
3253 qemu_get_8s(f, &s->Config5);
3254
3255 qemu_get_8s(f, &s->clock_enabled);
3256 qemu_get_8s(f, &s->bChipCmdState);
3257
3258 qemu_get_be16s(f, &s->MultiIntr);
3259
3260 qemu_get_be16s(f, &s->BasicModeCtrl);
3261 qemu_get_be16s(f, &s->BasicModeStatus);
3262 qemu_get_be16s(f, &s->NWayAdvert);
3263 qemu_get_be16s(f, &s->NWayLPAR);
3264 qemu_get_be16s(f, &s->NWayExpansion);
3265
3266 qemu_get_be16s(f, &s->CpCmd);
3267 qemu_get_8s(f, &s->TxThresh);
3268
80a34d67 3269 qemu_get_be32s(f, &i); /* unused. */
a41b2ff2 3270 qemu_get_buffer(f, s->macaddr, 6);
bee8d684 3271 s->rtl8139_mmio_io_addr=qemu_get_be32(f);
a41b2ff2
PB		 3272
3273 qemu_get_be32s(f, &s->currTxDesc);
3274 qemu_get_be32s(f, &s->currCPlusRxDesc);
3275 qemu_get_be32s(f, &s->currCPlusTxDesc);
3276 qemu_get_be32s(f, &s->RxRingAddrLO);
3277 qemu_get_be32s(f, &s->RxRingAddrHI);
3278
3279 for (i=0; i<EEPROM_9346_SIZE; ++i)
3280 {
3281 qemu_get_be16s(f, &s->eeprom.contents[i]);
3282 }
bee8d684 3283 s->eeprom.mode=qemu_get_be32(f);
a41b2ff2
PB		 3284 qemu_get_be32s(f, &s->eeprom.tick);
3285 qemu_get_8s(f, &s->eeprom.address);
3286 qemu_get_be16s(f, &s->eeprom.input);
3287 qemu_get_be16s(f, &s->eeprom.output);
3288
3289 qemu_get_8s(f, &s->eeprom.eecs);
3290 qemu_get_8s(f, &s->eeprom.eesk);
3291 qemu_get_8s(f, &s->eeprom.eedi);
3292 qemu_get_8s(f, &s->eeprom.eedo);
3293
6cadb320
FB		 3294 /* saved since version 2 */
3295 if (version_id >= 2)
3296 {
3297 qemu_get_be32s(f, &s->TCTR);
3298 qemu_get_be32s(f, &s->TimerInt);
bee8d684 3299 s->TCTR_base=qemu_get_be64(f);
6cadb320
FB		 3300
3301 RTL8139TallyCounters_load(f, &s->tally_counters);
3302 }
3303 else
3304 {
3305 /* not saved, use default */
3306 s->TCTR = 0;
3307 s->TimerInt = 0;
3308 s->TCTR_base = 0;
3309
3310 RTL8139TallyCounters_clear(&s->tally_counters);
3311 }
3312
2c3891ab
AL		 3313 if (version_id >= 4) {
3314 qemu_get_be32s(f, &s->cplus_enabled);
3315 } else {
3316 s->cplus_enabled = s->CpCmd != 0;
3317 }
3318
a41b2ff2
PB		 3319 return 0;
3320}
3321
3322/***********************************************************/
3323/* PCI RTL8139 definitions */
3324
3325typedef struct PCIRTL8139State {
3326 PCIDevice dev;
3327 RTL8139State rtl8139;
3328} PCIRTL8139State;
3329
5fafdf24 3330static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
a41b2ff2
PB		 3331 uint32_t addr, uint32_t size, int type)
3332{
3333 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3334 RTL8139State *s = &d->rtl8139;
3335
3336 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3337}
3338
5fafdf24 3339static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
a41b2ff2
PB		 3340 uint32_t addr, uint32_t size, int type)
3341{
3342 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3343 RTL8139State *s = &d->rtl8139;
3344
3345 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3346 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3347
3348 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3349 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3350
3351 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3352 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3353}
3354
3355static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
3356 rtl8139_mmio_readb,
3357 rtl8139_mmio_readw,
3358 rtl8139_mmio_readl,
3359};
3360
3361static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
3362 rtl8139_mmio_writeb,
3363 rtl8139_mmio_writew,
3364 rtl8139_mmio_writel,
3365};
3366
6cadb320
FB		 3367static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3368{
5fafdf24 3369 int64_t next_time = current_time +
6cadb320
FB		 3370 muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
3371 if (next_time <= current_time)
3372 next_time = current_time + 1;
3373 return next_time;
3374}
3375
eb38c52c 3376#ifdef RTL8139_ONBOARD_TIMER
6cadb320
FB		 3377static void rtl8139_timer(void *opaque)
3378{
3379 RTL8139State *s = opaque;
3380
3381 int is_timeout = 0;
3382
3383 int64_t curr_time;
3384 uint32_t curr_tick;
3385
3386 if (!s->clock_enabled)
3387 {
3388 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3389 return;
3390 }
3391
3392 curr_time = qemu_get_clock(vm_clock);
3393
3394 curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
3395
3396 if (s->TimerInt && curr_tick >= s->TimerInt)
3397 {
3398 if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3399 {
3400 is_timeout = 1;
3401 }
3402 }
3403
3404 s->TCTR = curr_tick;
3405
3406// DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3407
3408 if (is_timeout)
3409 {
3410 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3411 s->IntrStatus |= PCSTimeout;
3412 rtl8139_update_irq(s);
3413 }
3414
5fafdf24 3415 qemu_mod_timer(s->timer,
6cadb320
FB		 3416 rtl8139_get_next_tctr_time(s,curr_time));
3417}
3418#endif /* RTL8139_ONBOARD_TIMER */
3419
b946a153
AL		 3420static void rtl8139_cleanup(VLANClientState *vc)
3421{
3422 RTL8139State *s = vc->opaque;
3423
3424 if (s->cplus_txbuffer) {
3425 qemu_free(s->cplus_txbuffer);
3426 s->cplus_txbuffer = NULL;
3427 }
3428
3429#ifdef RTL8139_ONBOARD_TIMER
3430 qemu_del_timer(s->timer);
3431 qemu_free_timer(s->timer);
3432#endif
3433
3434 unregister_savevm("rtl8139", s);
3435}
3436
3437static int pci_rtl8139_uninit(PCIDevice *dev)
3438{
3439 PCIRTL8139State *d = (PCIRTL8139State *)dev;
3440 RTL8139State *s = &d->rtl8139;
3441
3442 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
3443
3444 return 0;
3445}
3446
9d07d757 3447static void pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3448{
9d07d757 3449 PCIRTL8139State *d = (PCIRTL8139State *)dev;
a41b2ff2
PB		 3450 RTL8139State *s;
3451 uint8_t *pci_conf;
3b46e624 3452
b946a153 3453 d->dev.unregister = pci_rtl8139_uninit;
aff427a1 3454
a41b2ff2 3455 pci_conf = d->dev.config;
deb54399
AL		 3456 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3457 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
a41b2ff2 3458 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
6cadb320 3459 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
173a543b 3460 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
6407f373 3461 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */
a41b2ff2
PB		 3462 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3463 pci_conf[0x34] = 0xdc;
3464
3465 s = &d->rtl8139;
3466
3467 /* I/O handler for memory-mapped I/O */
3468 s->rtl8139_mmio_io_addr =
3469 cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
3470
5fafdf24 3471 pci_register_io_region(&d->dev, 0, 0x100,
a41b2ff2
PB		 3472 PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3473
5fafdf24 3474 pci_register_io_region(&d->dev, 1, 0x100,
a41b2ff2
PB		 3475 PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
3476
a41b2ff2 3477 s->pci_dev = (PCIDevice *)d;
9d07d757 3478 qdev_get_macaddr(&dev->qdev, s->macaddr);
a41b2ff2 3479 rtl8139_reset(s);
9d07d757 3480 s->vc = qdev_get_vlan_client(&dev->qdev,
463af534 3481 rtl8139_can_receive, rtl8139_receive, NULL,
b946a153 3482 rtl8139_cleanup, s);
a41b2ff2 3483
7cb7434b 3484 qemu_format_nic_info_str(s->vc, s->macaddr);
6cadb320
FB		 3485
3486 s->cplus_txbuffer = NULL;
3487 s->cplus_txbuffer_len = 0;
3488 s->cplus_txbuffer_offset = 0;
3b46e624 3489
2c3891ab 3490 register_savevm("rtl8139", -1, 4, rtl8139_save, rtl8139_load, s);
6cadb320 3491
eb38c52c 3492#ifdef RTL8139_ONBOARD_TIMER
6cadb320
FB		 3493 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3494
5fafdf24 3495 qemu_mod_timer(s->timer,
6cadb320
FB		 3496 rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3497#endif /* RTL8139_ONBOARD_TIMER */
a41b2ff2 3498}
9d07d757
PB		 3499
3500static void rtl8139_register_devices(void)
3501{
3502 pci_qdev_register("rtl8139", sizeof(PCIRTL8139State), pci_rtl8139_init);
3503}
3504
3505device_init(rtl8139_register_devices)
Qemu copy for testing