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rtl8139: use variadic macro for debug statements
[qemu.git] / hw / rtl8139.c
CommitLineData
a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f
BP		 51/* For crc32 */
52#include <zlib.h>
53
87ecb68b
PB		 54#include "hw.h"
55#include "pci.h"
56#include "qemu-timer.h"
57#include "net.h"
254111ec 58#include "loader.h"
1ca4d09a 59#include "sysemu.h"
bf6b87a8 60#include "iov.h"
a41b2ff2 61
a41b2ff2
PB		 62/* debug RTL8139 card */
63//#define DEBUG_RTL8139 1
64
6cadb320
FB		 65#define PCI_FREQUENCY 33000000L
66
a41b2ff2
PB		 67/* debug RTL8139 card C+ mode only */
68//#define DEBUG_RTL8139CP 1
69
a41b2ff2
PB		 70#define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73/* arg % size for size which is a power of 2 */
74#define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
18dabfd1
BP		 77#define ETHER_ADDR_LEN 6
78#define ETHER_TYPE_LEN 2
79#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
80#define ETH_P_IP 0x0800 /* Internet Protocol packet */
81#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
82#define ETH_MTU 1500
83
84#define VLAN_TCI_LEN 2
85#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
86
6cadb320 87#if defined (DEBUG_RTL8139)
7cdeb319
BP		 88# define DPRINTF(fmt, ...) \
89 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 90#else
7cdeb319 91# define DPRINTF(fmt, ...) do { } while (0)
6cadb320
FB		 92#endif
93
a41b2ff2
PB		 94/* Symbolic offsets to registers. */
95enum RTL8139_registers {
96 MAC0 = 0, /* Ethernet hardware address. */
97 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 98 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
99 /* Dump Tally Conter control register(64bit). C+ mode only */
100 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 101 RxBuf = 0x30,
102 ChipCmd = 0x37,
103 RxBufPtr = 0x38,
104 RxBufAddr = 0x3A,
105 IntrMask = 0x3C,
106 IntrStatus = 0x3E,
107 TxConfig = 0x40,
108 RxConfig = 0x44,
109 Timer = 0x48, /* A general-purpose counter. */
110 RxMissed = 0x4C, /* 24 bits valid, write clears. */
111 Cfg9346 = 0x50,
112 Config0 = 0x51,
113 Config1 = 0x52,
114 FlashReg = 0x54,
115 MediaStatus = 0x58,
116 Config3 = 0x59,
117 Config4 = 0x5A, /* absent on RTL-8139A */
118 HltClk = 0x5B,
119 MultiIntr = 0x5C,
120 PCIRevisionID = 0x5E,
121 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
122 BasicModeCtrl = 0x62,
123 BasicModeStatus = 0x64,
124 NWayAdvert = 0x66,
125 NWayLPAR = 0x68,
126 NWayExpansion = 0x6A,
127 /* Undocumented registers, but required for proper operation. */
128 FIFOTMS = 0x70, /* FIFO Control and test. */
129 CSCR = 0x74, /* Chip Status and Configuration Register. */
130 PARA78 = 0x78,
131 PARA7c = 0x7c, /* Magic transceiver parameter register. */
132 Config5 = 0xD8, /* absent on RTL-8139A */
133 /* C+ mode */
134 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
135 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
136 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
137 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
138 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
139 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
140 TxThresh = 0xEC, /* Early Tx threshold */
141};
142
143enum ClearBitMasks {
144 MultiIntrClear = 0xF000,
145 ChipCmdClear = 0xE2,
146 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
147};
148
149enum ChipCmdBits {
150 CmdReset = 0x10,
151 CmdRxEnb = 0x08,
152 CmdTxEnb = 0x04,
153 RxBufEmpty = 0x01,
154};
155
156/* C+ mode */
157enum CplusCmdBits {
6cadb320
FB		 158 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
159 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
160 CPlusRxEnb = 0x0002,
161 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 162};
163
164/* Interrupt register bits, using my own meaningful names. */
165enum IntrStatusBits {
166 PCIErr = 0x8000,
167 PCSTimeout = 0x4000,
168 RxFIFOOver = 0x40,
169 RxUnderrun = 0x20,
170 RxOverflow = 0x10,
171 TxErr = 0x08,
172 TxOK = 0x04,
173 RxErr = 0x02,
174 RxOK = 0x01,
175
176 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
177};
178
179enum TxStatusBits {
180 TxHostOwns = 0x2000,
181 TxUnderrun = 0x4000,
182 TxStatOK = 0x8000,
183 TxOutOfWindow = 0x20000000,
184 TxAborted = 0x40000000,
185 TxCarrierLost = 0x80000000,
186};
187enum RxStatusBits {
188 RxMulticast = 0x8000,
189 RxPhysical = 0x4000,
190 RxBroadcast = 0x2000,
191 RxBadSymbol = 0x0020,
192 RxRunt = 0x0010,
193 RxTooLong = 0x0008,
194 RxCRCErr = 0x0004,
195 RxBadAlign = 0x0002,
196 RxStatusOK = 0x0001,
197};
198
199/* Bits in RxConfig. */
200enum rx_mode_bits {
201 AcceptErr = 0x20,
202 AcceptRunt = 0x10,
203 AcceptBroadcast = 0x08,
204 AcceptMulticast = 0x04,
205 AcceptMyPhys = 0x02,
206 AcceptAllPhys = 0x01,
207};
208
209/* Bits in TxConfig. */
210enum tx_config_bits {
211
212 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
213 TxIFGShift = 24,
214 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
215 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
216 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
217 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
218
219 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
220 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
221 TxClearAbt = (1 << 0), /* Clear abort (WO) */
222 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
223 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
224
225 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
226};
227
228
229/* Transmit Status of All Descriptors (TSAD) Register */
230enum TSAD_bits {
231 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
232 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
233 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
234 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
235 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
236 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
237 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
238 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
239 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
240 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
241 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
242 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
243 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
244 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
245 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
246 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
247};
248
249
250/* Bits in Config1 */
251enum Config1Bits {
252 Cfg1_PM_Enable = 0x01,
253 Cfg1_VPD_Enable = 0x02,
254 Cfg1_PIO = 0x04,
255 Cfg1_MMIO = 0x08,
256 LWAKE = 0x10, /* not on 8139, 8139A */
257 Cfg1_Driver_Load = 0x20,
258 Cfg1_LED0 = 0x40,
259 Cfg1_LED1 = 0x80,
260 SLEEP = (1 << 1), /* only on 8139, 8139A */
261 PWRDN = (1 << 0), /* only on 8139, 8139A */
262};
263
264/* Bits in Config3 */
265enum Config3Bits {
266 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
267 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
268 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
269 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
270 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
271 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
272 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
273 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
274};
275
276/* Bits in Config4 */
277enum Config4Bits {
278 LWPTN = (1 << 2), /* not on 8139, 8139A */
279};
280
281/* Bits in Config5 */
282enum Config5Bits {
283 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
284 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
285 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
286 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
287 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
288 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
289 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
290};
291
292enum RxConfigBits {
293 /* rx fifo threshold */
294 RxCfgFIFOShift = 13,
295 RxCfgFIFONone = (7 << RxCfgFIFOShift),
296
297 /* Max DMA burst */
298 RxCfgDMAShift = 8,
299 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
300
301 /* rx ring buffer length */
302 RxCfgRcv8K = 0,
303 RxCfgRcv16K = (1 << 11),
304 RxCfgRcv32K = (1 << 12),
305 RxCfgRcv64K = (1 << 11) | (1 << 12),
306
307 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
308 RxNoWrap = (1 << 7),
309};
310
311/* Twister tuning parameters from RealTek.
312 Completely undocumented, but required to tune bad links on some boards. */
313/*
314enum CSCRBits {
315 CSCR_LinkOKBit = 0x0400,
316 CSCR_LinkChangeBit = 0x0800,
317 CSCR_LinkStatusBits = 0x0f000,
318 CSCR_LinkDownOffCmd = 0x003c0,
319 CSCR_LinkDownCmd = 0x0f3c0,
320*/
321enum CSCRBits {
5fafdf24 322 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 323 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
324 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
325 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 326 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 327 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
328 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
329 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
330 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
331};
332
333enum Cfg9346Bits {
334 Cfg9346_Lock = 0x00,
335 Cfg9346_Unlock = 0xC0,
336};
337
338typedef enum {
339 CH_8139 = 0,
340 CH_8139_K,
341 CH_8139A,
342 CH_8139A_G,
343 CH_8139B,
344 CH_8130,
345 CH_8139C,
346 CH_8100,
347 CH_8100B_8139D,
348 CH_8101,
c227f099 349} chip_t;
a41b2ff2
PB		 350
351enum chip_flags {
352 HasHltClk = (1 << 0),
353 HasLWake = (1 << 1),
354};
355
356#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
357 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
358#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
359
6cadb320
FB		 360#define RTL8139_PCI_REVID_8139 0x10
361#define RTL8139_PCI_REVID_8139CPLUS 0x20
362
363#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
364
a41b2ff2
PB		 365/* Size is 64 * 16bit words */
366#define EEPROM_9346_ADDR_BITS 6
367#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
368#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
369
370enum Chip9346Operation
371{
372 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
373 Chip9346_op_read = 0x80, /* 10 AAAAAA */
374 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
375 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
376 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
377 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
378 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
379};
380
381enum Chip9346Mode
382{
383 Chip9346_none = 0,
384 Chip9346_enter_command_mode,
385 Chip9346_read_command,
386 Chip9346_data_read, /* from output register */
387 Chip9346_data_write, /* to input register, then to contents at specified address */
388 Chip9346_data_write_all, /* to input register, then filling contents */
389};
390
391typedef struct EEprom9346
392{
393 uint16_t contents[EEPROM_9346_SIZE];
394 int mode;
395 uint32_t tick;
396 uint8_t address;
397 uint16_t input;
398 uint16_t output;
399
400 uint8_t eecs;
401 uint8_t eesk;
402 uint8_t eedi;
403 uint8_t eedo;
404} EEprom9346;
405
6cadb320
FB		 406typedef struct RTL8139TallyCounters
407{
408 /* Tally counters */
409 uint64_t TxOk;
410 uint64_t RxOk;
411 uint64_t TxERR;
412 uint32_t RxERR;
413 uint16_t MissPkt;
414 uint16_t FAE;
415 uint32_t Tx1Col;
416 uint32_t TxMCol;
417 uint64_t RxOkPhy;
418 uint64_t RxOkBrd;
419 uint32_t RxOkMul;
420 uint16_t TxAbt;
421 uint16_t TxUndrn;
422} RTL8139TallyCounters;
423
424/* Clears all tally counters */
425static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
426
427/* Writes tally counters to specified physical memory address */
c227f099 428static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
6cadb320 429
a41b2ff2 430typedef struct RTL8139State {
efd6dd45 431 PCIDevice dev;
a41b2ff2
PB		 432 uint8_t phys[8]; /* mac address */
433 uint8_t mult[8]; /* multicast mask array */
434
6cadb320 435 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 436 uint32_t TxAddr[4]; /* TxAddr0 */
437 uint32_t RxBuf; /* Receive buffer */
438 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
439 uint32_t RxBufPtr;
440 uint32_t RxBufAddr;
441
442 uint16_t IntrStatus;
443 uint16_t IntrMask;
444
445 uint32_t TxConfig;
446 uint32_t RxConfig;
447 uint32_t RxMissed;
448
449 uint16_t CSCR;
450
451 uint8_t Cfg9346;
452 uint8_t Config0;
453 uint8_t Config1;
454 uint8_t Config3;
455 uint8_t Config4;
456 uint8_t Config5;
457
458 uint8_t clock_enabled;
459 uint8_t bChipCmdState;
460
461 uint16_t MultiIntr;
462
463 uint16_t BasicModeCtrl;
464 uint16_t BasicModeStatus;
465 uint16_t NWayAdvert;
466 uint16_t NWayLPAR;
467 uint16_t NWayExpansion;
468
469 uint16_t CpCmd;
470 uint8_t TxThresh;
471
1673ad51 472 NICState *nic;
254111ec 473 NICConf conf;
a41b2ff2
PB		 474 int rtl8139_mmio_io_addr;
475
476 /* C ring mode */
477 uint32_t currTxDesc;
478
479 /* C+ mode */
2c3891ab
AL		 480 uint32_t cplus_enabled;
481
a41b2ff2
PB		 482 uint32_t currCPlusRxDesc;
483 uint32_t currCPlusTxDesc;
484
485 uint32_t RxRingAddrLO;
486 uint32_t RxRingAddrHI;
487
488 EEprom9346 eeprom;
6cadb320
FB		 489
490 uint32_t TCTR;
491 uint32_t TimerInt;
492 int64_t TCTR_base;
493
494 /* Tally counters */
495 RTL8139TallyCounters tally_counters;
496
497 /* Non-persistent data */
498 uint8_t *cplus_txbuffer;
499 int cplus_txbuffer_len;
500 int cplus_txbuffer_offset;
501
502 /* PCI interrupt timer */
503 QEMUTimer *timer;
05447803 504 int64_t TimerExpire;
6cadb320 505
c574ba5a
AW		 506 /* Support migration to/from old versions */
507 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 508} RTL8139State;
509
05447803
FZ		 510static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
511
9596ebb7 512static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 513{
7cdeb319 514 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 515
516 switch (command & Chip9346_op_mask)
517 {
518 case Chip9346_op_read:
519 {
520 eeprom->address = command & EEPROM_9346_ADDR_MASK;
521 eeprom->output = eeprom->contents[eeprom->address];
522 eeprom->eedo = 0;
523 eeprom->tick = 0;
524 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 525 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
526 eeprom->address, eeprom->output);
a41b2ff2
PB		 527 }
528 break;
529
530 case Chip9346_op_write:
531 {
532 eeprom->address = command & EEPROM_9346_ADDR_MASK;
533 eeprom->input = 0;
534 eeprom->tick = 0;
535 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 536 DPRINTF("eeprom begin write to address 0x%02x\n",
537 eeprom->address);
a41b2ff2
PB		 538 }
539 break;
540 default:
541 eeprom->mode = Chip9346_none;
542 switch (command & Chip9346_op_ext_mask)
543 {
544 case Chip9346_op_write_enable:
7cdeb319 545 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 546 break;
547 case Chip9346_op_write_all:
7cdeb319 548 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 549 break;
550 case Chip9346_op_write_disable:
7cdeb319 551 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 552 break;
553 }
554 break;
555 }
556}
557
9596ebb7 558static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 559{
560 int bit = eeprom->eedi?1:0;
561
562 ++ eeprom->tick;
563
7cdeb319
BP		 564 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
565 eeprom->eedo);
a41b2ff2
PB		 566
567 switch (eeprom->mode)
568 {
569 case Chip9346_enter_command_mode:
570 if (bit)
571 {
572 eeprom->mode = Chip9346_read_command;
573 eeprom->tick = 0;
574 eeprom->input = 0;
7cdeb319 575 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 576 }
577 break;
578
579 case Chip9346_read_command:
580 eeprom->input = (eeprom->input << 1) | (bit & 1);
581 if (eeprom->tick == 8)
582 {
583 prom9346_decode_command(eeprom, eeprom->input & 0xff);
584 }
585 break;
586
587 case Chip9346_data_read:
588 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
589 eeprom->output <<= 1;
590 if (eeprom->tick == 16)
591 {
6cadb320
FB		 592#if 1
593 // the FreeBSD drivers (rl and re) don't explicitly toggle
594 // CS between reads (or does setting Cfg9346 to 0 count too?),
595 // so we need to enter wait-for-command state here
596 eeprom->mode = Chip9346_enter_command_mode;
597 eeprom->input = 0;
598 eeprom->tick = 0;
599
7cdeb319 600 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 601#else
602 // original behaviour
a41b2ff2
PB		 603 ++eeprom->address;
604 eeprom->address &= EEPROM_9346_ADDR_MASK;
605 eeprom->output = eeprom->contents[eeprom->address];
606 eeprom->tick = 0;
607
7cdeb319
BP		 608 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
609 eeprom->address, eeprom->output);
a41b2ff2
PB		 610#endif
611 }
612 break;
613
614 case Chip9346_data_write:
615 eeprom->input = (eeprom->input << 1) | (bit & 1);
616 if (eeprom->tick == 16)
617 {
7cdeb319
BP		 618 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
619 eeprom->address, eeprom->input);
6cadb320 620
a41b2ff2
PB		 621 eeprom->contents[eeprom->address] = eeprom->input;
622 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
623 eeprom->tick = 0;
624 eeprom->input = 0;
625 }
626 break;
627
628 case Chip9346_data_write_all:
629 eeprom->input = (eeprom->input << 1) | (bit & 1);
630 if (eeprom->tick == 16)
631 {
632 int i;
633 for (i = 0; i < EEPROM_9346_SIZE; i++)
634 {
635 eeprom->contents[i] = eeprom->input;
636 }
7cdeb319 637 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 638
a41b2ff2
PB		 639 eeprom->mode = Chip9346_enter_command_mode;
640 eeprom->tick = 0;
641 eeprom->input = 0;
642 }
643 break;
644
645 default:
646 break;
647 }
648}
649
9596ebb7 650static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 651{
652 EEprom9346 *eeprom = &s->eeprom;
653 if (!eeprom->eecs)
654 return 0;
655
656 return eeprom->eedo;
657}
658
9596ebb7
PB		 659/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
660static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 661{
662 EEprom9346 *eeprom = &s->eeprom;
663 uint8_t old_eecs = eeprom->eecs;
664 uint8_t old_eesk = eeprom->eesk;
665
666 eeprom->eecs = eecs;
667 eeprom->eesk = eesk;
668 eeprom->eedi = eedi;
669
7cdeb319
BP		 670 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
671 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 672
673 if (!old_eecs && eecs)
674 {
675 /* Synchronize start */
676 eeprom->tick = 0;
677 eeprom->input = 0;
678 eeprom->output = 0;
679 eeprom->mode = Chip9346_enter_command_mode;
680
7cdeb319 681 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 682 }
683
684 if (!eecs)
685 {
7cdeb319 686 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 687 return;
688 }
689
690 if (!old_eesk && eesk)
691 {
692 /* SK front rules */
693 prom9346_shift_clock(eeprom);
694 }
695}
696
697static void rtl8139_update_irq(RTL8139State *s)
698{
699 int isr;
700 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 701
7cdeb319
BP		 702 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
703 s->IntrMask);
6cadb320 704
efd6dd45 705 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 706}
707
708#define POLYNOMIAL 0x04c11db6
709
710/* From FreeBSD */
711/* XXX: optimize */
712static int compute_mcast_idx(const uint8_t *ep)
713{
714 uint32_t crc;
715 int carry, i, j;
716 uint8_t b;
717
718 crc = 0xffffffff;
719 for (i = 0; i < 6; i++) {
720 b = *ep++;
721 for (j = 0; j < 8; j++) {
722 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
723 crc <<= 1;
724 b >>= 1;
725 if (carry)
726 crc = ((crc ^ POLYNOMIAL) | carry);
727 }
728 }
729 return (crc >> 26);
730}
731
732static int rtl8139_RxWrap(RTL8139State *s)
733{
734 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
735 return (s->RxConfig & (1 << 7));
736}
737
738static int rtl8139_receiver_enabled(RTL8139State *s)
739{
740 return s->bChipCmdState & CmdRxEnb;
741}
742
743static int rtl8139_transmitter_enabled(RTL8139State *s)
744{
745 return s->bChipCmdState & CmdTxEnb;
746}
747
748static int rtl8139_cp_receiver_enabled(RTL8139State *s)
749{
750 return s->CpCmd & CPlusRxEnb;
751}
752
753static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
754{
755 return s->CpCmd & CPlusTxEnb;
756}
757
758static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
759{
760 if (s->RxBufAddr + size > s->RxBufferSize)
761 {
762 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
763
764 /* write packet data */
ccf1d14a 765 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 766 {
7cdeb319 767 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 768
769 if (size > wrapped)
770 {
771 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
772 buf, size-wrapped );
773 }
774
775 /* reset buffer pointer */
776 s->RxBufAddr = 0;
777
778 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
779 buf + (size-wrapped), wrapped );
780
781 s->RxBufAddr = wrapped;
782
783 return;
784 }
785 }
786
787 /* non-wrapping path or overwrapping enabled */
788 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
789
790 s->RxBufAddr += size;
791}
792
793#define MIN_BUF_SIZE 60
c227f099 794static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 795{
796#if TARGET_PHYS_ADDR_BITS > 32
c227f099 797 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 798#else
799 return low;
800#endif
801}
802
1673ad51 803static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 804{
1673ad51 805 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 806 int avail;
807
aa1f17c1 808 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 809 if (!s->clock_enabled)
810 return 1;
811 if (!rtl8139_receiver_enabled(s))
812 return 1;
813
814 if (rtl8139_cp_receiver_enabled(s)) {
815 /* ??? Flow control not implemented in c+ mode.
816 This is a hack to work around slirp deficiencies anyway. */
817 return 1;
818 } else {
819 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
820 s->RxBufferSize);
821 return (avail == 0 || avail >= 1514);
822 }
823}
824
1673ad51 825static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 826{
1673ad51 827 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
18dabfd1 828 /* size is the length of the buffer passed to the driver */
4f1c942b 829 int size = size_;
18dabfd1 830 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 831
832 uint32_t packet_header = 0;
833
18dabfd1 834 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 835 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 836 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
837
7cdeb319 838 DPRINTF(">>> received len=%d\n", size);
a41b2ff2
PB		 839
840 /* test if board clock is stopped */
841 if (!s->clock_enabled)
842 {
7cdeb319 843 DPRINTF("stopped ==========================\n");
4f1c942b 844 return -1;
a41b2ff2
PB		 845 }
846
847 /* first check if receiver is enabled */
848
849 if (!rtl8139_receiver_enabled(s))
850 {
7cdeb319 851 DPRINTF("receiver disabled ================\n");
4f1c942b 852 return -1;
a41b2ff2
PB		 853 }
854
855 /* XXX: check this */
856 if (s->RxConfig & AcceptAllPhys) {
857 /* promiscuous: receive all */
7cdeb319 858 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 859
860 } else {
861 if (!memcmp(buf, broadcast_macaddr, 6)) {
862 /* broadcast address */
863 if (!(s->RxConfig & AcceptBroadcast))
864 {
7cdeb319 865 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 866
867 /* update tally counter */
868 ++s->tally_counters.RxERR;
869
4f1c942b 870 return size;
a41b2ff2
PB		 871 }
872
873 packet_header |= RxBroadcast;
874
7cdeb319 875 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 876
877 /* update tally counter */
878 ++s->tally_counters.RxOkBrd;
879
a41b2ff2
PB		 880 } else if (buf[0] & 0x01) {
881 /* multicast */
882 if (!(s->RxConfig & AcceptMulticast))
883 {
7cdeb319 884 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 885
886 /* update tally counter */
887 ++s->tally_counters.RxERR;
888
4f1c942b 889 return size;
a41b2ff2
PB		 890 }
891
892 int mcast_idx = compute_mcast_idx(buf);
893
894 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
895 {
7cdeb319 896 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 897
898 /* update tally counter */
899 ++s->tally_counters.RxERR;
900
4f1c942b 901 return size;
a41b2ff2
PB		 902 }
903
904 packet_header |= RxMulticast;
905
7cdeb319 906 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 907
908 /* update tally counter */
909 ++s->tally_counters.RxOkMul;
910
a41b2ff2 911 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 912 s->phys[1] == buf[1] &&
913 s->phys[2] == buf[2] &&
914 s->phys[3] == buf[3] &&
915 s->phys[4] == buf[4] &&
a41b2ff2
PB		 916 s->phys[5] == buf[5]) {
917 /* match */
918 if (!(s->RxConfig & AcceptMyPhys))
919 {
7cdeb319 920 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 921
922 /* update tally counter */
923 ++s->tally_counters.RxERR;
924
4f1c942b 925 return size;
a41b2ff2
PB		 926 }
927
928 packet_header |= RxPhysical;
929
7cdeb319 930 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 931
932 /* update tally counter */
933 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 934
935 } else {
936
7cdeb319 937 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 938
939 /* update tally counter */
940 ++s->tally_counters.RxERR;
941
4f1c942b 942 return size;
a41b2ff2
PB		 943 }
944 }
945
18dabfd1
BP		 946 /* if too small buffer, then expand it
947 * Include some tailroom in case a vlan tag is later removed. */
948 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 949 memcpy(buf1, buf, size);
18dabfd1 950 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 951 buf = buf1;
18dabfd1
BP		 952 if (size < MIN_BUF_SIZE) {
953 size = MIN_BUF_SIZE;
954 }
a41b2ff2
PB		 955 }
956
957 if (rtl8139_cp_receiver_enabled(s))
958 {
7cdeb319 959 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 960
961 /* begin C+ receiver mode */
962
963/* w0 ownership flag */
964#define CP_RX_OWN (1<<31)
965/* w0 end of ring flag */
966#define CP_RX_EOR (1<<30)
967/* w0 bits 0...12 : buffer size */
968#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
969/* w1 tag available flag */
970#define CP_RX_TAVA (1<<16)
971/* w1 bits 0...15 : VLAN tag */
972#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
973/* w2 low 32bit of Rx buffer ptr */
974/* w3 high 32bit of Rx buffer ptr */
975
976 int descriptor = s->currCPlusRxDesc;
c227f099 977 target_phys_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 978
979 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
980 cplus_rx_ring_desc += 16 * descriptor;
981
7cdeb319
BP		 982 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
983 "%08x %08x = "TARGET_FMT_plx"\n", descriptor, s->RxRingAddrHI,
984 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 985
986 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
987
988 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
989 rxdw0 = le32_to_cpu(val);
990 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
991 rxdw1 = le32_to_cpu(val);
992 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
993 rxbufLO = le32_to_cpu(val);
994 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
995 rxbufHI = le32_to_cpu(val);
996
7cdeb319
BP		 997 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
998 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 999
1000 if (!(rxdw0 & CP_RX_OWN))
1001 {
7cdeb319
BP		 1002 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1003 descriptor);
6cadb320 1004
a41b2ff2
PB		 1005 s->IntrStatus |= RxOverflow;
1006 ++s->RxMissed;
6cadb320
FB		 1007
1008 /* update tally counter */
1009 ++s->tally_counters.RxERR;
1010 ++s->tally_counters.MissPkt;
1011
a41b2ff2 1012 rtl8139_update_irq(s);
4f1c942b 1013 return size_;
a41b2ff2
PB		 1014 }
1015
1016 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1017
18dabfd1
BP		 1018 /* write VLAN info to descriptor variables. */
1019 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1020 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1021 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1022 size -= VLAN_HLEN;
1023 /* if too small buffer, use the tailroom added duing expansion */
1024 if (size < MIN_BUF_SIZE) {
1025 size = MIN_BUF_SIZE;
1026 }
1027
1028 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1029 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1030 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1031 &dot1q_buf[ETHER_TYPE_LEN]);
1032
7cdeb319
BP		 1033 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1034 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1035 } else {
1036 /* reset VLAN tag flag */
1037 rxdw1 &= ~CP_RX_TAVA;
1038 }
1039
6cadb320
FB		 1040 /* TODO: scatter the packet over available receive ring descriptors space */
1041
a41b2ff2
PB		 1042 if (size+4 > rx_space)
1043 {
7cdeb319
BP		 1044 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1045 descriptor, rx_space, size);
6cadb320 1046
a41b2ff2
PB		 1047 s->IntrStatus |= RxOverflow;
1048 ++s->RxMissed;
6cadb320
FB		 1049
1050 /* update tally counter */
1051 ++s->tally_counters.RxERR;
1052 ++s->tally_counters.MissPkt;
1053
a41b2ff2 1054 rtl8139_update_irq(s);
4f1c942b 1055 return size_;
a41b2ff2
PB		 1056 }
1057
c227f099 1058 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1059
1060 /* receive/copy to target memory */
18dabfd1
BP		 1061 if (dot1q_buf) {
1062 cpu_physical_memory_write(rx_addr, buf, 2 * ETHER_ADDR_LEN);
1063 cpu_physical_memory_write(rx_addr + 2 * ETHER_ADDR_LEN,
1064 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1065 size - 2 * ETHER_ADDR_LEN);
1066 } else {
1067 cpu_physical_memory_write(rx_addr, buf, size);
1068 }
a41b2ff2 1069
6cadb320
FB		 1070 if (s->CpCmd & CPlusRxChkSum)
1071 {
1072 /* do some packet checksumming */
1073 }
1074
a41b2ff2 1075 /* write checksum */
18dabfd1 1076 val = cpu_to_le32(crc32(0, buf, size_));
a41b2ff2
PB		 1077 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1078
1079/* first segment of received packet flag */
1080#define CP_RX_STATUS_FS (1<<29)
1081/* last segment of received packet flag */
1082#define CP_RX_STATUS_LS (1<<28)
1083/* multicast packet flag */
1084#define CP_RX_STATUS_MAR (1<<26)
1085/* physical-matching packet flag */
1086#define CP_RX_STATUS_PAM (1<<25)
1087/* broadcast packet flag */
1088#define CP_RX_STATUS_BAR (1<<24)
1089/* runt packet flag */
1090#define CP_RX_STATUS_RUNT (1<<19)
1091/* crc error flag */
1092#define CP_RX_STATUS_CRC (1<<18)
1093/* IP checksum error flag */
1094#define CP_RX_STATUS_IPF (1<<15)
1095/* UDP checksum error flag */
1096#define CP_RX_STATUS_UDPF (1<<14)
1097/* TCP checksum error flag */
1098#define CP_RX_STATUS_TCPF (1<<13)
1099
1100 /* transfer ownership to target */
1101 rxdw0 &= ~CP_RX_OWN;
1102
1103 /* set first segment bit */
1104 rxdw0 |= CP_RX_STATUS_FS;
1105
1106 /* set last segment bit */
1107 rxdw0 |= CP_RX_STATUS_LS;
1108
1109 /* set received packet type flags */
1110 if (packet_header & RxBroadcast)
1111 rxdw0 |= CP_RX_STATUS_BAR;
1112 if (packet_header & RxMulticast)
1113 rxdw0 |= CP_RX_STATUS_MAR;
1114 if (packet_header & RxPhysical)
1115 rxdw0 |= CP_RX_STATUS_PAM;
1116
1117 /* set received size */
1118 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1119 rxdw0 |= (size+4);
1120
a41b2ff2
PB		 1121 /* update ring data */
1122 val = cpu_to_le32(rxdw0);
1123 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1124 val = cpu_to_le32(rxdw1);
1125 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1126
6cadb320
FB		 1127 /* update tally counter */
1128 ++s->tally_counters.RxOk;
1129
a41b2ff2
PB		 1130 /* seek to next Rx descriptor */
1131 if (rxdw0 & CP_RX_EOR)
1132 {
1133 s->currCPlusRxDesc = 0;
1134 }
1135 else
1136 {
1137 ++s->currCPlusRxDesc;
1138 }
1139
7cdeb319 1140 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1141
1142 }
1143 else
1144 {
7cdeb319 1145 DPRINTF("in ring Rx mode ================\n");
6cadb320 1146
a41b2ff2
PB		 1147 /* begin ring receiver mode */
1148 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1149
1150 /* if receiver buffer is empty then avail == 0 */
1151
1152 if (avail != 0 && size + 8 >= avail)
1153 {
7cdeb319
BP		 1154 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1155 "read 0x%04x === available 0x%04x need 0x%04x\n",
1156 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1157
a41b2ff2
PB		 1158 s->IntrStatus |= RxOverflow;
1159 ++s->RxMissed;
1160 rtl8139_update_irq(s);
4f1c942b 1161 return size_;
a41b2ff2
PB		 1162 }
1163
1164 packet_header |= RxStatusOK;
1165
1166 packet_header |= (((size+4) << 16) & 0xffff0000);
1167
1168 /* write header */
1169 uint32_t val = cpu_to_le32(packet_header);
1170
1171 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1172
1173 rtl8139_write_buffer(s, buf, size);
1174
1175 /* write checksum */
ccf1d14a 1176 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1177 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1178
1179 /* correct buffer write pointer */
1180 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1181
1182 /* now we can signal we have received something */
1183
7cdeb319
BP		 1184 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1185 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1186 }
1187
1188 s->IntrStatus |= RxOK;
6cadb320
FB		 1189
1190 if (do_interrupt)
1191 {
1192 rtl8139_update_irq(s);
1193 }
4f1c942b
MM		 1194
1195 return size_;
6cadb320
FB		 1196}
1197
1673ad51 1198static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1199{
1673ad51 1200 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1201}
1202
1203static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1204{
1205 s->RxBufferSize = bufferSize;
1206 s->RxBufPtr = 0;
1207 s->RxBufAddr = 0;
1208}
1209
7f23f812 1210static void rtl8139_reset(DeviceState *d)
a41b2ff2 1211{
7f23f812 1212 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1213 int i;
1214
1215 /* restore MAC address */
254111ec 1216 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1217
1218 /* reset interrupt mask */
1219 s->IntrStatus = 0;
1220 s->IntrMask = 0;
1221
1222 rtl8139_update_irq(s);
1223
a41b2ff2
PB		 1224 /* mark all status registers as owned by host */
1225 for (i = 0; i < 4; ++i)
1226 {
1227 s->TxStatus[i] = TxHostOwns;
1228 }
1229
1230 s->currTxDesc = 0;
1231 s->currCPlusRxDesc = 0;
1232 s->currCPlusTxDesc = 0;
1233
1234 s->RxRingAddrLO = 0;
1235 s->RxRingAddrHI = 0;
1236
1237 s->RxBuf = 0;
1238
1239 rtl8139_reset_rxring(s, 8192);
1240
1241 /* ACK the reset */
1242 s->TxConfig = 0;
1243
1244#if 0
1245// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1246 s->clock_enabled = 0;
1247#else
6cadb320 1248 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1249 s->clock_enabled = 1;
1250#endif
1251
1252 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1253
1254 /* set initial state data */
1255 s->Config0 = 0x0; /* No boot ROM */
1256 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1257 s->Config3 = 0x1; /* fast back-to-back compatible */
1258 s->Config5 = 0x0;
1259
5fafdf24 1260 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1261
1262 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1263 s->cplus_enabled = 0;
1264
a41b2ff2
PB		 1265
1266// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1267// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1268 s->BasicModeCtrl = 0x1000; // autonegotiation
1269
1270 s->BasicModeStatus = 0x7809;
1271 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1272 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1273 s->BasicModeStatus |= 0x0004; /* link is up */
1274
1275 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1276 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1277 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1278
1279 /* also reset timer and disable timer interrupt */
1280 s->TCTR = 0;
1281 s->TimerInt = 0;
1282 s->TCTR_base = 0;
1283
1284 /* reset tally counters */
1285 RTL8139TallyCounters_clear(&s->tally_counters);
1286}
1287
b1d8e52e 1288static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1289{
1290 counters->TxOk = 0;
1291 counters->RxOk = 0;
1292 counters->TxERR = 0;
1293 counters->RxERR = 0;
1294 counters->MissPkt = 0;
1295 counters->FAE = 0;
1296 counters->Tx1Col = 0;
1297 counters->TxMCol = 0;
1298 counters->RxOkPhy = 0;
1299 counters->RxOkBrd = 0;
1300 counters->RxOkMul = 0;
1301 counters->TxAbt = 0;
1302 counters->TxUndrn = 0;
1303}
1304
c227f099 1305static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
6cadb320
FB		 1306{
1307 uint16_t val16;
1308 uint32_t val32;
1309 uint64_t val64;
1310
1311 val64 = cpu_to_le64(tally_counters->TxOk);
1312 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1313
1314 val64 = cpu_to_le64(tally_counters->RxOk);
1315 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1316
1317 val64 = cpu_to_le64(tally_counters->TxERR);
1318 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1319
1320 val32 = cpu_to_le32(tally_counters->RxERR);
1321 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1322
1323 val16 = cpu_to_le16(tally_counters->MissPkt);
1324 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1325
1326 val16 = cpu_to_le16(tally_counters->FAE);
1327 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1328
1329 val32 = cpu_to_le32(tally_counters->Tx1Col);
1330 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1331
1332 val32 = cpu_to_le32(tally_counters->TxMCol);
1333 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1334
1335 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1336 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1337
1338 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1339 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1340
1341 val32 = cpu_to_le32(tally_counters->RxOkMul);
1342 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1343
1344 val16 = cpu_to_le16(tally_counters->TxAbt);
1345 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1346
1347 val16 = cpu_to_le16(tally_counters->TxUndrn);
1348 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1349}
1350
1351/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1352
1353static const VMStateDescription vmstate_tally_counters = {
1354 .name = "tally_counters",
1355 .version_id = 1,
1356 .minimum_version_id = 1,
1357 .minimum_version_id_old = 1,
1358 .fields = (VMStateField []) {
1359 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1360 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1361 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1362 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1363 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1364 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1365 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1366 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1367 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1368 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1369 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1370 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1371 VMSTATE_END_OF_LIST()
1372 }
1373};
a41b2ff2
PB		 1374
1375static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1376{
1377 val &= 0xff;
1378
7cdeb319 1379 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1380
1381 if (val & CmdReset)
1382 {
7cdeb319 1383 DPRINTF("ChipCmd reset\n");
7f23f812 1384 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1385 }
1386 if (val & CmdRxEnb)
1387 {
7cdeb319 1388 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1389
1390 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1391 }
1392 if (val & CmdTxEnb)
1393 {
7cdeb319 1394 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1395
1396 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1397 }
1398
1399 /* mask unwriteable bits */
1400 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1401
1402 /* Deassert reset pin before next read */
1403 val &= ~CmdReset;
1404
1405 s->bChipCmdState = val;
1406}
1407
1408static int rtl8139_RxBufferEmpty(RTL8139State *s)
1409{
1410 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1411
1412 if (unread != 0)
1413 {
7cdeb319 1414 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1415 return 0;
1416 }
1417
7cdeb319 1418 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1419
1420 return 1;
1421}
1422
1423static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1424{
1425 uint32_t ret = s->bChipCmdState;
1426
1427 if (rtl8139_RxBufferEmpty(s))
1428 ret |= RxBufEmpty;
1429
7cdeb319 1430 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1431
1432 return ret;
1433}
1434
1435static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1436{
1437 val &= 0xffff;
1438
7cdeb319 1439 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1440
2c3891ab
AL		 1441 s->cplus_enabled = 1;
1442
a41b2ff2
PB		 1443 /* mask unwriteable bits */
1444 val = SET_MASKED(val, 0xff84, s->CpCmd);
1445
1446 s->CpCmd = val;
1447}
1448
1449static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1450{
1451 uint32_t ret = s->CpCmd;
1452
7cdeb319 1453 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1454
1455 return ret;
1456}
1457
1458static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1459{
7cdeb319 1460 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1461}
1462
1463static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1464{
1465 uint32_t ret = 0;
1466
7cdeb319 1467 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1468
1469 return ret;
1470}
1471
9596ebb7 1472static int rtl8139_config_writeable(RTL8139State *s)
a41b2ff2
PB		 1473{
1474 if (s->Cfg9346 & Cfg9346_Unlock)
1475 {
1476 return 1;
1477 }
1478
7cdeb319 1479 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1480
1481 return 0;
1482}
1483
1484static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1485{
1486 val &= 0xffff;
1487
7cdeb319 1488 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2
PB		 1489
1490 /* mask unwriteable bits */
e3d7e843 1491 uint32_t mask = 0x4cff;
a41b2ff2
PB		 1492
1493 if (1 || !rtl8139_config_writeable(s))
1494 {
1495 /* Speed setting and autonegotiation enable bits are read-only */
1496 mask |= 0x3000;
1497 /* Duplex mode setting is read-only */
1498 mask |= 0x0100;
1499 }
1500
1501 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1502
1503 s->BasicModeCtrl = val;
1504}
1505
1506static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1507{
1508 uint32_t ret = s->BasicModeCtrl;
1509
7cdeb319 1510 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1511
1512 return ret;
1513}
1514
1515static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1516{
1517 val &= 0xffff;
1518
7cdeb319 1519 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2
PB		 1520
1521 /* mask unwriteable bits */
1522 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1523
1524 s->BasicModeStatus = val;
1525}
1526
1527static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1528{
1529 uint32_t ret = s->BasicModeStatus;
1530
7cdeb319 1531 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1532
1533 return ret;
1534}
1535
1536static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1537{
1538 val &= 0xff;
1539
7cdeb319 1540 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2
PB		 1541
1542 /* mask unwriteable bits */
1543 val = SET_MASKED(val, 0x31, s->Cfg9346);
1544
1545 uint32_t opmode = val & 0xc0;
1546 uint32_t eeprom_val = val & 0xf;
1547
1548 if (opmode == 0x80) {
1549 /* eeprom access */
1550 int eecs = (eeprom_val & 0x08)?1:0;
1551 int eesk = (eeprom_val & 0x04)?1:0;
1552 int eedi = (eeprom_val & 0x02)?1:0;
1553 prom9346_set_wire(s, eecs, eesk, eedi);
1554 } else if (opmode == 0x40) {
1555 /* Reset. */
1556 val = 0;
7f23f812 1557 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1558 }
1559
1560 s->Cfg9346 = val;
1561}
1562
1563static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1564{
1565 uint32_t ret = s->Cfg9346;
1566
1567 uint32_t opmode = ret & 0xc0;
1568
1569 if (opmode == 0x80)
1570 {
1571 /* eeprom access */
1572 int eedo = prom9346_get_wire(s);
1573 if (eedo)
1574 {
1575 ret |= 0x01;
1576 }
1577 else
1578 {
1579 ret &= ~0x01;
1580 }
1581 }
1582
7cdeb319 1583 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1584
1585 return ret;
1586}
1587
1588static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1589{
1590 val &= 0xff;
1591
7cdeb319 1592 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2
PB		 1593
1594 if (!rtl8139_config_writeable(s))
1595 return;
1596
1597 /* mask unwriteable bits */
1598 val = SET_MASKED(val, 0xf8, s->Config0);
1599
1600 s->Config0 = val;
1601}
1602
1603static uint32_t rtl8139_Config0_read(RTL8139State *s)
1604{
1605 uint32_t ret = s->Config0;
1606
7cdeb319 1607 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1608
1609 return ret;
1610}
1611
1612static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1613{
1614 val &= 0xff;
1615
7cdeb319 1616 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2
PB		 1617
1618 if (!rtl8139_config_writeable(s))
1619 return;
1620
1621 /* mask unwriteable bits */
1622 val = SET_MASKED(val, 0xC, s->Config1);
1623
1624 s->Config1 = val;
1625}
1626
1627static uint32_t rtl8139_Config1_read(RTL8139State *s)
1628{
1629 uint32_t ret = s->Config1;
1630
7cdeb319 1631 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1632
1633 return ret;
1634}
1635
1636static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1637{
1638 val &= 0xff;
1639
7cdeb319 1640 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2
PB		 1641
1642 if (!rtl8139_config_writeable(s))
1643 return;
1644
1645 /* mask unwriteable bits */
1646 val = SET_MASKED(val, 0x8F, s->Config3);
1647
1648 s->Config3 = val;
1649}
1650
1651static uint32_t rtl8139_Config3_read(RTL8139State *s)
1652{
1653 uint32_t ret = s->Config3;
1654
7cdeb319 1655 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1656
1657 return ret;
1658}
1659
1660static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1661{
1662 val &= 0xff;
1663
7cdeb319 1664 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2
PB		 1665
1666 if (!rtl8139_config_writeable(s))
1667 return;
1668
1669 /* mask unwriteable bits */
1670 val = SET_MASKED(val, 0x0a, s->Config4);
1671
1672 s->Config4 = val;
1673}
1674
1675static uint32_t rtl8139_Config4_read(RTL8139State *s)
1676{
1677 uint32_t ret = s->Config4;
1678
7cdeb319 1679 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1680
1681 return ret;
1682}
1683
1684static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1685{
1686 val &= 0xff;
1687
7cdeb319 1688 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2
PB		 1689
1690 /* mask unwriteable bits */
1691 val = SET_MASKED(val, 0x80, s->Config5);
1692
1693 s->Config5 = val;
1694}
1695
1696static uint32_t rtl8139_Config5_read(RTL8139State *s)
1697{
1698 uint32_t ret = s->Config5;
1699
7cdeb319 1700 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1701
1702 return ret;
1703}
1704
1705static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1706{
1707 if (!rtl8139_transmitter_enabled(s))
1708 {
7cdeb319 1709 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1710 return;
1711 }
1712
7cdeb319 1713 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1714
1715 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1716
1717 s->TxConfig = val;
1718}
1719
1720static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1721{
7cdeb319 1722 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1723
1724 uint32_t tc = s->TxConfig;
1725 tc &= 0xFFFFFF00;
1726 tc |= (val & 0x000000FF);
1727 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1728}
1729
1730static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1731{
1732 uint32_t ret = s->TxConfig;
1733
7cdeb319 1734 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1735
1736 return ret;
1737}
1738
1739static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1740{
7cdeb319 1741 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1742
1743 /* mask unwriteable bits */
1744 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1745
1746 s->RxConfig = val;
1747
1748 /* reset buffer size and read/write pointers */
1749 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1750
7cdeb319 1751 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1752}
1753
1754static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1755{
1756 uint32_t ret = s->RxConfig;
1757
7cdeb319 1758 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1759
1760 return ret;
1761}
1762
bf6b87a8
BP		 1763static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1764 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1765{
bf6b87a8
BP		 1766 struct iovec *iov = NULL;
1767
718da2b9
FB		 1768 if (!size)
1769 {
7cdeb319 1770 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1771 return;
1772 }
1773
bf6b87a8
BP		 1774 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1775 iov = (struct iovec[3]) {
1776 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1777 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1778 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1779 .iov_len = size - ETHER_ADDR_LEN * 2 },
1780 };
1781 }
1782
718da2b9
FB		 1783 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1784 {
bf6b87a8
BP		 1785 size_t buf2_size;
1786 uint8_t *buf2;
1787
1788 if (iov) {
1789 buf2_size = iov_size(iov, 3);
1790 buf2 = qemu_malloc(buf2_size);
1791 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1792 buf = buf2;
1793 }
1794
7cdeb319 1795 DPRINTF("+++ transmit loopback mode\n");
1673ad51 1796 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
bf6b87a8
BP		 1797
1798 if (iov) {
1799 qemu_free(buf2);
1800 }
718da2b9
FB		 1801 }
1802 else
1803 {
bf6b87a8
BP		 1804 if (iov) {
1805 qemu_sendv_packet(&s->nic->nc, iov, 3);
1806 } else {
1807 qemu_send_packet(&s->nic->nc, buf, size);
1808 }
718da2b9
FB		 1809 }
1810}
1811
a41b2ff2
PB		 1812static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1813{
1814 if (!rtl8139_transmitter_enabled(s))
1815 {
7cdeb319
BP		 1816 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1817 "disabled\n", descriptor);
a41b2ff2
PB		 1818 return 0;
1819 }
1820
1821 if (s->TxStatus[descriptor] & TxHostOwns)
1822 {
7cdeb319
BP		 1823 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1824 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1825 return 0;
1826 }
1827
7cdeb319 1828 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2
PB		 1829
1830 int txsize = s->TxStatus[descriptor] & 0x1fff;
1831 uint8_t txbuffer[0x2000];
1832
7cdeb319
BP		 1833 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1834 txsize, s->TxAddr[descriptor]);
a41b2ff2 1835
6cadb320 1836 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1837
1838 /* Mark descriptor as transferred */
1839 s->TxStatus[descriptor] |= TxHostOwns;
1840 s->TxStatus[descriptor] |= TxStatOK;
1841
bf6b87a8 1842 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1843
7cdeb319
BP		 1844 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1845 descriptor);
a41b2ff2
PB		 1846
1847 /* update interrupt */
1848 s->IntrStatus |= TxOK;
1849 rtl8139_update_irq(s);
1850
1851 return 1;
1852}
1853
718da2b9
FB		 1854/* structures and macros for task offloading */
1855typedef struct ip_header
1856{
1857 uint8_t ip_ver_len; /* version and header length */
1858 uint8_t ip_tos; /* type of service */
1859 uint16_t ip_len; /* total length */
1860 uint16_t ip_id; /* identification */
1861 uint16_t ip_off; /* fragment offset field */
1862 uint8_t ip_ttl; /* time to live */
1863 uint8_t ip_p; /* protocol */
1864 uint16_t ip_sum; /* checksum */
1865 uint32_t ip_src,ip_dst; /* source and dest address */
1866} ip_header;
1867
1868#define IP_HEADER_VERSION_4 4
1869#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1870#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1871
1872typedef struct tcp_header
1873{
1874 uint16_t th_sport; /* source port */
1875 uint16_t th_dport; /* destination port */
1876 uint32_t th_seq; /* sequence number */
1877 uint32_t th_ack; /* acknowledgement number */
1878 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1879 uint16_t th_win; /* window */
1880 uint16_t th_sum; /* checksum */
1881 uint16_t th_urp; /* urgent pointer */
1882} tcp_header;
1883
1884typedef struct udp_header
1885{
1886 uint16_t uh_sport; /* source port */
1887 uint16_t uh_dport; /* destination port */
1888 uint16_t uh_ulen; /* udp length */
1889 uint16_t uh_sum; /* udp checksum */
1890} udp_header;
1891
1892typedef struct ip_pseudo_header
1893{
1894 uint32_t ip_src;
1895 uint32_t ip_dst;
1896 uint8_t zeros;
1897 uint8_t ip_proto;
1898 uint16_t ip_payload;
1899} ip_pseudo_header;
1900
1901#define IP_PROTO_TCP 6
1902#define IP_PROTO_UDP 17
1903
1904#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1905#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1906#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1907
1908#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1909
1910#define TCP_FLAG_FIN 0x01
1911#define TCP_FLAG_PUSH 0x08
1912
1913/* produces ones' complement sum of data */
1914static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1915{
1916 uint32_t result = 0;
1917
1918 for (; len > 1; data+=2, len-=2)
1919 {
1920 result += *(uint16_t*)data;
1921 }
1922
1923 /* add the remainder byte */
1924 if (len)
1925 {
1926 uint8_t odd[2] = {*data, 0};
1927 result += *(uint16_t*)odd;
1928 }
1929
1930 while (result>>16)
1931 result = (result & 0xffff) + (result >> 16);
1932
1933 return result;
1934}
1935
1936static uint16_t ip_checksum(void *data, size_t len)
1937{
1938 return ~ones_complement_sum((uint8_t*)data, len);
1939}
1940
a41b2ff2
PB		 1941static int rtl8139_cplus_transmit_one(RTL8139State *s)
1942{
1943 if (!rtl8139_transmitter_enabled(s))
1944 {
7cdeb319 1945 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1946 return 0;
1947 }
1948
1949 if (!rtl8139_cp_transmitter_enabled(s))
1950 {
7cdeb319 1951 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1952 return 0 ;
1953 }
1954
1955 int descriptor = s->currCPlusTxDesc;
1956
c227f099 1957 target_phys_addr_t cplus_tx_ring_desc =
a41b2ff2
PB		 1958 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1959
1960 /* Normal priority ring */
1961 cplus_tx_ring_desc += 16 * descriptor;
1962
7cdeb319
BP		 1963 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1964 "%08x0x%08x = 0x"TARGET_FMT_plx"\n", descriptor, s->TxAddr[1],
1965 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1966
1967 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1968
1969 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1970 txdw0 = le32_to_cpu(val);
1971 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1972 txdw1 = le32_to_cpu(val);
1973 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1974 txbufLO = le32_to_cpu(val);
1975 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1976 txbufHI = le32_to_cpu(val);
1977
7cdeb319
BP		 1978 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1979 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1980
1981/* w0 ownership flag */
1982#define CP_TX_OWN (1<<31)
1983/* w0 end of ring flag */
1984#define CP_TX_EOR (1<<30)
1985/* first segment of received packet flag */
1986#define CP_TX_FS (1<<29)
1987/* last segment of received packet flag */
1988#define CP_TX_LS (1<<28)
1989/* large send packet flag */
1990#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1991/* large send MSS mask, bits 16...25 */
1992#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1993
a41b2ff2
PB		 1994/* IP checksum offload flag */
1995#define CP_TX_IPCS (1<<18)
1996/* UDP checksum offload flag */
1997#define CP_TX_UDPCS (1<<17)
1998/* TCP checksum offload flag */
1999#define CP_TX_TCPCS (1<<16)
2000
2001/* w0 bits 0...15 : buffer size */
2002#define CP_TX_BUFFER_SIZE (1<<16)
2003#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 2004/* w1 add tag flag */
2005#define CP_TX_TAGC (1<<17)
2006/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 2007#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2008/* w2 low 32bit of Rx buffer ptr */
2009/* w3 high 32bit of Rx buffer ptr */
2010
2011/* set after transmission */
2012/* FIFO underrun flag */
2013#define CP_TX_STATUS_UNF (1<<25)
2014/* transmit error summary flag, valid if set any of three below */
2015#define CP_TX_STATUS_TES (1<<23)
2016/* out-of-window collision flag */
2017#define CP_TX_STATUS_OWC (1<<22)
2018/* link failure flag */
2019#define CP_TX_STATUS_LNKF (1<<21)
2020/* excessive collisions flag */
2021#define CP_TX_STATUS_EXC (1<<20)
2022
2023 if (!(txdw0 & CP_TX_OWN))
2024 {
7cdeb319 2025 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 2026 return 0 ;
2027 }
2028
7cdeb319 2029 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 2030
2031 if (txdw0 & CP_TX_FS)
2032 {
7cdeb319
BP		 2033 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2034 "descriptor\n", descriptor);
6cadb320
FB		 2035
2036 /* reset internal buffer offset */
2037 s->cplus_txbuffer_offset = 0;
2038 }
a41b2ff2
PB		 2039
2040 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
c227f099 2041 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 2042
6cadb320
FB		 2043 /* make sure we have enough space to assemble the packet */
2044 if (!s->cplus_txbuffer)
2045 {
2046 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2bc6f59b 2047 s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
6cadb320 2048 s->cplus_txbuffer_offset = 0;
718da2b9 2049
7cdeb319
BP		 2050 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2051 s->cplus_txbuffer_len);
6cadb320
FB		 2052 }
2053
2054 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2055 {
2056 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2137b4cc 2057 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2058
7cdeb319
BP		 2059 DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
2060 s->cplus_txbuffer_len);
6cadb320
FB		 2061 }
2062
2063 if (!s->cplus_txbuffer)
2064 {
2065 /* out of memory */
a41b2ff2 2066
7cdeb319
BP		 2067 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2068 s->cplus_txbuffer_len);
6cadb320
FB		 2069
2070 /* update tally counter */
2071 ++s->tally_counters.TxERR;
2072 ++s->tally_counters.TxAbt;
2073
2074 return 0;
2075 }
2076
2077 /* append more data to the packet */
2078
7cdeb319
BP		 2079 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2080 TARGET_FMT_plx" to offset %d\n", txsize, tx_addr,
2081 s->cplus_txbuffer_offset);
6cadb320
FB		 2082
2083 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2084 s->cplus_txbuffer_offset += txsize;
2085
2086 /* seek to next Rx descriptor */
2087 if (txdw0 & CP_TX_EOR)
2088 {
2089 s->currCPlusTxDesc = 0;
2090 }
2091 else
2092 {
2093 ++s->currCPlusTxDesc;
2094 if (s->currCPlusTxDesc >= 64)
2095 s->currCPlusTxDesc = 0;
2096 }
a41b2ff2
PB		 2097
2098 /* transfer ownership to target */
2099 txdw0 &= ~CP_RX_OWN;
2100
2101 /* reset error indicator bits */
2102 txdw0 &= ~CP_TX_STATUS_UNF;
2103 txdw0 &= ~CP_TX_STATUS_TES;
2104 txdw0 &= ~CP_TX_STATUS_OWC;
2105 txdw0 &= ~CP_TX_STATUS_LNKF;
2106 txdw0 &= ~CP_TX_STATUS_EXC;
2107
2108 /* update ring data */
2109 val = cpu_to_le32(txdw0);
2110 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2111
6cadb320
FB		 2112 /* Now decide if descriptor being processed is holding the last segment of packet */
2113 if (txdw0 & CP_TX_LS)
a41b2ff2 2114 {
bf6b87a8
BP		 2115 uint8_t dot1q_buffer_space[VLAN_HLEN];
2116 uint16_t *dot1q_buffer;
2117
7cdeb319
BP		 2118 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2119 descriptor);
6cadb320
FB		 2120
2121 /* can transfer fully assembled packet */
2122
2123 uint8_t *saved_buffer = s->cplus_txbuffer;
2124 int saved_size = s->cplus_txbuffer_offset;
2125 int saved_buffer_len = s->cplus_txbuffer_len;
2126
bf6b87a8
BP		 2127 /* create vlan tag */
2128 if (txdw1 & CP_TX_TAGC) {
2129 /* the vlan tag is in BE byte order in the descriptor
2130 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2131 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2132 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2133
2134 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2135 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2136 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2137 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2138 } else {
2139 dot1q_buffer = NULL;
2140 }
2141
6cadb320
FB		 2142 /* reset the card space to protect from recursive call */
2143 s->cplus_txbuffer = NULL;
2144 s->cplus_txbuffer_offset = 0;
2145 s->cplus_txbuffer_len = 0;
2146
718da2b9 2147 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2148 {
7cdeb319 2149 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2150
6cadb320 2151 /* ip packet header */
660f11be 2152 ip_header *ip = NULL;
6cadb320 2153 int hlen = 0;
718da2b9
FB		 2154 uint8_t ip_protocol = 0;
2155 uint16_t ip_data_len = 0;
6cadb320 2156
660f11be 2157 uint8_t *eth_payload_data = NULL;
718da2b9 2158 size_t eth_payload_len = 0;
6cadb320 2159
718da2b9 2160 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2161 if (proto == ETH_P_IP)
2162 {
7cdeb319 2163 DPRINTF("+++ C+ mode has IP packet\n");
6cadb320
FB		 2164
2165 /* not aligned */
718da2b9
FB		 2166 eth_payload_data = saved_buffer + ETH_HLEN;
2167 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2168
718da2b9 2169 ip = (ip_header*)eth_payload_data;
6cadb320 2170
718da2b9 2171 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
7cdeb319
BP		 2172 DPRINTF("+++ C+ mode packet has bad IP version %d "
2173 "expected %d\n", IP_HEADER_VERSION(ip),
2174 IP_HEADER_VERSION_4);
6cadb320
FB		 2175 ip = NULL;
2176 } else {
718da2b9
FB		 2177 hlen = IP_HEADER_LENGTH(ip);
2178 ip_protocol = ip->ip_p;
2179 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2180 }
2181 }
2182
2183 if (ip)
2184 {
2185 if (txdw0 & CP_TX_IPCS)
2186 {
7cdeb319 2187 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2188
718da2b9 2189 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2190 /* bad packet header len */
2191 /* or packet too short */
2192 }
2193 else
2194 {
2195 ip->ip_sum = 0;
718da2b9 2196 ip->ip_sum = ip_checksum(ip, hlen);
7cdeb319
BP		 2197 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2198 hlen, ip->ip_sum);
6cadb320
FB		 2199 }
2200 }
2201
718da2b9 2202 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2203 {
718da2b9
FB		 2204#if defined (DEBUG_RTL8139)
2205 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2206#endif
7cdeb319
BP		 2207 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2208 "frame data %d specified MSS=%d\n", ETH_MTU,
2209 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2210
718da2b9
FB		 2211 int tcp_send_offset = 0;
2212 int send_count = 0;
6cadb320
FB		 2213
2214 /* maximum IP header length is 60 bytes */
2215 uint8_t saved_ip_header[60];
6cadb320 2216
718da2b9
FB		 2217 /* save IP header template; data area is used in tcp checksum calculation */
2218 memcpy(saved_ip_header, eth_payload_data, hlen);
2219
2220 /* a placeholder for checksum calculation routine in tcp case */
2221 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2222 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2223
2224 /* pointer to TCP header */
2225 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2226
2227 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2228
2229 /* ETH_MTU = ip header len + tcp header len + payload */
2230 int tcp_data_len = ip_data_len - tcp_hlen;
2231 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2232
7cdeb319
BP		 2233 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2234 "data len %d TCP chunk size %d\n", ip_data_len,
2235 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9
FB		 2236
2237 /* note the cycle below overwrites IP header data,
2238 but restores it from saved_ip_header before sending packet */
2239
2240 int is_last_frame = 0;
2241
2242 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2243 {
2244 uint16_t chunk_size = tcp_chunk_size;
2245
2246 /* check if this is the last frame */
2247 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2248 {
2249 is_last_frame = 1;
2250 chunk_size = tcp_data_len - tcp_send_offset;
2251 }
2252
7cdeb319
BP		 2253 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2254 be32_to_cpu(p_tcp_hdr->th_seq));
718da2b9
FB		 2255
2256 /* add 4 TCP pseudoheader fields */
2257 /* copy IP source and destination fields */
2258 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2259
7cdeb319
BP		 2260 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2261 "packet with %d bytes data\n", tcp_hlen +
2262 chunk_size);
718da2b9
FB		 2263
2264 if (tcp_send_offset)
2265 {
2266 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2267 }
2268
2269 /* keep PUSH and FIN flags only for the last frame */
2270 if (!is_last_frame)
2271 {
2272 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2273 }
6cadb320 2274
718da2b9
FB		 2275 /* recalculate TCP checksum */
2276 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2277 p_tcpip_hdr->zeros = 0;
2278 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2279 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2280
2281 p_tcp_hdr->th_sum = 0;
2282
2283 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
7cdeb319
BP		 2284 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2285 tcp_checksum);
718da2b9
FB		 2286
2287 p_tcp_hdr->th_sum = tcp_checksum;
2288
2289 /* restore IP header */
2290 memcpy(eth_payload_data, saved_ip_header, hlen);
2291
2292 /* set IP data length and recalculate IP checksum */
2293 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2294
2295 /* increment IP id for subsequent frames */
2296 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2297
2298 ip->ip_sum = 0;
2299 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
7cdeb319
BP		 2300 DPRINTF("+++ C+ mode TSO IP header len=%d "
2301 "checksum=%04x\n", hlen, ip->ip_sum);
718da2b9
FB		 2302
2303 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
7cdeb319
BP		 2304 DPRINTF("+++ C+ mode TSO transferring packet size "
2305 "%d\n", tso_send_size);
bf6b87a8
BP		 2306 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2307 0, (uint8_t *) dot1q_buffer);
718da2b9
FB		 2308
2309 /* add transferred count to TCP sequence number */
2310 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2311 ++send_count;
2312 }
2313
2314 /* Stop sending this frame */
2315 saved_size = 0;
2316 }
2317 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2318 {
7cdeb319 2319 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
718da2b9
FB		 2320
2321 /* maximum IP header length is 60 bytes */
2322 uint8_t saved_ip_header[60];
2323 memcpy(saved_ip_header, eth_payload_data, hlen);
2324
2325 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2326 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2327
2328 /* add 4 TCP pseudoheader fields */
2329 /* copy IP source and destination fields */
718da2b9 2330 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2331
718da2b9 2332 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320 2333 {
7cdeb319
BP		 2334 DPRINTF("+++ C+ mode calculating TCP checksum for "
2335 "packet with %d bytes data\n", ip_data_len);
6cadb320 2336
718da2b9
FB		 2337 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2338 p_tcpip_hdr->zeros = 0;
2339 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2340 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2341
718da2b9 2342 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2343
2344 p_tcp_hdr->th_sum = 0;
2345
718da2b9 2346 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2347 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2348 tcp_checksum);
6cadb320
FB		 2349
2350 p_tcp_hdr->th_sum = tcp_checksum;
2351 }
718da2b9 2352 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320 2353 {
7cdeb319
BP		 2354 DPRINTF("+++ C+ mode calculating UDP checksum for "
2355 "packet with %d bytes data\n", ip_data_len);
6cadb320 2356
718da2b9
FB		 2357 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2358 p_udpip_hdr->zeros = 0;
2359 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2360 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2361
718da2b9 2362 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2363
6cadb320
FB		 2364 p_udp_hdr->uh_sum = 0;
2365
718da2b9 2366 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2367 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2368 udp_checksum);
6cadb320 2369
6cadb320
FB		 2370 p_udp_hdr->uh_sum = udp_checksum;
2371 }
2372
2373 /* restore IP header */
718da2b9 2374 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2375 }
2376 }
2377 }
2378
2379 /* update tally counter */
2380 ++s->tally_counters.TxOk;
2381
7cdeb319 2382 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2383
bf6b87a8
BP		 2384 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2385 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2386
2387 /* restore card space if there was no recursion and reset offset */
2388 if (!s->cplus_txbuffer)
2389 {
2390 s->cplus_txbuffer = saved_buffer;
2391 s->cplus_txbuffer_len = saved_buffer_len;
2392 s->cplus_txbuffer_offset = 0;
2393 }
2394 else
2395 {
2bc6f59b 2396 qemu_free(saved_buffer);
6cadb320 2397 }
a41b2ff2
PB		 2398 }
2399 else
2400 {
7cdeb319 2401 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2402 }
2403
a41b2ff2
PB		 2404 return 1;
2405}
2406
2407static void rtl8139_cplus_transmit(RTL8139State *s)
2408{
2409 int txcount = 0;
2410
2411 while (rtl8139_cplus_transmit_one(s))
2412 {
2413 ++txcount;
2414 }
2415
2416 /* Mark transfer completed */
2417 if (!txcount)
2418 {
7cdeb319
BP		 2419 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2420 s->currCPlusTxDesc);
a41b2ff2
PB		 2421 }
2422 else
2423 {
2424 /* update interrupt status */
2425 s->IntrStatus |= TxOK;
2426 rtl8139_update_irq(s);
2427 }
2428}
2429
2430static void rtl8139_transmit(RTL8139State *s)
2431{
2432 int descriptor = s->currTxDesc, txcount = 0;
2433
2434 /*while*/
2435 if (rtl8139_transmit_one(s, descriptor))
2436 {
2437 ++s->currTxDesc;
2438 s->currTxDesc %= 4;
2439 ++txcount;
2440 }
2441
2442 /* Mark transfer completed */
2443 if (!txcount)
2444 {
7cdeb319
BP		 2445 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2446 s->currTxDesc);
a41b2ff2
PB		 2447 }
2448}
2449
2450static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2451{
2452
2453 int descriptor = txRegOffset/4;
6cadb320
FB		 2454
2455 /* handle C+ transmit mode register configuration */
2456
2c3891ab 2457 if (s->cplus_enabled)
6cadb320 2458 {
7cdeb319
BP		 2459 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2460 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2461
2462 /* handle Dump Tally Counters command */
2463 s->TxStatus[descriptor] = val;
2464
2465 if (descriptor == 0 && (val & 0x8))
2466 {
c227f099 2467 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2468
2469 /* dump tally counters to specified memory location */
2470 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2471
2472 /* mark dump completed */
2473 s->TxStatus[0] &= ~0x8;
2474 }
2475
2476 return;
2477 }
2478
7cdeb319
BP		 2479 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2480 txRegOffset, val, descriptor);
a41b2ff2
PB		 2481
2482 /* mask only reserved bits */
2483 val &= ~0xff00c000; /* these bits are reset on write */
2484 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2485
2486 s->TxStatus[descriptor] = val;
2487
2488 /* attempt to start transmission */
2489 rtl8139_transmit(s);
2490}
2491
2492static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2493{
2494 uint32_t ret = s->TxStatus[txRegOffset/4];
2495
7cdeb319 2496 DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
a41b2ff2
PB		 2497
2498 return ret;
2499}
2500
2501static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2502{
2503 uint16_t ret = 0;
2504
2505 /* Simulate TSAD, it is read only anyway */
2506
2507 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2508 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2509 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2510 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2511
2512 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2513 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2514 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2515 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2516
a41b2ff2
PB		 2517 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2518 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2519 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2520 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2521
a41b2ff2
PB		 2522 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2523 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2524 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2525 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2526
a41b2ff2 2527
7cdeb319 2528 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2529
2530 return ret;
2531}
2532
2533static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2534{
2535 uint16_t ret = s->CSCR;
2536
7cdeb319 2537 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2538
2539 return ret;
2540}
2541
2542static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2543{
7cdeb319 2544 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2545
290a0933 2546 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2547}
2548
2549static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2550{
290a0933 2551 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2552
7cdeb319 2553 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2554
2555 return ret;
2556}
2557
2558static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2559{
7cdeb319 2560 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2561
2562 /* this value is off by 16 */
2563 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2564
7cdeb319
BP		 2565 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2566 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2567}
2568
2569static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2570{
2571 /* this value is off by 16 */
2572 uint32_t ret = s->RxBufPtr - 0x10;
2573
7cdeb319 2574 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2575
2576 return ret;
2577}
2578
2579static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2580{
2581 /* this value is NOT off by 16 */
2582 uint32_t ret = s->RxBufAddr;
2583
7cdeb319 2584 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2585
2586 return ret;
2587}
2588
2589static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2590{
7cdeb319 2591 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2592
2593 s->RxBuf = val;
2594
2595 /* may need to reset rxring here */
2596}
2597
2598static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2599{
2600 uint32_t ret = s->RxBuf;
2601
7cdeb319 2602 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2603
2604 return ret;
2605}
2606
2607static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2608{
7cdeb319 2609 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2610
2611 /* mask unwriteable bits */
2612 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2613
2614 s->IntrMask = val;
2615
74475455 2616 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2617 rtl8139_update_irq(s);
05447803 2618
a41b2ff2
PB		 2619}
2620
2621static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2622{
2623 uint32_t ret = s->IntrMask;
2624
7cdeb319 2625 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2626
2627 return ret;
2628}
2629
2630static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2631{
7cdeb319 2632 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2633
2634#if 0
2635
2636 /* writing to ISR has no effect */
2637
2638 return;
2639
2640#else
2641 uint16_t newStatus = s->IntrStatus & ~val;
2642
2643 /* mask unwriteable bits */
2644 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2645
2646 /* writing 1 to interrupt status register bit clears it */
2647 s->IntrStatus = 0;
2648 rtl8139_update_irq(s);
2649
2650 s->IntrStatus = newStatus;
05447803
FZ		 2651 /*
2652 * Computing if we miss an interrupt here is not that correct but
2653 * considered that we should have had already an interrupt
2654 * and probably emulated is slower is better to assume this resetting was
2655 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2656 */
74475455 2657 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2658 rtl8139_update_irq(s);
05447803 2659
a41b2ff2
PB		 2660#endif
2661}
2662
2663static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2664{
74475455 2665 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2666
a41b2ff2
PB		 2667 uint32_t ret = s->IntrStatus;
2668
7cdeb319 2669 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2670
2671#if 0
2672
2673 /* reading ISR clears all interrupts */
2674 s->IntrStatus = 0;
2675
2676 rtl8139_update_irq(s);
2677
2678#endif
2679
2680 return ret;
2681}
2682
2683static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2684{
7cdeb319 2685 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2686
2687 /* mask unwriteable bits */
2688 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2689
2690 s->MultiIntr = val;
2691}
2692
2693static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2694{
2695 uint32_t ret = s->MultiIntr;
2696
7cdeb319 2697 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2698
2699 return ret;
2700}
2701
2702static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2703{
2704 RTL8139State *s = opaque;
2705
2706 addr &= 0xff;
2707
2708 switch (addr)
2709 {
2710 case MAC0 ... MAC0+5:
2711 s->phys[addr - MAC0] = val;
2712 break;
2713 case MAC0+6 ... MAC0+7:
2714 /* reserved */
2715 break;
2716 case MAR0 ... MAR0+7:
2717 s->mult[addr - MAR0] = val;
2718 break;
2719 case ChipCmd:
2720 rtl8139_ChipCmd_write(s, val);
2721 break;
2722 case Cfg9346:
2723 rtl8139_Cfg9346_write(s, val);
2724 break;
2725 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2726 rtl8139_TxConfig_writeb(s, val);
2727 break;
2728 case Config0:
2729 rtl8139_Config0_write(s, val);
2730 break;
2731 case Config1:
2732 rtl8139_Config1_write(s, val);
2733 break;
2734 case Config3:
2735 rtl8139_Config3_write(s, val);
2736 break;
2737 case Config4:
2738 rtl8139_Config4_write(s, val);
2739 break;
2740 case Config5:
2741 rtl8139_Config5_write(s, val);
2742 break;
2743 case MediaStatus:
2744 /* ignore */
7cdeb319
BP		 2745 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2746 val);
a41b2ff2
PB		 2747 break;
2748
2749 case HltClk:
7cdeb319 2750 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2751 if (val == 'R')
2752 {
2753 s->clock_enabled = 1;
2754 }
2755 else if (val == 'H')
2756 {
2757 s->clock_enabled = 0;
2758 }
2759 break;
2760
2761 case TxThresh:
7cdeb319 2762 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2763 s->TxThresh = val;
2764 break;
2765
2766 case TxPoll:
7cdeb319 2767 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2768 if (val & (1 << 7))
2769 {
7cdeb319
BP		 2770 DPRINTF("C+ TxPoll high priority transmission (not "
2771 "implemented)\n");
a41b2ff2
PB		 2772 //rtl8139_cplus_transmit(s);
2773 }
2774 if (val & (1 << 6))
2775 {
7cdeb319 2776 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2777 rtl8139_cplus_transmit(s);
2778 }
2779
2780 break;
2781
2782 default:
7cdeb319
BP		 2783 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2784 val);
a41b2ff2
PB		 2785 break;
2786 }
2787}
2788
2789static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2790{
2791 RTL8139State *s = opaque;
2792
2793 addr &= 0xfe;
2794
2795 switch (addr)
2796 {
2797 case IntrMask:
2798 rtl8139_IntrMask_write(s, val);
2799 break;
2800
2801 case IntrStatus:
2802 rtl8139_IntrStatus_write(s, val);
2803 break;
2804
2805 case MultiIntr:
2806 rtl8139_MultiIntr_write(s, val);
2807 break;
2808
2809 case RxBufPtr:
2810 rtl8139_RxBufPtr_write(s, val);
2811 break;
2812
2813 case BasicModeCtrl:
2814 rtl8139_BasicModeCtrl_write(s, val);
2815 break;
2816 case BasicModeStatus:
2817 rtl8139_BasicModeStatus_write(s, val);
2818 break;
2819 case NWayAdvert:
7cdeb319 2820 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2821 s->NWayAdvert = val;
2822 break;
2823 case NWayLPAR:
7cdeb319 2824 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2825 break;
2826 case NWayExpansion:
7cdeb319 2827 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2828 s->NWayExpansion = val;
2829 break;
2830
2831 case CpCmd:
2832 rtl8139_CpCmd_write(s, val);
2833 break;
2834
6cadb320
FB		 2835 case IntrMitigate:
2836 rtl8139_IntrMitigate_write(s, val);
2837 break;
2838
a41b2ff2 2839 default:
7cdeb319
BP		 2840 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2841 addr, val);
a41b2ff2 2842
a41b2ff2
PB		 2843 rtl8139_io_writeb(opaque, addr, val & 0xff);
2844 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2845 break;
2846 }
2847}
2848
05447803
FZ		 2849static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2850{
2851 int64_t pci_time, next_time;
2852 uint32_t low_pci;
2853
7cdeb319 2854 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803
FZ		 2855
2856 if (s->TimerExpire && current_time >= s->TimerExpire) {
2857 s->IntrStatus |= PCSTimeout;
2858 rtl8139_update_irq(s);
2859 }
2860
2861 /* Set QEMU timer only if needed that is
2862 * - TimerInt <> 0 (we have a timer)
2863 * - mask = 1 (we want an interrupt timer)
2864 * - irq = 0 (irq is not already active)
2865 * If any of above change we need to compute timer again
2866 * Also we must check if timer is passed without QEMU timer
2867 */
2868 s->TimerExpire = 0;
2869 if (!s->TimerInt) {
2870 return;
2871 }
2872
2873 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2874 get_ticks_per_sec());
2875 low_pci = pci_time & 0xffffffff;
2876 pci_time = pci_time - low_pci + s->TimerInt;
2877 if (low_pci >= s->TimerInt) {
2878 pci_time += 0x100000000LL;
2879 }
2880 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2881 PCI_FREQUENCY);
2882 s->TimerExpire = next_time;
2883
2884 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2885 qemu_mod_timer(s->timer, next_time);
2886 }
2887}
2888
a41b2ff2
PB		 2889static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2890{
2891 RTL8139State *s = opaque;
2892
2893 addr &= 0xfc;
2894
2895 switch (addr)
2896 {
2897 case RxMissed:
7cdeb319 2898 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2899 s->RxMissed = 0;
2900 break;
2901
2902 case TxConfig:
2903 rtl8139_TxConfig_write(s, val);
2904 break;
2905
2906 case RxConfig:
2907 rtl8139_RxConfig_write(s, val);
2908 break;
2909
2910 case TxStatus0 ... TxStatus0+4*4-1:
2911 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2912 break;
2913
2914 case TxAddr0 ... TxAddr0+4*4-1:
2915 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2916 break;
2917
2918 case RxBuf:
2919 rtl8139_RxBuf_write(s, val);
2920 break;
2921
2922 case RxRingAddrLO:
7cdeb319 2923 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2924 s->RxRingAddrLO = val;
2925 break;
2926
2927 case RxRingAddrHI:
7cdeb319 2928 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2929 s->RxRingAddrHI = val;
2930 break;
2931
6cadb320 2932 case Timer:
7cdeb319 2933 DPRINTF("TCTR Timer reset on write\n");
74475455 2934 s->TCTR_base = qemu_get_clock_ns(vm_clock);
05447803 2935 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2936 break;
2937
2938 case FlashReg:
7cdeb319 2939 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2940 if (s->TimerInt != val) {
2941 s->TimerInt = val;
74475455 2942 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2943 }
6cadb320
FB		 2944 break;
2945
a41b2ff2 2946 default:
7cdeb319
BP		 2947 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2948 addr, val);
a41b2ff2
PB		 2949 rtl8139_io_writeb(opaque, addr, val & 0xff);
2950 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2951 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2952 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2953 break;
2954 }
2955}
2956
2957static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2958{
2959 RTL8139State *s = opaque;
2960 int ret;
2961
2962 addr &= 0xff;
2963
2964 switch (addr)
2965 {
2966 case MAC0 ... MAC0+5:
2967 ret = s->phys[addr - MAC0];
2968 break;
2969 case MAC0+6 ... MAC0+7:
2970 ret = 0;
2971 break;
2972 case MAR0 ... MAR0+7:
2973 ret = s->mult[addr - MAR0];
2974 break;
2975 case ChipCmd:
2976 ret = rtl8139_ChipCmd_read(s);
2977 break;
2978 case Cfg9346:
2979 ret = rtl8139_Cfg9346_read(s);
2980 break;
2981 case Config0:
2982 ret = rtl8139_Config0_read(s);
2983 break;
2984 case Config1:
2985 ret = rtl8139_Config1_read(s);
2986 break;
2987 case Config3:
2988 ret = rtl8139_Config3_read(s);
2989 break;
2990 case Config4:
2991 ret = rtl8139_Config4_read(s);
2992 break;
2993 case Config5:
2994 ret = rtl8139_Config5_read(s);
2995 break;
2996
2997 case MediaStatus:
2998 ret = 0xd0;
7cdeb319 2999 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 3000 break;
3001
3002 case HltClk:
3003 ret = s->clock_enabled;
7cdeb319 3004 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 3005 break;
3006
3007 case PCIRevisionID:
6cadb320 3008 ret = RTL8139_PCI_REVID;
7cdeb319 3009 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 3010 break;
3011
3012 case TxThresh:
3013 ret = s->TxThresh;
7cdeb319 3014 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3015 break;
3016
3017 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3018 ret = s->TxConfig >> 24;
7cdeb319 3019 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3020 break;
3021
3022 default:
7cdeb319 3023 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 3024 ret = 0;
3025 break;
3026 }
3027
3028 return ret;
3029}
3030
3031static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3032{
3033 RTL8139State *s = opaque;
3034 uint32_t ret;
3035
3036 addr &= 0xfe; /* mask lower bit */
3037
3038 switch (addr)
3039 {
3040 case IntrMask:
3041 ret = rtl8139_IntrMask_read(s);
3042 break;
3043
3044 case IntrStatus:
3045 ret = rtl8139_IntrStatus_read(s);
3046 break;
3047
3048 case MultiIntr:
3049 ret = rtl8139_MultiIntr_read(s);
3050 break;
3051
3052 case RxBufPtr:
3053 ret = rtl8139_RxBufPtr_read(s);
3054 break;
3055
6cadb320
FB		 3056 case RxBufAddr:
3057 ret = rtl8139_RxBufAddr_read(s);
3058 break;
3059
a41b2ff2
PB		 3060 case BasicModeCtrl:
3061 ret = rtl8139_BasicModeCtrl_read(s);
3062 break;
3063 case BasicModeStatus:
3064 ret = rtl8139_BasicModeStatus_read(s);
3065 break;
3066 case NWayAdvert:
3067 ret = s->NWayAdvert;
7cdeb319 3068 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3069 break;
3070 case NWayLPAR:
3071 ret = s->NWayLPAR;
7cdeb319 3072 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3073 break;
3074 case NWayExpansion:
3075 ret = s->NWayExpansion;
7cdeb319 3076 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3077 break;
3078
3079 case CpCmd:
3080 ret = rtl8139_CpCmd_read(s);
3081 break;
3082
6cadb320
FB		 3083 case IntrMitigate:
3084 ret = rtl8139_IntrMitigate_read(s);
3085 break;
3086
a41b2ff2
PB		 3087 case TxSummary:
3088 ret = rtl8139_TSAD_read(s);
3089 break;
3090
3091 case CSCR:
3092 ret = rtl8139_CSCR_read(s);
3093 break;
3094
3095 default:
7cdeb319 3096 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3097
a41b2ff2
PB		 3098 ret = rtl8139_io_readb(opaque, addr);
3099 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3100
7cdeb319 3101 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3102 break;
3103 }
3104
3105 return ret;
3106}
3107
3108static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3109{
3110 RTL8139State *s = opaque;
3111 uint32_t ret;
3112
3113 addr &= 0xfc; /* also mask low 2 bits */
3114
3115 switch (addr)
3116 {
3117 case RxMissed:
3118 ret = s->RxMissed;
3119
7cdeb319 3120 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3121 break;
3122
3123 case TxConfig:
3124 ret = rtl8139_TxConfig_read(s);
3125 break;
3126
3127 case RxConfig:
3128 ret = rtl8139_RxConfig_read(s);
3129 break;
3130
3131 case TxStatus0 ... TxStatus0+4*4-1:
3132 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3133 break;
3134
3135 case TxAddr0 ... TxAddr0+4*4-1:
3136 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3137 break;
3138
3139 case RxBuf:
3140 ret = rtl8139_RxBuf_read(s);
3141 break;
3142
3143 case RxRingAddrLO:
3144 ret = s->RxRingAddrLO;
7cdeb319 3145 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3146 break;
3147
3148 case RxRingAddrHI:
3149 ret = s->RxRingAddrHI;
7cdeb319 3150 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3151 break;
3152
3153 case Timer:
74475455 3154 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
05447803 3155 PCI_FREQUENCY, get_ticks_per_sec());
7cdeb319 3156 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3157 break;
3158
3159 case FlashReg:
3160 ret = s->TimerInt;
7cdeb319 3161 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3162 break;
3163
3164 default:
7cdeb319 3165 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3166
a41b2ff2
PB		 3167 ret = rtl8139_io_readb(opaque, addr);
3168 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3169 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3170 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3171
7cdeb319 3172 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3173 break;
3174 }
3175
3176 return ret;
3177}
3178
3179/* */
3180
3181static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3182{
3183 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3184}
3185
3186static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3187{
3188 rtl8139_io_writew(opaque, addr & 0xFF, val);
3189}
3190
3191static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3192{
3193 rtl8139_io_writel(opaque, addr & 0xFF, val);
3194}
3195
3196static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3197{
3198 return rtl8139_io_readb(opaque, addr & 0xFF);
3199}
3200
3201static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3202{
3203 return rtl8139_io_readw(opaque, addr & 0xFF);
3204}
3205
3206static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3207{
3208 return rtl8139_io_readl(opaque, addr & 0xFF);
3209}
3210
3211/* */
3212
c227f099 3213static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3214{
3215 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3216}
3217
c227f099 3218static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3219{
3220 rtl8139_io_writew(opaque, addr & 0xFF, val);
3221}
3222
c227f099 3223static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3224{
3225 rtl8139_io_writel(opaque, addr & 0xFF, val);
3226}
3227
c227f099 3228static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3229{
3230 return rtl8139_io_readb(opaque, addr & 0xFF);
3231}
3232
c227f099 3233static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3234{
5fedc612 3235 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3236 return val;
a41b2ff2
PB		 3237}
3238
c227f099 3239static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3240{
5fedc612 3241 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3242 return val;
a41b2ff2
PB		 3243}
3244
060110c3 3245static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3246{
6597ebbb 3247 RTL8139State* s = opaque;
74475455 3248 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
060110c3 3249 if (version_id < 4) {
2c3891ab
AL		 3250 s->cplus_enabled = s->CpCmd != 0;
3251 }
3252
a41b2ff2
PB		 3253 return 0;
3254}
3255
c574ba5a
AW		 3256static bool rtl8139_hotplug_ready_needed(void *opaque)
3257{
3258 return qdev_machine_modified();
3259}
3260
3261static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3262 .name = "rtl8139/hotplug_ready",
3263 .version_id = 1,
3264 .minimum_version_id = 1,
3265 .minimum_version_id_old = 1,
3266 .fields = (VMStateField []) {
3267 VMSTATE_END_OF_LIST()
3268 }
3269};
3270
05447803
FZ		 3271static void rtl8139_pre_save(void *opaque)
3272{
3273 RTL8139State* s = opaque;
74475455 3274 int64_t current_time = qemu_get_clock_ns(vm_clock);
05447803
FZ		 3275
3276 /* set IntrStatus correctly */
3277 rtl8139_set_next_tctr_time(s, current_time);
3278 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3279 get_ticks_per_sec());
c574ba5a 3280 s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr;
05447803
FZ		 3281}
3282
060110c3
JQ		 3283static const VMStateDescription vmstate_rtl8139 = {
3284 .name = "rtl8139",
3285 .version_id = 4,
3286 .minimum_version_id = 3,
3287 .minimum_version_id_old = 3,
3288 .post_load = rtl8139_post_load,
05447803 3289 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3290 .fields = (VMStateField []) {
3291 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3292 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3293 VMSTATE_BUFFER(mult, RTL8139State),
3294 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3295 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3296
3297 VMSTATE_UINT32(RxBuf, RTL8139State),
3298 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3299 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3300 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3301
3302 VMSTATE_UINT16(IntrStatus, RTL8139State),
3303 VMSTATE_UINT16(IntrMask, RTL8139State),
3304
3305 VMSTATE_UINT32(TxConfig, RTL8139State),
3306 VMSTATE_UINT32(RxConfig, RTL8139State),
3307 VMSTATE_UINT32(RxMissed, RTL8139State),
3308 VMSTATE_UINT16(CSCR, RTL8139State),
3309
3310 VMSTATE_UINT8(Cfg9346, RTL8139State),
3311 VMSTATE_UINT8(Config0, RTL8139State),
3312 VMSTATE_UINT8(Config1, RTL8139State),
3313 VMSTATE_UINT8(Config3, RTL8139State),
3314 VMSTATE_UINT8(Config4, RTL8139State),
3315 VMSTATE_UINT8(Config5, RTL8139State),
3316
3317 VMSTATE_UINT8(clock_enabled, RTL8139State),
3318 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3319
3320 VMSTATE_UINT16(MultiIntr, RTL8139State),
3321
3322 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3323 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3324 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3325 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3326 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3327
3328 VMSTATE_UINT16(CpCmd, RTL8139State),
3329 VMSTATE_UINT8(TxThresh, RTL8139State),
3330
3331 VMSTATE_UNUSED(4),
3332 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3333 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3334
3335 VMSTATE_UINT32(currTxDesc, RTL8139State),
3336 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3337 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3338 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3339 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3340
3341 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3342 VMSTATE_INT32(eeprom.mode, RTL8139State),
3343 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3344 VMSTATE_UINT8(eeprom.address, RTL8139State),
3345 VMSTATE_UINT16(eeprom.input, RTL8139State),
3346 VMSTATE_UINT16(eeprom.output, RTL8139State),
3347
3348 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3349 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3350 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3351 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3352
3353 VMSTATE_UINT32(TCTR, RTL8139State),
3354 VMSTATE_UINT32(TimerInt, RTL8139State),
3355 VMSTATE_INT64(TCTR_base, RTL8139State),
3356
3357 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3358 vmstate_tally_counters, RTL8139TallyCounters),
3359
3360 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3361 VMSTATE_END_OF_LIST()
c574ba5a
AW		 3362 },
3363 .subsections = (VMStateSubsection []) {
3364 {
3365 .vmsd = &vmstate_rtl8139_hotplug_ready,
3366 .needed = rtl8139_hotplug_ready_needed,
3367 }, {
3368 /* empty */
3369 }
060110c3
JQ		 3370 }
3371};
3372
a41b2ff2
PB		 3373/***********************************************************/
3374/* PCI RTL8139 definitions */
3375
5fafdf24 3376static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
6e355d90 3377 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3378{
efd6dd45 3379 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3380
3381 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3382}
3383
5fafdf24 3384static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
6e355d90 3385 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3386{
efd6dd45 3387 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3388
3389 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3390 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3391
3392 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3393 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3394
3395 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3396 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3397}
3398
d60efc6b 3399static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
a41b2ff2
PB		 3400 rtl8139_mmio_readb,
3401 rtl8139_mmio_readw,
3402 rtl8139_mmio_readl,
3403};
3404
d60efc6b 3405static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
a41b2ff2
PB		 3406 rtl8139_mmio_writeb,
3407 rtl8139_mmio_writew,
3408 rtl8139_mmio_writel,
3409};
3410
6cadb320
FB		 3411static void rtl8139_timer(void *opaque)
3412{
3413 RTL8139State *s = opaque;
3414
6cadb320
FB		 3415 if (!s->clock_enabled)
3416 {
7cdeb319 3417 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3418 return;
3419 }
3420
05447803
FZ		 3421 s->IntrStatus |= PCSTimeout;
3422 rtl8139_update_irq(s);
74475455 3423 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
6cadb320 3424}
6cadb320 3425
1673ad51 3426static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3427{
1673ad51 3428 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3429
1673ad51 3430 s->nic = NULL;
254111ec
GH		 3431}
3432
3433static int pci_rtl8139_uninit(PCIDevice *dev)
3434{
3435 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3436
3437 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
b946a153
AL		 3438 if (s->cplus_txbuffer) {
3439 qemu_free(s->cplus_txbuffer);
3440 s->cplus_txbuffer = NULL;
3441 }
b946a153
AL		 3442 qemu_del_timer(s->timer);
3443 qemu_free_timer(s->timer);
1673ad51 3444 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3445 return 0;
3446}
3447
1673ad51
MM		 3448static NetClientInfo net_rtl8139_info = {
3449 .type = NET_CLIENT_TYPE_NIC,
3450 .size = sizeof(NICState),
3451 .can_receive = rtl8139_can_receive,
3452 .receive = rtl8139_receive,
3453 .cleanup = rtl8139_cleanup,
3454};
3455
81a322d4 3456static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3457{
efd6dd45 3458 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3459 uint8_t *pci_conf;
3b46e624 3460
efd6dd45 3461 pci_conf = s->dev.config;
deb54399
AL		 3462 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3463 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
0b5b3547 3464 pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
173a543b 3465 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
0b5b3547
MT		 3466 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
3467 /* TODO: start of capability list, but no capability
3468 * list bit in status register, and offset 0xdc seems unused. */
3469 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3470
a41b2ff2
PB		 3471 /* I/O handler for memory-mapped I/O */
3472 s->rtl8139_mmio_io_addr =
2507c12a 3473 cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
5cf7a3ca 3474 DEVICE_LITTLE_ENDIAN);
a41b2ff2 3475
efd6dd45 3476 pci_register_bar(&s->dev, 0, 0x100,
0392a017 3477 PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
a41b2ff2 3478
efd6dd45 3479 pci_register_bar(&s->dev, 1, 0x100,
0392a017 3480 PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map);
a41b2ff2 3481
254111ec 3482 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3483
7165448a
WD		 3484 /* prepare eeprom */
3485 s->eeprom.contents[0] = 0x8129;
3486#if 1
3487 /* PCI vendor and device ID should be mirrored here */
3488 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3489 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3490#endif
3491 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3492 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3493 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3494
1673ad51
MM		 3495 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3496 dev->qdev.info->name, dev->qdev.id, s);
3497 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3498
3499 s->cplus_txbuffer = NULL;
3500 s->cplus_txbuffer_len = 0;
3501 s->cplus_txbuffer_offset = 0;
3b46e624 3502
05447803 3503 s->TimerExpire = 0;
74475455
PB		 3504 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3505 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
1ca4d09a
GN		 3506
3507 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3508
81a322d4 3509 return 0;
a41b2ff2 3510}
9d07d757 3511
0aab0d3a 3512static PCIDeviceInfo rtl8139_info = {
f82de8f0
GH		 3513 .qdev.name = "rtl8139",
3514 .qdev.size = sizeof(RTL8139State),
3515 .qdev.reset = rtl8139_reset,
be73cfe2 3516 .qdev.vmsd = &vmstate_rtl8139,
f82de8f0 3517 .init = pci_rtl8139_init,
e3936fa5 3518 .exit = pci_rtl8139_uninit,
5ee8ad71 3519 .romfile = "pxe-rtl8139.rom",
254111ec
GH		 3520 .qdev.props = (Property[]) {
3521 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3522 DEFINE_PROP_END_OF_LIST(),
3523 }
0aab0d3a
GH		 3524};
3525
9d07d757
PB		 3526static void rtl8139_register_devices(void)
3527{
0aab0d3a 3528 pci_qdev_register(&rtl8139_info);
9d07d757
PB		 3529}
3530
3531device_init(rtl8139_register_devices)
Qemu copy for testing