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[qemu.git] / hw / rtl8139.c
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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
6cadb320
FB		 26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
a41b2ff2
PB		 44 */
45
46#include "vl.h"
47
a41b2ff2
PB		 48/* debug RTL8139 card */
49//#define DEBUG_RTL8139 1
50
6cadb320
FB		 51#define PCI_FREQUENCY 33000000L
52
a41b2ff2
PB		 53/* debug RTL8139 card C+ mode only */
54//#define DEBUG_RTL8139CP 1
55
56/* RTL8139 provides frame CRC with received packet, this feature seems to be
57 ignored by most drivers, disabled by default */
58//#define RTL8139_CALCULATE_RXCRC 1
59
6cadb320
FB		 60/* Uncomment to enable on-board timer interrupts */
61//#define RTL8139_ONBOARD_TIMER 1
a41b2ff2
PB		 62
63#if defined(RTL8139_CALCULATE_RXCRC)
64/* For crc32 */
65#include <zlib.h>
66#endif
67
68#define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71/* arg % size for size which is a power of 2 */
72#define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
6cadb320
FB		 75#if defined (DEBUG_RTL8139)
76# define DEBUG_PRINT(x) do { printf x ; } while (0)
77#else
78# define DEBUG_PRINT(x)
79#endif
80
a41b2ff2
PB		 81/* Symbolic offsets to registers. */
82enum RTL8139_registers {
83 MAC0 = 0, /* Ethernet hardware address. */
84 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 85 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
86 /* Dump Tally Conter control register(64bit). C+ mode only */
87 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 88 RxBuf = 0x30,
89 ChipCmd = 0x37,
90 RxBufPtr = 0x38,
91 RxBufAddr = 0x3A,
92 IntrMask = 0x3C,
93 IntrStatus = 0x3E,
94 TxConfig = 0x40,
95 RxConfig = 0x44,
96 Timer = 0x48, /* A general-purpose counter. */
97 RxMissed = 0x4C, /* 24 bits valid, write clears. */
98 Cfg9346 = 0x50,
99 Config0 = 0x51,
100 Config1 = 0x52,
101 FlashReg = 0x54,
102 MediaStatus = 0x58,
103 Config3 = 0x59,
104 Config4 = 0x5A, /* absent on RTL-8139A */
105 HltClk = 0x5B,
106 MultiIntr = 0x5C,
107 PCIRevisionID = 0x5E,
108 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
109 BasicModeCtrl = 0x62,
110 BasicModeStatus = 0x64,
111 NWayAdvert = 0x66,
112 NWayLPAR = 0x68,
113 NWayExpansion = 0x6A,
114 /* Undocumented registers, but required for proper operation. */
115 FIFOTMS = 0x70, /* FIFO Control and test. */
116 CSCR = 0x74, /* Chip Status and Configuration Register. */
117 PARA78 = 0x78,
118 PARA7c = 0x7c, /* Magic transceiver parameter register. */
119 Config5 = 0xD8, /* absent on RTL-8139A */
120 /* C+ mode */
121 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
122 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
123 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
124 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
125 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
126 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
127 TxThresh = 0xEC, /* Early Tx threshold */
128};
129
130enum ClearBitMasks {
131 MultiIntrClear = 0xF000,
132 ChipCmdClear = 0xE2,
133 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
134};
135
136enum ChipCmdBits {
137 CmdReset = 0x10,
138 CmdRxEnb = 0x08,
139 CmdTxEnb = 0x04,
140 RxBufEmpty = 0x01,
141};
142
143/* C+ mode */
144enum CplusCmdBits {
6cadb320
FB		 145 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
146 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
147 CPlusRxEnb = 0x0002,
148 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 149};
150
151/* Interrupt register bits, using my own meaningful names. */
152enum IntrStatusBits {
153 PCIErr = 0x8000,
154 PCSTimeout = 0x4000,
155 RxFIFOOver = 0x40,
156 RxUnderrun = 0x20,
157 RxOverflow = 0x10,
158 TxErr = 0x08,
159 TxOK = 0x04,
160 RxErr = 0x02,
161 RxOK = 0x01,
162
163 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
164};
165
166enum TxStatusBits {
167 TxHostOwns = 0x2000,
168 TxUnderrun = 0x4000,
169 TxStatOK = 0x8000,
170 TxOutOfWindow = 0x20000000,
171 TxAborted = 0x40000000,
172 TxCarrierLost = 0x80000000,
173};
174enum RxStatusBits {
175 RxMulticast = 0x8000,
176 RxPhysical = 0x4000,
177 RxBroadcast = 0x2000,
178 RxBadSymbol = 0x0020,
179 RxRunt = 0x0010,
180 RxTooLong = 0x0008,
181 RxCRCErr = 0x0004,
182 RxBadAlign = 0x0002,
183 RxStatusOK = 0x0001,
184};
185
186/* Bits in RxConfig. */
187enum rx_mode_bits {
188 AcceptErr = 0x20,
189 AcceptRunt = 0x10,
190 AcceptBroadcast = 0x08,
191 AcceptMulticast = 0x04,
192 AcceptMyPhys = 0x02,
193 AcceptAllPhys = 0x01,
194};
195
196/* Bits in TxConfig. */
197enum tx_config_bits {
198
199 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
200 TxIFGShift = 24,
201 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
202 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
203 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
204 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
205
206 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
207 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
208 TxClearAbt = (1 << 0), /* Clear abort (WO) */
209 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
210 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
211
212 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
213};
214
215
216/* Transmit Status of All Descriptors (TSAD) Register */
217enum TSAD_bits {
218 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
219 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
220 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
221 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
222 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
223 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
224 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
225 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
226 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
227 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
228 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
229 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
230 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
231 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
232 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
233 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
234};
235
236
237/* Bits in Config1 */
238enum Config1Bits {
239 Cfg1_PM_Enable = 0x01,
240 Cfg1_VPD_Enable = 0x02,
241 Cfg1_PIO = 0x04,
242 Cfg1_MMIO = 0x08,
243 LWAKE = 0x10, /* not on 8139, 8139A */
244 Cfg1_Driver_Load = 0x20,
245 Cfg1_LED0 = 0x40,
246 Cfg1_LED1 = 0x80,
247 SLEEP = (1 << 1), /* only on 8139, 8139A */
248 PWRDN = (1 << 0), /* only on 8139, 8139A */
249};
250
251/* Bits in Config3 */
252enum Config3Bits {
253 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
254 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
255 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
256 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
257 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
258 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
259 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
260 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
261};
262
263/* Bits in Config4 */
264enum Config4Bits {
265 LWPTN = (1 << 2), /* not on 8139, 8139A */
266};
267
268/* Bits in Config5 */
269enum Config5Bits {
270 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
271 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
272 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
273 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
274 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
275 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
276 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
277};
278
279enum RxConfigBits {
280 /* rx fifo threshold */
281 RxCfgFIFOShift = 13,
282 RxCfgFIFONone = (7 << RxCfgFIFOShift),
283
284 /* Max DMA burst */
285 RxCfgDMAShift = 8,
286 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
287
288 /* rx ring buffer length */
289 RxCfgRcv8K = 0,
290 RxCfgRcv16K = (1 << 11),
291 RxCfgRcv32K = (1 << 12),
292 RxCfgRcv64K = (1 << 11) | (1 << 12),
293
294 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
295 RxNoWrap = (1 << 7),
296};
297
298/* Twister tuning parameters from RealTek.
299 Completely undocumented, but required to tune bad links on some boards. */
300/*
301enum CSCRBits {
302 CSCR_LinkOKBit = 0x0400,
303 CSCR_LinkChangeBit = 0x0800,
304 CSCR_LinkStatusBits = 0x0f000,
305 CSCR_LinkDownOffCmd = 0x003c0,
306 CSCR_LinkDownCmd = 0x0f3c0,
307*/
308enum CSCRBits {
309 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
310 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
311 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
312 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
313 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
314 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
315 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
316 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
317 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
318};
319
320enum Cfg9346Bits {
321 Cfg9346_Lock = 0x00,
322 Cfg9346_Unlock = 0xC0,
323};
324
325typedef enum {
326 CH_8139 = 0,
327 CH_8139_K,
328 CH_8139A,
329 CH_8139A_G,
330 CH_8139B,
331 CH_8130,
332 CH_8139C,
333 CH_8100,
334 CH_8100B_8139D,
335 CH_8101,
336} chip_t;
337
338enum chip_flags {
339 HasHltClk = (1 << 0),
340 HasLWake = (1 << 1),
341};
342
343#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
344 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
345#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
346
6cadb320
FB		 347#define RTL8139_PCI_REVID_8139 0x10
348#define RTL8139_PCI_REVID_8139CPLUS 0x20
349
350#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
351
a41b2ff2
PB		 352/* Size is 64 * 16bit words */
353#define EEPROM_9346_ADDR_BITS 6
354#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
355#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
356
357enum Chip9346Operation
358{
359 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
360 Chip9346_op_read = 0x80, /* 10 AAAAAA */
361 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
362 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
363 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
364 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
365 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
366};
367
368enum Chip9346Mode
369{
370 Chip9346_none = 0,
371 Chip9346_enter_command_mode,
372 Chip9346_read_command,
373 Chip9346_data_read, /* from output register */
374 Chip9346_data_write, /* to input register, then to contents at specified address */
375 Chip9346_data_write_all, /* to input register, then filling contents */
376};
377
378typedef struct EEprom9346
379{
380 uint16_t contents[EEPROM_9346_SIZE];
381 int mode;
382 uint32_t tick;
383 uint8_t address;
384 uint16_t input;
385 uint16_t output;
386
387 uint8_t eecs;
388 uint8_t eesk;
389 uint8_t eedi;
390 uint8_t eedo;
391} EEprom9346;
392
6cadb320
FB		 393typedef struct RTL8139TallyCounters
394{
395 /* Tally counters */
396 uint64_t TxOk;
397 uint64_t RxOk;
398 uint64_t TxERR;
399 uint32_t RxERR;
400 uint16_t MissPkt;
401 uint16_t FAE;
402 uint32_t Tx1Col;
403 uint32_t TxMCol;
404 uint64_t RxOkPhy;
405 uint64_t RxOkBrd;
406 uint32_t RxOkMul;
407 uint16_t TxAbt;
408 uint16_t TxUndrn;
409} RTL8139TallyCounters;
410
411/* Clears all tally counters */
412static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
413
414/* Writes tally counters to specified physical memory address */
415static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
416
417/* Loads values of tally counters from VM state file */
418static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
419
420/* Saves values of tally counters to VM state file */
421static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
422
a41b2ff2
PB		 423typedef struct RTL8139State {
424 uint8_t phys[8]; /* mac address */
425 uint8_t mult[8]; /* multicast mask array */
426
6cadb320 427 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 428 uint32_t TxAddr[4]; /* TxAddr0 */
429 uint32_t RxBuf; /* Receive buffer */
430 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
431 uint32_t RxBufPtr;
432 uint32_t RxBufAddr;
433
434 uint16_t IntrStatus;
435 uint16_t IntrMask;
436
437 uint32_t TxConfig;
438 uint32_t RxConfig;
439 uint32_t RxMissed;
440
441 uint16_t CSCR;
442
443 uint8_t Cfg9346;
444 uint8_t Config0;
445 uint8_t Config1;
446 uint8_t Config3;
447 uint8_t Config4;
448 uint8_t Config5;
449
450 uint8_t clock_enabled;
451 uint8_t bChipCmdState;
452
453 uint16_t MultiIntr;
454
455 uint16_t BasicModeCtrl;
456 uint16_t BasicModeStatus;
457 uint16_t NWayAdvert;
458 uint16_t NWayLPAR;
459 uint16_t NWayExpansion;
460
461 uint16_t CpCmd;
462 uint8_t TxThresh;
463
a41b2ff2
PB		 464 PCIDevice *pci_dev;
465 VLANClientState *vc;
466 uint8_t macaddr[6];
467 int rtl8139_mmio_io_addr;
468
469 /* C ring mode */
470 uint32_t currTxDesc;
471
472 /* C+ mode */
473 uint32_t currCPlusRxDesc;
474 uint32_t currCPlusTxDesc;
475
476 uint32_t RxRingAddrLO;
477 uint32_t RxRingAddrHI;
478
479 EEprom9346 eeprom;
6cadb320
FB		 480
481 uint32_t TCTR;
482 uint32_t TimerInt;
483 int64_t TCTR_base;
484
485 /* Tally counters */
486 RTL8139TallyCounters tally_counters;
487
488 /* Non-persistent data */
489 uint8_t *cplus_txbuffer;
490 int cplus_txbuffer_len;
491 int cplus_txbuffer_offset;
492
493 /* PCI interrupt timer */
494 QEMUTimer *timer;
495
a41b2ff2
PB		 496} RTL8139State;
497
498void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
499{
6cadb320 500 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
a41b2ff2
PB		 501
502 switch (command & Chip9346_op_mask)
503 {
504 case Chip9346_op_read:
505 {
506 eeprom->address = command & EEPROM_9346_ADDR_MASK;
507 eeprom->output = eeprom->contents[eeprom->address];
508 eeprom->eedo = 0;
509 eeprom->tick = 0;
510 eeprom->mode = Chip9346_data_read;
6cadb320
FB		 511 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
512 eeprom->address, eeprom->output));
a41b2ff2
PB		 513 }
514 break;
515
516 case Chip9346_op_write:
517 {
518 eeprom->address = command & EEPROM_9346_ADDR_MASK;
519 eeprom->input = 0;
520 eeprom->tick = 0;
521 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
6cadb320
FB		 522 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
523 eeprom->address));
a41b2ff2
PB		 524 }
525 break;
526 default:
527 eeprom->mode = Chip9346_none;
528 switch (command & Chip9346_op_ext_mask)
529 {
530 case Chip9346_op_write_enable:
6cadb320 531 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
a41b2ff2
PB		 532 break;
533 case Chip9346_op_write_all:
6cadb320 534 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
a41b2ff2
PB		 535 break;
536 case Chip9346_op_write_disable:
6cadb320 537 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
a41b2ff2
PB		 538 break;
539 }
540 break;
541 }
542}
543
544void prom9346_shift_clock(EEprom9346 *eeprom)
545{
546 int bit = eeprom->eedi?1:0;
547
548 ++ eeprom->tick;
549
6cadb320 550 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 551
552 switch (eeprom->mode)
553 {
554 case Chip9346_enter_command_mode:
555 if (bit)
556 {
557 eeprom->mode = Chip9346_read_command;
558 eeprom->tick = 0;
559 eeprom->input = 0;
6cadb320 560 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
a41b2ff2
PB		 561 }
562 break;
563
564 case Chip9346_read_command:
565 eeprom->input = (eeprom->input << 1) | (bit & 1);
566 if (eeprom->tick == 8)
567 {
568 prom9346_decode_command(eeprom, eeprom->input & 0xff);
569 }
570 break;
571
572 case Chip9346_data_read:
573 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
574 eeprom->output <<= 1;
575 if (eeprom->tick == 16)
576 {
6cadb320
FB		 577#if 1
578 // the FreeBSD drivers (rl and re) don't explicitly toggle
579 // CS between reads (or does setting Cfg9346 to 0 count too?),
580 // so we need to enter wait-for-command state here
581 eeprom->mode = Chip9346_enter_command_mode;
582 eeprom->input = 0;
583 eeprom->tick = 0;
584
585 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
586#else
587 // original behaviour
a41b2ff2
PB		 588 ++eeprom->address;
589 eeprom->address &= EEPROM_9346_ADDR_MASK;
590 eeprom->output = eeprom->contents[eeprom->address];
591 eeprom->tick = 0;
592
6cadb320
FB		 593 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
594 eeprom->address, eeprom->output));
a41b2ff2
PB		 595#endif
596 }
597 break;
598
599 case Chip9346_data_write:
600 eeprom->input = (eeprom->input << 1) | (bit & 1);
601 if (eeprom->tick == 16)
602 {
6cadb320
FB		 603 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
604 eeprom->address, eeprom->input));
605
a41b2ff2
PB		 606 eeprom->contents[eeprom->address] = eeprom->input;
607 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
608 eeprom->tick = 0;
609 eeprom->input = 0;
610 }
611 break;
612
613 case Chip9346_data_write_all:
614 eeprom->input = (eeprom->input << 1) | (bit & 1);
615 if (eeprom->tick == 16)
616 {
617 int i;
618 for (i = 0; i < EEPROM_9346_SIZE; i++)
619 {
620 eeprom->contents[i] = eeprom->input;
621 }
6cadb320
FB		 622 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
623 eeprom->input));
624
a41b2ff2
PB		 625 eeprom->mode = Chip9346_enter_command_mode;
626 eeprom->tick = 0;
627 eeprom->input = 0;
628 }
629 break;
630
631 default:
632 break;
633 }
634}
635
636int prom9346_get_wire(RTL8139State *s)
637{
638 EEprom9346 *eeprom = &s->eeprom;
639 if (!eeprom->eecs)
640 return 0;
641
642 return eeprom->eedo;
643}
644
645void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
646{
647 EEprom9346 *eeprom = &s->eeprom;
648 uint8_t old_eecs = eeprom->eecs;
649 uint8_t old_eesk = eeprom->eesk;
650
651 eeprom->eecs = eecs;
652 eeprom->eesk = eesk;
653 eeprom->eedi = eedi;
654
6cadb320
FB		 655 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
656 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 657
658 if (!old_eecs && eecs)
659 {
660 /* Synchronize start */
661 eeprom->tick = 0;
662 eeprom->input = 0;
663 eeprom->output = 0;
664 eeprom->mode = Chip9346_enter_command_mode;
665
6cadb320 666 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
a41b2ff2
PB		 667 }
668
669 if (!eecs)
670 {
6cadb320 671 DEBUG_PRINT(("=== eeprom: end access\n"));
a41b2ff2
PB		 672 return;
673 }
674
675 if (!old_eesk && eesk)
676 {
677 /* SK front rules */
678 prom9346_shift_clock(eeprom);
679 }
680}
681
682static void rtl8139_update_irq(RTL8139State *s)
683{
684 int isr;
685 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 686
80a34d67
PB		 687 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
688 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
6cadb320 689
d537cf6c 690 qemu_set_irq(s->pci_dev->irq[0], (isr != 0));
a41b2ff2
PB		 691}
692
693#define POLYNOMIAL 0x04c11db6
694
695/* From FreeBSD */
696/* XXX: optimize */
697static int compute_mcast_idx(const uint8_t *ep)
698{
699 uint32_t crc;
700 int carry, i, j;
701 uint8_t b;
702
703 crc = 0xffffffff;
704 for (i = 0; i < 6; i++) {
705 b = *ep++;
706 for (j = 0; j < 8; j++) {
707 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
708 crc <<= 1;
709 b >>= 1;
710 if (carry)
711 crc = ((crc ^ POLYNOMIAL) | carry);
712 }
713 }
714 return (crc >> 26);
715}
716
717static int rtl8139_RxWrap(RTL8139State *s)
718{
719 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
720 return (s->RxConfig & (1 << 7));
721}
722
723static int rtl8139_receiver_enabled(RTL8139State *s)
724{
725 return s->bChipCmdState & CmdRxEnb;
726}
727
728static int rtl8139_transmitter_enabled(RTL8139State *s)
729{
730 return s->bChipCmdState & CmdTxEnb;
731}
732
733static int rtl8139_cp_receiver_enabled(RTL8139State *s)
734{
735 return s->CpCmd & CPlusRxEnb;
736}
737
738static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
739{
740 return s->CpCmd & CPlusTxEnb;
741}
742
743static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
744{
745 if (s->RxBufAddr + size > s->RxBufferSize)
746 {
747 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
748
749 /* write packet data */
750 if (wrapped && s->RxBufferSize < 65536 && !rtl8139_RxWrap(s))
751 {
6cadb320 752 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
a41b2ff2
PB		 753
754 if (size > wrapped)
755 {
756 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
757 buf, size-wrapped );
758 }
759
760 /* reset buffer pointer */
761 s->RxBufAddr = 0;
762
763 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
764 buf + (size-wrapped), wrapped );
765
766 s->RxBufAddr = wrapped;
767
768 return;
769 }
770 }
771
772 /* non-wrapping path or overwrapping enabled */
773 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
774
775 s->RxBufAddr += size;
776}
777
778#define MIN_BUF_SIZE 60
779static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
780{
781#if TARGET_PHYS_ADDR_BITS > 32
782 return low | ((target_phys_addr_t)high << 32);
783#else
784 return low;
785#endif
786}
787
788static int rtl8139_can_receive(void *opaque)
789{
790 RTL8139State *s = opaque;
791 int avail;
792
aa1f17c1 793 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 794 if (!s->clock_enabled)
795 return 1;
796 if (!rtl8139_receiver_enabled(s))
797 return 1;
798
799 if (rtl8139_cp_receiver_enabled(s)) {
800 /* ??? Flow control not implemented in c+ mode.
801 This is a hack to work around slirp deficiencies anyway. */
802 return 1;
803 } else {
804 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
805 s->RxBufferSize);
806 return (avail == 0 || avail >= 1514);
807 }
808}
809
6cadb320 810static void rtl8139_do_receive(void *opaque, const uint8_t *buf, int size, int do_interrupt)
a41b2ff2
PB		 811{
812 RTL8139State *s = opaque;
813
814 uint32_t packet_header = 0;
815
816 uint8_t buf1[60];
817 static const uint8_t broadcast_macaddr[6] =
818 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
819
6cadb320 820 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
a41b2ff2
PB		 821
822 /* test if board clock is stopped */
823 if (!s->clock_enabled)
824 {
6cadb320 825 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
a41b2ff2
PB		 826 return;
827 }
828
829 /* first check if receiver is enabled */
830
831 if (!rtl8139_receiver_enabled(s))
832 {
6cadb320 833 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
a41b2ff2
PB		 834 return;
835 }
836
837 /* XXX: check this */
838 if (s->RxConfig & AcceptAllPhys) {
839 /* promiscuous: receive all */
6cadb320 840 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
a41b2ff2
PB		 841
842 } else {
843 if (!memcmp(buf, broadcast_macaddr, 6)) {
844 /* broadcast address */
845 if (!(s->RxConfig & AcceptBroadcast))
846 {
6cadb320
FB		 847 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
848
849 /* update tally counter */
850 ++s->tally_counters.RxERR;
851
a41b2ff2
PB		 852 return;
853 }
854
855 packet_header |= RxBroadcast;
856
6cadb320
FB		 857 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
858
859 /* update tally counter */
860 ++s->tally_counters.RxOkBrd;
861
a41b2ff2
PB		 862 } else if (buf[0] & 0x01) {
863 /* multicast */
864 if (!(s->RxConfig & AcceptMulticast))
865 {
6cadb320
FB		 866 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
867
868 /* update tally counter */
869 ++s->tally_counters.RxERR;
870
a41b2ff2
PB		 871 return;
872 }
873
874 int mcast_idx = compute_mcast_idx(buf);
875
876 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
877 {
6cadb320
FB		 878 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
879
880 /* update tally counter */
881 ++s->tally_counters.RxERR;
882
a41b2ff2
PB		 883 return;
884 }
885
886 packet_header |= RxMulticast;
887
6cadb320
FB		 888 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
889
890 /* update tally counter */
891 ++s->tally_counters.RxOkMul;
892
a41b2ff2
PB		 893 } else if (s->phys[0] == buf[0] &&
894 s->phys[1] == buf[1] &&
895 s->phys[2] == buf[2] &&
896 s->phys[3] == buf[3] &&
897 s->phys[4] == buf[4] &&
898 s->phys[5] == buf[5]) {
899 /* match */
900 if (!(s->RxConfig & AcceptMyPhys))
901 {
6cadb320
FB		 902 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
903
904 /* update tally counter */
905 ++s->tally_counters.RxERR;
906
a41b2ff2
PB		 907 return;
908 }
909
910 packet_header |= RxPhysical;
911
6cadb320
FB		 912 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
913
914 /* update tally counter */
915 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 916
917 } else {
918
6cadb320
FB		 919 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
920
921 /* update tally counter */
922 ++s->tally_counters.RxERR;
923
a41b2ff2
PB		 924 return;
925 }
926 }
927
928 /* if too small buffer, then expand it */
929 if (size < MIN_BUF_SIZE) {
930 memcpy(buf1, buf, size);
931 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
932 buf = buf1;
933 size = MIN_BUF_SIZE;
934 }
935
936 if (rtl8139_cp_receiver_enabled(s))
937 {
6cadb320 938 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
a41b2ff2
PB		 939
940 /* begin C+ receiver mode */
941
942/* w0 ownership flag */
943#define CP_RX_OWN (1<<31)
944/* w0 end of ring flag */
945#define CP_RX_EOR (1<<30)
946/* w0 bits 0...12 : buffer size */
947#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
948/* w1 tag available flag */
949#define CP_RX_TAVA (1<<16)
950/* w1 bits 0...15 : VLAN tag */
951#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
952/* w2 low 32bit of Rx buffer ptr */
953/* w3 high 32bit of Rx buffer ptr */
954
955 int descriptor = s->currCPlusRxDesc;
956 target_phys_addr_t cplus_rx_ring_desc;
957
958 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
959 cplus_rx_ring_desc += 16 * descriptor;
960
6cadb320
FB		 961 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
962 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
a41b2ff2
PB		 963
964 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
965
966 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
967 rxdw0 = le32_to_cpu(val);
968 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
969 rxdw1 = le32_to_cpu(val);
970 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
971 rxbufLO = le32_to_cpu(val);
972 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
973 rxbufHI = le32_to_cpu(val);
974
6cadb320 975 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 976 descriptor,
6cadb320 977 rxdw0, rxdw1, rxbufLO, rxbufHI));
a41b2ff2
PB		 978
979 if (!(rxdw0 & CP_RX_OWN))
980 {
6cadb320
FB		 981 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
982
a41b2ff2
PB		 983 s->IntrStatus |= RxOverflow;
984 ++s->RxMissed;
6cadb320
FB		 985
986 /* update tally counter */
987 ++s->tally_counters.RxERR;
988 ++s->tally_counters.MissPkt;
989
a41b2ff2
PB		 990 rtl8139_update_irq(s);
991 return;
992 }
993
994 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
995
6cadb320
FB		 996 /* TODO: scatter the packet over available receive ring descriptors space */
997
a41b2ff2
PB		 998 if (size+4 > rx_space)
999 {
6cadb320
FB		 1000 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1001 descriptor, rx_space, size));
1002
a41b2ff2
PB		 1003 s->IntrStatus |= RxOverflow;
1004 ++s->RxMissed;
6cadb320
FB		 1005
1006 /* update tally counter */
1007 ++s->tally_counters.RxERR;
1008 ++s->tally_counters.MissPkt;
1009
a41b2ff2
PB		 1010 rtl8139_update_irq(s);
1011 return;
1012 }
1013
1014 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1015
1016 /* receive/copy to target memory */
1017 cpu_physical_memory_write( rx_addr, buf, size );
1018
6cadb320
FB		 1019 if (s->CpCmd & CPlusRxChkSum)
1020 {
1021 /* do some packet checksumming */
1022 }
1023
a41b2ff2
PB		 1024 /* write checksum */
1025#if defined (RTL8139_CALCULATE_RXCRC)
1026 val = cpu_to_le32(crc32(~0, buf, size));
1027#else
1028 val = 0;
1029#endif
1030 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1031
1032/* first segment of received packet flag */
1033#define CP_RX_STATUS_FS (1<<29)
1034/* last segment of received packet flag */
1035#define CP_RX_STATUS_LS (1<<28)
1036/* multicast packet flag */
1037#define CP_RX_STATUS_MAR (1<<26)
1038/* physical-matching packet flag */
1039#define CP_RX_STATUS_PAM (1<<25)
1040/* broadcast packet flag */
1041#define CP_RX_STATUS_BAR (1<<24)
1042/* runt packet flag */
1043#define CP_RX_STATUS_RUNT (1<<19)
1044/* crc error flag */
1045#define CP_RX_STATUS_CRC (1<<18)
1046/* IP checksum error flag */
1047#define CP_RX_STATUS_IPF (1<<15)
1048/* UDP checksum error flag */
1049#define CP_RX_STATUS_UDPF (1<<14)
1050/* TCP checksum error flag */
1051#define CP_RX_STATUS_TCPF (1<<13)
1052
1053 /* transfer ownership to target */
1054 rxdw0 &= ~CP_RX_OWN;
1055
1056 /* set first segment bit */
1057 rxdw0 |= CP_RX_STATUS_FS;
1058
1059 /* set last segment bit */
1060 rxdw0 |= CP_RX_STATUS_LS;
1061
1062 /* set received packet type flags */
1063 if (packet_header & RxBroadcast)
1064 rxdw0 |= CP_RX_STATUS_BAR;
1065 if (packet_header & RxMulticast)
1066 rxdw0 |= CP_RX_STATUS_MAR;
1067 if (packet_header & RxPhysical)
1068 rxdw0 |= CP_RX_STATUS_PAM;
1069
1070 /* set received size */
1071 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1072 rxdw0 |= (size+4);
1073
1074 /* reset VLAN tag flag */
1075 rxdw1 &= ~CP_RX_TAVA;
1076
1077 /* update ring data */
1078 val = cpu_to_le32(rxdw0);
1079 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1080 val = cpu_to_le32(rxdw1);
1081 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1082
6cadb320
FB		 1083 /* update tally counter */
1084 ++s->tally_counters.RxOk;
1085
a41b2ff2
PB		 1086 /* seek to next Rx descriptor */
1087 if (rxdw0 & CP_RX_EOR)
1088 {
1089 s->currCPlusRxDesc = 0;
1090 }
1091 else
1092 {
1093 ++s->currCPlusRxDesc;
1094 }
1095
6cadb320 1096 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
a41b2ff2
PB		 1097
1098 }
1099 else
1100 {
6cadb320
FB		 1101 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1102
a41b2ff2
PB		 1103 /* begin ring receiver mode */
1104 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1105
1106 /* if receiver buffer is empty then avail == 0 */
1107
1108 if (avail != 0 && size + 8 >= avail)
1109 {
6cadb320
FB		 1110 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1111 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1112
a41b2ff2
PB		 1113 s->IntrStatus |= RxOverflow;
1114 ++s->RxMissed;
1115 rtl8139_update_irq(s);
1116 return;
1117 }
1118
1119 packet_header |= RxStatusOK;
1120
1121 packet_header |= (((size+4) << 16) & 0xffff0000);
1122
1123 /* write header */
1124 uint32_t val = cpu_to_le32(packet_header);
1125
1126 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1127
1128 rtl8139_write_buffer(s, buf, size);
1129
1130 /* write checksum */
1131#if defined (RTL8139_CALCULATE_RXCRC)
1132 val = cpu_to_le32(crc32(~0, buf, size));
1133#else
1134 val = 0;
1135#endif
1136
1137 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1138
1139 /* correct buffer write pointer */
1140 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1141
1142 /* now we can signal we have received something */
1143
6cadb320
FB		 1144 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1145 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 1146 }
1147
1148 s->IntrStatus |= RxOK;
6cadb320
FB		 1149
1150 if (do_interrupt)
1151 {
1152 rtl8139_update_irq(s);
1153 }
1154}
1155
1156static void rtl8139_receive(void *opaque, const uint8_t *buf, int size)
1157{
1158 rtl8139_do_receive(opaque, buf, size, 1);
a41b2ff2
PB		 1159}
1160
1161static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1162{
1163 s->RxBufferSize = bufferSize;
1164 s->RxBufPtr = 0;
1165 s->RxBufAddr = 0;
1166}
1167
1168static void rtl8139_reset(RTL8139State *s)
1169{
1170 int i;
1171
1172 /* restore MAC address */
1173 memcpy(s->phys, s->macaddr, 6);
1174
1175 /* reset interrupt mask */
1176 s->IntrStatus = 0;
1177 s->IntrMask = 0;
1178
1179 rtl8139_update_irq(s);
1180
1181 /* prepare eeprom */
1182 s->eeprom.contents[0] = 0x8129;
6cadb320
FB		 1183#if 1
1184 // PCI vendor and device ID should be mirrored here
1185 s->eeprom.contents[1] = 0x10ec;
1186 s->eeprom.contents[2] = 0x8139;
1187#endif
290a0933
TS		 1188
1189 s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8;
1190 s->eeprom.contents[8] = s->macaddr[2] | s->macaddr[3] << 8;
1191 s->eeprom.contents[9] = s->macaddr[4] | s->macaddr[5] << 8;
a41b2ff2
PB		 1192
1193 /* mark all status registers as owned by host */
1194 for (i = 0; i < 4; ++i)
1195 {
1196 s->TxStatus[i] = TxHostOwns;
1197 }
1198
1199 s->currTxDesc = 0;
1200 s->currCPlusRxDesc = 0;
1201 s->currCPlusTxDesc = 0;
1202
1203 s->RxRingAddrLO = 0;
1204 s->RxRingAddrHI = 0;
1205
1206 s->RxBuf = 0;
1207
1208 rtl8139_reset_rxring(s, 8192);
1209
1210 /* ACK the reset */
1211 s->TxConfig = 0;
1212
1213#if 0
1214// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1215 s->clock_enabled = 0;
1216#else
6cadb320 1217 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1218 s->clock_enabled = 1;
1219#endif
1220
1221 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1222
1223 /* set initial state data */
1224 s->Config0 = 0x0; /* No boot ROM */
1225 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1226 s->Config3 = 0x1; /* fast back-to-back compatible */
1227 s->Config5 = 0x0;
1228
1229 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1230
1231 s->CpCmd = 0x0; /* reset C+ mode */
1232
1233// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1234// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1235 s->BasicModeCtrl = 0x1000; // autonegotiation
1236
1237 s->BasicModeStatus = 0x7809;
1238 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1239 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1240 s->BasicModeStatus |= 0x0004; /* link is up */
1241
1242 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1243 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1244 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1245
1246 /* also reset timer and disable timer interrupt */
1247 s->TCTR = 0;
1248 s->TimerInt = 0;
1249 s->TCTR_base = 0;
1250
1251 /* reset tally counters */
1252 RTL8139TallyCounters_clear(&s->tally_counters);
1253}
1254
1255void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1256{
1257 counters->TxOk = 0;
1258 counters->RxOk = 0;
1259 counters->TxERR = 0;
1260 counters->RxERR = 0;
1261 counters->MissPkt = 0;
1262 counters->FAE = 0;
1263 counters->Tx1Col = 0;
1264 counters->TxMCol = 0;
1265 counters->RxOkPhy = 0;
1266 counters->RxOkBrd = 0;
1267 counters->RxOkMul = 0;
1268 counters->TxAbt = 0;
1269 counters->TxUndrn = 0;
1270}
1271
1272static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1273{
1274 uint16_t val16;
1275 uint32_t val32;
1276 uint64_t val64;
1277
1278 val64 = cpu_to_le64(tally_counters->TxOk);
1279 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1280
1281 val64 = cpu_to_le64(tally_counters->RxOk);
1282 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1283
1284 val64 = cpu_to_le64(tally_counters->TxERR);
1285 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1286
1287 val32 = cpu_to_le32(tally_counters->RxERR);
1288 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1289
1290 val16 = cpu_to_le16(tally_counters->MissPkt);
1291 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1292
1293 val16 = cpu_to_le16(tally_counters->FAE);
1294 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1295
1296 val32 = cpu_to_le32(tally_counters->Tx1Col);
1297 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1298
1299 val32 = cpu_to_le32(tally_counters->TxMCol);
1300 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1301
1302 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1303 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1304
1305 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1306 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1307
1308 val32 = cpu_to_le32(tally_counters->RxOkMul);
1309 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1310
1311 val16 = cpu_to_le16(tally_counters->TxAbt);
1312 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1313
1314 val16 = cpu_to_le16(tally_counters->TxUndrn);
1315 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1316}
1317
1318/* Loads values of tally counters from VM state file */
1319static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1320{
1321 qemu_get_be64s(f, &tally_counters->TxOk);
1322 qemu_get_be64s(f, &tally_counters->RxOk);
1323 qemu_get_be64s(f, &tally_counters->TxERR);
1324 qemu_get_be32s(f, &tally_counters->RxERR);
1325 qemu_get_be16s(f, &tally_counters->MissPkt);
1326 qemu_get_be16s(f, &tally_counters->FAE);
1327 qemu_get_be32s(f, &tally_counters->Tx1Col);
1328 qemu_get_be32s(f, &tally_counters->TxMCol);
1329 qemu_get_be64s(f, &tally_counters->RxOkPhy);
1330 qemu_get_be64s(f, &tally_counters->RxOkBrd);
1331 qemu_get_be32s(f, &tally_counters->RxOkMul);
1332 qemu_get_be16s(f, &tally_counters->TxAbt);
1333 qemu_get_be16s(f, &tally_counters->TxUndrn);
1334}
1335
1336/* Saves values of tally counters to VM state file */
1337static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1338{
1339 qemu_put_be64s(f, &tally_counters->TxOk);
1340 qemu_put_be64s(f, &tally_counters->RxOk);
1341 qemu_put_be64s(f, &tally_counters->TxERR);
1342 qemu_put_be32s(f, &tally_counters->RxERR);
1343 qemu_put_be16s(f, &tally_counters->MissPkt);
1344 qemu_put_be16s(f, &tally_counters->FAE);
1345 qemu_put_be32s(f, &tally_counters->Tx1Col);
1346 qemu_put_be32s(f, &tally_counters->TxMCol);
1347 qemu_put_be64s(f, &tally_counters->RxOkPhy);
1348 qemu_put_be64s(f, &tally_counters->RxOkBrd);
1349 qemu_put_be32s(f, &tally_counters->RxOkMul);
1350 qemu_put_be16s(f, &tally_counters->TxAbt);
1351 qemu_put_be16s(f, &tally_counters->TxUndrn);
a41b2ff2
PB		 1352}
1353
1354static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1355{
1356 val &= 0xff;
1357
6cadb320 1358 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
a41b2ff2
PB		 1359
1360 if (val & CmdReset)
1361 {
6cadb320 1362 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
a41b2ff2
PB		 1363 rtl8139_reset(s);
1364 }
1365 if (val & CmdRxEnb)
1366 {
6cadb320 1367 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
718da2b9
FB		 1368
1369 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1370 }
1371 if (val & CmdTxEnb)
1372 {
6cadb320 1373 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
718da2b9
FB		 1374
1375 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1376 }
1377
1378 /* mask unwriteable bits */
1379 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1380
1381 /* Deassert reset pin before next read */
1382 val &= ~CmdReset;
1383
1384 s->bChipCmdState = val;
1385}
1386
1387static int rtl8139_RxBufferEmpty(RTL8139State *s)
1388{
1389 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1390
1391 if (unread != 0)
1392 {
6cadb320 1393 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
a41b2ff2
PB		 1394 return 0;
1395 }
1396
6cadb320 1397 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
a41b2ff2
PB		 1398
1399 return 1;
1400}
1401
1402static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1403{
1404 uint32_t ret = s->bChipCmdState;
1405
1406 if (rtl8139_RxBufferEmpty(s))
1407 ret |= RxBufEmpty;
1408
6cadb320 1409 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
a41b2ff2
PB		 1410
1411 return ret;
1412}
1413
1414static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1415{
1416 val &= 0xffff;
1417
6cadb320 1418 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1419
1420 /* mask unwriteable bits */
1421 val = SET_MASKED(val, 0xff84, s->CpCmd);
1422
1423 s->CpCmd = val;
1424}
1425
1426static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1427{
1428 uint32_t ret = s->CpCmd;
1429
6cadb320
FB		 1430 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1431
1432 return ret;
1433}
1434
1435static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1436{
1437 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1438}
1439
1440static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1441{
1442 uint32_t ret = 0;
1443
1444 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1445
1446 return ret;
1447}
1448
1449int rtl8139_config_writeable(RTL8139State *s)
1450{
1451 if (s->Cfg9346 & Cfg9346_Unlock)
1452 {
1453 return 1;
1454 }
1455
6cadb320 1456 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
a41b2ff2
PB		 1457
1458 return 0;
1459}
1460
1461static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1462{
1463 val &= 0xffff;
1464
6cadb320 1465 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1466
1467 /* mask unwriteable bits */
1468 uint32 mask = 0x4cff;
1469
1470 if (1 || !rtl8139_config_writeable(s))
1471 {
1472 /* Speed setting and autonegotiation enable bits are read-only */
1473 mask |= 0x3000;
1474 /* Duplex mode setting is read-only */
1475 mask |= 0x0100;
1476 }
1477
1478 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1479
1480 s->BasicModeCtrl = val;
1481}
1482
1483static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1484{
1485 uint32_t ret = s->BasicModeCtrl;
1486
6cadb320 1487 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1488
1489 return ret;
1490}
1491
1492static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1493{
1494 val &= 0xffff;
1495
6cadb320 1496 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1497
1498 /* mask unwriteable bits */
1499 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1500
1501 s->BasicModeStatus = val;
1502}
1503
1504static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1505{
1506 uint32_t ret = s->BasicModeStatus;
1507
6cadb320 1508 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1509
1510 return ret;
1511}
1512
1513static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1514{
1515 val &= 0xff;
1516
6cadb320 1517 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
a41b2ff2
PB		 1518
1519 /* mask unwriteable bits */
1520 val = SET_MASKED(val, 0x31, s->Cfg9346);
1521
1522 uint32_t opmode = val & 0xc0;
1523 uint32_t eeprom_val = val & 0xf;
1524
1525 if (opmode == 0x80) {
1526 /* eeprom access */
1527 int eecs = (eeprom_val & 0x08)?1:0;
1528 int eesk = (eeprom_val & 0x04)?1:0;
1529 int eedi = (eeprom_val & 0x02)?1:0;
1530 prom9346_set_wire(s, eecs, eesk, eedi);
1531 } else if (opmode == 0x40) {
1532 /* Reset. */
1533 val = 0;
1534 rtl8139_reset(s);
1535 }
1536
1537 s->Cfg9346 = val;
1538}
1539
1540static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1541{
1542 uint32_t ret = s->Cfg9346;
1543
1544 uint32_t opmode = ret & 0xc0;
1545
1546 if (opmode == 0x80)
1547 {
1548 /* eeprom access */
1549 int eedo = prom9346_get_wire(s);
1550 if (eedo)
1551 {
1552 ret |= 0x01;
1553 }
1554 else
1555 {
1556 ret &= ~0x01;
1557 }
1558 }
1559
6cadb320 1560 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
a41b2ff2
PB		 1561
1562 return ret;
1563}
1564
1565static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1566{
1567 val &= 0xff;
1568
6cadb320 1569 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
a41b2ff2
PB		 1570
1571 if (!rtl8139_config_writeable(s))
1572 return;
1573
1574 /* mask unwriteable bits */
1575 val = SET_MASKED(val, 0xf8, s->Config0);
1576
1577 s->Config0 = val;
1578}
1579
1580static uint32_t rtl8139_Config0_read(RTL8139State *s)
1581{
1582 uint32_t ret = s->Config0;
1583
6cadb320 1584 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
a41b2ff2
PB		 1585
1586 return ret;
1587}
1588
1589static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1590{
1591 val &= 0xff;
1592
6cadb320 1593 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
a41b2ff2
PB		 1594
1595 if (!rtl8139_config_writeable(s))
1596 return;
1597
1598 /* mask unwriteable bits */
1599 val = SET_MASKED(val, 0xC, s->Config1);
1600
1601 s->Config1 = val;
1602}
1603
1604static uint32_t rtl8139_Config1_read(RTL8139State *s)
1605{
1606 uint32_t ret = s->Config1;
1607
6cadb320 1608 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
a41b2ff2
PB		 1609
1610 return ret;
1611}
1612
1613static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1614{
1615 val &= 0xff;
1616
6cadb320 1617 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
a41b2ff2
PB		 1618
1619 if (!rtl8139_config_writeable(s))
1620 return;
1621
1622 /* mask unwriteable bits */
1623 val = SET_MASKED(val, 0x8F, s->Config3);
1624
1625 s->Config3 = val;
1626}
1627
1628static uint32_t rtl8139_Config3_read(RTL8139State *s)
1629{
1630 uint32_t ret = s->Config3;
1631
6cadb320 1632 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
a41b2ff2
PB		 1633
1634 return ret;
1635}
1636
1637static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1638{
1639 val &= 0xff;
1640
6cadb320 1641 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
a41b2ff2
PB		 1642
1643 if (!rtl8139_config_writeable(s))
1644 return;
1645
1646 /* mask unwriteable bits */
1647 val = SET_MASKED(val, 0x0a, s->Config4);
1648
1649 s->Config4 = val;
1650}
1651
1652static uint32_t rtl8139_Config4_read(RTL8139State *s)
1653{
1654 uint32_t ret = s->Config4;
1655
6cadb320 1656 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
a41b2ff2
PB		 1657
1658 return ret;
1659}
1660
1661static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1662{
1663 val &= 0xff;
1664
6cadb320 1665 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
a41b2ff2
PB		 1666
1667 /* mask unwriteable bits */
1668 val = SET_MASKED(val, 0x80, s->Config5);
1669
1670 s->Config5 = val;
1671}
1672
1673static uint32_t rtl8139_Config5_read(RTL8139State *s)
1674{
1675 uint32_t ret = s->Config5;
1676
6cadb320 1677 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
a41b2ff2
PB		 1678
1679 return ret;
1680}
1681
1682static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1683{
1684 if (!rtl8139_transmitter_enabled(s))
1685 {
6cadb320 1686 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1687 return;
1688 }
1689
6cadb320 1690 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1691
1692 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1693
1694 s->TxConfig = val;
1695}
1696
1697static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1698{
6cadb320
FB		 1699 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1700
1701 uint32_t tc = s->TxConfig;
1702 tc &= 0xFFFFFF00;
1703 tc |= (val & 0x000000FF);
1704 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1705}
1706
1707static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1708{
1709 uint32_t ret = s->TxConfig;
1710
6cadb320 1711 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
a41b2ff2
PB		 1712
1713 return ret;
1714}
1715
1716static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1717{
6cadb320 1718 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1719
1720 /* mask unwriteable bits */
1721 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1722
1723 s->RxConfig = val;
1724
1725 /* reset buffer size and read/write pointers */
1726 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1727
6cadb320 1728 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
a41b2ff2
PB		 1729}
1730
1731static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1732{
1733 uint32_t ret = s->RxConfig;
1734
6cadb320 1735 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
a41b2ff2
PB		 1736
1737 return ret;
1738}
1739
718da2b9
FB		 1740static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1741{
1742 if (!size)
1743 {
1744 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1745 return;
1746 }
1747
1748 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1749 {
1750 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1751 rtl8139_do_receive(s, buf, size, do_interrupt);
1752 }
1753 else
1754 {
1755 qemu_send_packet(s->vc, buf, size);
1756 }
1757}
1758
a41b2ff2
PB		 1759static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1760{
1761 if (!rtl8139_transmitter_enabled(s))
1762 {
6cadb320
FB		 1763 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1764 descriptor));
a41b2ff2
PB		 1765 return 0;
1766 }
1767
1768 if (s->TxStatus[descriptor] & TxHostOwns)
1769 {
6cadb320
FB		 1770 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1771 descriptor, s->TxStatus[descriptor]));
a41b2ff2
PB		 1772 return 0;
1773 }
1774
6cadb320 1775 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
a41b2ff2
PB		 1776
1777 int txsize = s->TxStatus[descriptor] & 0x1fff;
1778 uint8_t txbuffer[0x2000];
1779
6cadb320
FB		 1780 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1781 txsize, s->TxAddr[descriptor]));
a41b2ff2 1782
6cadb320 1783 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1784
1785 /* Mark descriptor as transferred */
1786 s->TxStatus[descriptor] |= TxHostOwns;
1787 s->TxStatus[descriptor] |= TxStatOK;
1788
718da2b9 1789 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
6cadb320
FB		 1790
1791 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
a41b2ff2
PB		 1792
1793 /* update interrupt */
1794 s->IntrStatus |= TxOK;
1795 rtl8139_update_irq(s);
1796
1797 return 1;
1798}
1799
718da2b9
FB		 1800/* structures and macros for task offloading */
1801typedef struct ip_header
1802{
1803 uint8_t ip_ver_len; /* version and header length */
1804 uint8_t ip_tos; /* type of service */
1805 uint16_t ip_len; /* total length */
1806 uint16_t ip_id; /* identification */
1807 uint16_t ip_off; /* fragment offset field */
1808 uint8_t ip_ttl; /* time to live */
1809 uint8_t ip_p; /* protocol */
1810 uint16_t ip_sum; /* checksum */
1811 uint32_t ip_src,ip_dst; /* source and dest address */
1812} ip_header;
1813
1814#define IP_HEADER_VERSION_4 4
1815#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1816#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1817
1818typedef struct tcp_header
1819{
1820 uint16_t th_sport; /* source port */
1821 uint16_t th_dport; /* destination port */
1822 uint32_t th_seq; /* sequence number */
1823 uint32_t th_ack; /* acknowledgement number */
1824 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1825 uint16_t th_win; /* window */
1826 uint16_t th_sum; /* checksum */
1827 uint16_t th_urp; /* urgent pointer */
1828} tcp_header;
1829
1830typedef struct udp_header
1831{
1832 uint16_t uh_sport; /* source port */
1833 uint16_t uh_dport; /* destination port */
1834 uint16_t uh_ulen; /* udp length */
1835 uint16_t uh_sum; /* udp checksum */
1836} udp_header;
1837
1838typedef struct ip_pseudo_header
1839{
1840 uint32_t ip_src;
1841 uint32_t ip_dst;
1842 uint8_t zeros;
1843 uint8_t ip_proto;
1844 uint16_t ip_payload;
1845} ip_pseudo_header;
1846
1847#define IP_PROTO_TCP 6
1848#define IP_PROTO_UDP 17
1849
1850#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1851#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1852#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1853
1854#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1855
1856#define TCP_FLAG_FIN 0x01
1857#define TCP_FLAG_PUSH 0x08
1858
1859/* produces ones' complement sum of data */
1860static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1861{
1862 uint32_t result = 0;
1863
1864 for (; len > 1; data+=2, len-=2)
1865 {
1866 result += *(uint16_t*)data;
1867 }
1868
1869 /* add the remainder byte */
1870 if (len)
1871 {
1872 uint8_t odd[2] = {*data, 0};
1873 result += *(uint16_t*)odd;
1874 }
1875
1876 while (result>>16)
1877 result = (result & 0xffff) + (result >> 16);
1878
1879 return result;
1880}
1881
1882static uint16_t ip_checksum(void *data, size_t len)
1883{
1884 return ~ones_complement_sum((uint8_t*)data, len);
1885}
1886
a41b2ff2
PB		 1887static int rtl8139_cplus_transmit_one(RTL8139State *s)
1888{
1889 if (!rtl8139_transmitter_enabled(s))
1890 {
6cadb320 1891 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
a41b2ff2
PB		 1892 return 0;
1893 }
1894
1895 if (!rtl8139_cp_transmitter_enabled(s))
1896 {
6cadb320 1897 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
a41b2ff2
PB		 1898 return 0 ;
1899 }
1900
1901 int descriptor = s->currCPlusTxDesc;
1902
1903 target_phys_addr_t cplus_tx_ring_desc =
1904 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1905
1906 /* Normal priority ring */
1907 cplus_tx_ring_desc += 16 * descriptor;
1908
6cadb320
FB		 1909 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1910 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
a41b2ff2
PB		 1911
1912 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1913
1914 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1915 txdw0 = le32_to_cpu(val);
1916 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1917 txdw1 = le32_to_cpu(val);
1918 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1919 txbufLO = le32_to_cpu(val);
1920 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1921 txbufHI = le32_to_cpu(val);
1922
6cadb320 1923 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 1924 descriptor,
6cadb320 1925 txdw0, txdw1, txbufLO, txbufHI));
a41b2ff2
PB		 1926
1927/* w0 ownership flag */
1928#define CP_TX_OWN (1<<31)
1929/* w0 end of ring flag */
1930#define CP_TX_EOR (1<<30)
1931/* first segment of received packet flag */
1932#define CP_TX_FS (1<<29)
1933/* last segment of received packet flag */
1934#define CP_TX_LS (1<<28)
1935/* large send packet flag */
1936#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1937/* large send MSS mask, bits 16...25 */
1938#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1939
a41b2ff2
PB		 1940/* IP checksum offload flag */
1941#define CP_TX_IPCS (1<<18)
1942/* UDP checksum offload flag */
1943#define CP_TX_UDPCS (1<<17)
1944/* TCP checksum offload flag */
1945#define CP_TX_TCPCS (1<<16)
1946
1947/* w0 bits 0...15 : buffer size */
1948#define CP_TX_BUFFER_SIZE (1<<16)
1949#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1950/* w1 tag available flag */
1951#define CP_RX_TAGC (1<<17)
1952/* w1 bits 0...15 : VLAN tag */
1953#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1954/* w2 low 32bit of Rx buffer ptr */
1955/* w3 high 32bit of Rx buffer ptr */
1956
1957/* set after transmission */
1958/* FIFO underrun flag */
1959#define CP_TX_STATUS_UNF (1<<25)
1960/* transmit error summary flag, valid if set any of three below */
1961#define CP_TX_STATUS_TES (1<<23)
1962/* out-of-window collision flag */
1963#define CP_TX_STATUS_OWC (1<<22)
1964/* link failure flag */
1965#define CP_TX_STATUS_LNKF (1<<21)
1966/* excessive collisions flag */
1967#define CP_TX_STATUS_EXC (1<<20)
1968
1969 if (!(txdw0 & CP_TX_OWN))
1970 {
6cadb320 1971 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
a41b2ff2
PB		 1972 return 0 ;
1973 }
1974
6cadb320
FB		 1975 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1976
1977 if (txdw0 & CP_TX_FS)
1978 {
1979 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1980
1981 /* reset internal buffer offset */
1982 s->cplus_txbuffer_offset = 0;
1983 }
a41b2ff2
PB		 1984
1985 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1986 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1987
6cadb320
FB		 1988 /* make sure we have enough space to assemble the packet */
1989 if (!s->cplus_txbuffer)
1990 {
1991 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
1992 s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
1993 s->cplus_txbuffer_offset = 0;
718da2b9
FB		 1994
1995 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
6cadb320
FB		 1996 }
1997
1998 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
1999 {
2000 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2001 s->cplus_txbuffer = realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2002
6cadb320
FB		 2003 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2004 }
2005
2006 if (!s->cplus_txbuffer)
2007 {
2008 /* out of memory */
a41b2ff2 2009
6cadb320
FB		 2010 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2011
2012 /* update tally counter */
2013 ++s->tally_counters.TxERR;
2014 ++s->tally_counters.TxAbt;
2015
2016 return 0;
2017 }
2018
2019 /* append more data to the packet */
2020
2021 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2022 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2023
2024 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2025 s->cplus_txbuffer_offset += txsize;
2026
2027 /* seek to next Rx descriptor */
2028 if (txdw0 & CP_TX_EOR)
2029 {
2030 s->currCPlusTxDesc = 0;
2031 }
2032 else
2033 {
2034 ++s->currCPlusTxDesc;
2035 if (s->currCPlusTxDesc >= 64)
2036 s->currCPlusTxDesc = 0;
2037 }
a41b2ff2
PB		 2038
2039 /* transfer ownership to target */
2040 txdw0 &= ~CP_RX_OWN;
2041
2042 /* reset error indicator bits */
2043 txdw0 &= ~CP_TX_STATUS_UNF;
2044 txdw0 &= ~CP_TX_STATUS_TES;
2045 txdw0 &= ~CP_TX_STATUS_OWC;
2046 txdw0 &= ~CP_TX_STATUS_LNKF;
2047 txdw0 &= ~CP_TX_STATUS_EXC;
2048
2049 /* update ring data */
2050 val = cpu_to_le32(txdw0);
2051 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2052// val = cpu_to_le32(txdw1);
2053// cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2054
6cadb320
FB		 2055 /* Now decide if descriptor being processed is holding the last segment of packet */
2056 if (txdw0 & CP_TX_LS)
a41b2ff2 2057 {
6cadb320
FB		 2058 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2059
2060 /* can transfer fully assembled packet */
2061
2062 uint8_t *saved_buffer = s->cplus_txbuffer;
2063 int saved_size = s->cplus_txbuffer_offset;
2064 int saved_buffer_len = s->cplus_txbuffer_len;
2065
2066 /* reset the card space to protect from recursive call */
2067 s->cplus_txbuffer = NULL;
2068 s->cplus_txbuffer_offset = 0;
2069 s->cplus_txbuffer_len = 0;
2070
718da2b9 2071 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320
FB		 2072 {
2073 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2074
2075 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2076 #define ETH_HLEN 14
718da2b9 2077 #define ETH_MTU 1500
6cadb320
FB		 2078
2079 /* ip packet header */
718da2b9 2080 ip_header *ip = 0;
6cadb320 2081 int hlen = 0;
718da2b9
FB		 2082 uint8_t ip_protocol = 0;
2083 uint16_t ip_data_len = 0;
6cadb320 2084
718da2b9
FB		 2085 uint8_t *eth_payload_data = 0;
2086 size_t eth_payload_len = 0;
6cadb320 2087
718da2b9 2088 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2089 if (proto == ETH_P_IP)
2090 {
2091 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2092
2093 /* not aligned */
718da2b9
FB		 2094 eth_payload_data = saved_buffer + ETH_HLEN;
2095 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2096
718da2b9 2097 ip = (ip_header*)eth_payload_data;
6cadb320 2098
718da2b9
FB		 2099 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2100 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
6cadb320
FB		 2101 ip = NULL;
2102 } else {
718da2b9
FB		 2103 hlen = IP_HEADER_LENGTH(ip);
2104 ip_protocol = ip->ip_p;
2105 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2106 }
2107 }
2108
2109 if (ip)
2110 {
2111 if (txdw0 & CP_TX_IPCS)
2112 {
2113 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2114
718da2b9 2115 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2116 /* bad packet header len */
2117 /* or packet too short */
2118 }
2119 else
2120 {
2121 ip->ip_sum = 0;
718da2b9 2122 ip->ip_sum = ip_checksum(ip, hlen);
6cadb320
FB		 2123 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2124 }
2125 }
2126
718da2b9 2127 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2128 {
718da2b9
FB		 2129#if defined (DEBUG_RTL8139)
2130 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2131#endif
2132 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2133 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
6cadb320 2134
718da2b9
FB		 2135 int tcp_send_offset = 0;
2136 int send_count = 0;
6cadb320
FB		 2137
2138 /* maximum IP header length is 60 bytes */
2139 uint8_t saved_ip_header[60];
6cadb320 2140
718da2b9
FB		 2141 /* save IP header template; data area is used in tcp checksum calculation */
2142 memcpy(saved_ip_header, eth_payload_data, hlen);
2143
2144 /* a placeholder for checksum calculation routine in tcp case */
2145 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2146 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2147
2148 /* pointer to TCP header */
2149 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2150
2151 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2152
2153 /* ETH_MTU = ip header len + tcp header len + payload */
2154 int tcp_data_len = ip_data_len - tcp_hlen;
2155 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2156
2157 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2158 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2159
2160 /* note the cycle below overwrites IP header data,
2161 but restores it from saved_ip_header before sending packet */
2162
2163 int is_last_frame = 0;
2164
2165 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2166 {
2167 uint16_t chunk_size = tcp_chunk_size;
2168
2169 /* check if this is the last frame */
2170 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2171 {
2172 is_last_frame = 1;
2173 chunk_size = tcp_data_len - tcp_send_offset;
2174 }
2175
2176 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2177
2178 /* add 4 TCP pseudoheader fields */
2179 /* copy IP source and destination fields */
2180 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2181
2182 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2183
2184 if (tcp_send_offset)
2185 {
2186 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2187 }
2188
2189 /* keep PUSH and FIN flags only for the last frame */
2190 if (!is_last_frame)
2191 {
2192 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2193 }
6cadb320 2194
718da2b9
FB		 2195 /* recalculate TCP checksum */
2196 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2197 p_tcpip_hdr->zeros = 0;
2198 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2199 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2200
2201 p_tcp_hdr->th_sum = 0;
2202
2203 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2204 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2205
2206 p_tcp_hdr->th_sum = tcp_checksum;
2207
2208 /* restore IP header */
2209 memcpy(eth_payload_data, saved_ip_header, hlen);
2210
2211 /* set IP data length and recalculate IP checksum */
2212 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2213
2214 /* increment IP id for subsequent frames */
2215 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2216
2217 ip->ip_sum = 0;
2218 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2219 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2220
2221 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2222 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2223 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2224
2225 /* add transferred count to TCP sequence number */
2226 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2227 ++send_count;
2228 }
2229
2230 /* Stop sending this frame */
2231 saved_size = 0;
2232 }
2233 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2234 {
2235 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2236
2237 /* maximum IP header length is 60 bytes */
2238 uint8_t saved_ip_header[60];
2239 memcpy(saved_ip_header, eth_payload_data, hlen);
2240
2241 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2242 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2243
2244 /* add 4 TCP pseudoheader fields */
2245 /* copy IP source and destination fields */
718da2b9 2246 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2247
718da2b9 2248 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320
FB		 2249 {
2250 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2251
718da2b9
FB		 2252 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2253 p_tcpip_hdr->zeros = 0;
2254 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2255 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2256
718da2b9 2257 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2258
2259 p_tcp_hdr->th_sum = 0;
2260
718da2b9 2261 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2262 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2263
2264 p_tcp_hdr->th_sum = tcp_checksum;
2265 }
718da2b9 2266 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320
FB		 2267 {
2268 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2269
718da2b9
FB		 2270 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2271 p_udpip_hdr->zeros = 0;
2272 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2273 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2274
718da2b9 2275 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2276
6cadb320
FB		 2277 p_udp_hdr->uh_sum = 0;
2278
718da2b9 2279 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2280 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2281
6cadb320
FB		 2282 p_udp_hdr->uh_sum = udp_checksum;
2283 }
2284
2285 /* restore IP header */
718da2b9 2286 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2287 }
2288 }
2289 }
2290
2291 /* update tally counter */
2292 ++s->tally_counters.TxOk;
2293
2294 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2295
718da2b9 2296 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
6cadb320
FB		 2297
2298 /* restore card space if there was no recursion and reset offset */
2299 if (!s->cplus_txbuffer)
2300 {
2301 s->cplus_txbuffer = saved_buffer;
2302 s->cplus_txbuffer_len = saved_buffer_len;
2303 s->cplus_txbuffer_offset = 0;
2304 }
2305 else
2306 {
2307 free(saved_buffer);
2308 }
a41b2ff2
PB		 2309 }
2310 else
2311 {
6cadb320 2312 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
a41b2ff2
PB		 2313 }
2314
a41b2ff2
PB		 2315 return 1;
2316}
2317
2318static void rtl8139_cplus_transmit(RTL8139State *s)
2319{
2320 int txcount = 0;
2321
2322 while (rtl8139_cplus_transmit_one(s))
2323 {
2324 ++txcount;
2325 }
2326
2327 /* Mark transfer completed */
2328 if (!txcount)
2329 {
6cadb320
FB		 2330 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2331 s->currCPlusTxDesc));
a41b2ff2
PB		 2332 }
2333 else
2334 {
2335 /* update interrupt status */
2336 s->IntrStatus |= TxOK;
2337 rtl8139_update_irq(s);
2338 }
2339}
2340
2341static void rtl8139_transmit(RTL8139State *s)
2342{
2343 int descriptor = s->currTxDesc, txcount = 0;
2344
2345 /*while*/
2346 if (rtl8139_transmit_one(s, descriptor))
2347 {
2348 ++s->currTxDesc;
2349 s->currTxDesc %= 4;
2350 ++txcount;
2351 }
2352
2353 /* Mark transfer completed */
2354 if (!txcount)
2355 {
6cadb320 2356 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
a41b2ff2
PB		 2357 }
2358}
2359
2360static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2361{
2362
2363 int descriptor = txRegOffset/4;
6cadb320
FB		 2364
2365 /* handle C+ transmit mode register configuration */
2366
2367 if (rtl8139_cp_transmitter_enabled(s))
2368 {
2369 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2370
2371 /* handle Dump Tally Counters command */
2372 s->TxStatus[descriptor] = val;
2373
2374 if (descriptor == 0 && (val & 0x8))
2375 {
2376 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2377
2378 /* dump tally counters to specified memory location */
2379 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2380
2381 /* mark dump completed */
2382 s->TxStatus[0] &= ~0x8;
2383 }
2384
2385 return;
2386 }
2387
2388 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
a41b2ff2
PB		 2389
2390 /* mask only reserved bits */
2391 val &= ~0xff00c000; /* these bits are reset on write */
2392 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2393
2394 s->TxStatus[descriptor] = val;
2395
2396 /* attempt to start transmission */
2397 rtl8139_transmit(s);
2398}
2399
2400static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2401{
2402 uint32_t ret = s->TxStatus[txRegOffset/4];
2403
6cadb320 2404 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
a41b2ff2
PB		 2405
2406 return ret;
2407}
2408
2409static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2410{
2411 uint16_t ret = 0;
2412
2413 /* Simulate TSAD, it is read only anyway */
2414
2415 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2416 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2417 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2418 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2419
2420 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2421 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2422 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2423 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2424
2425 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2426 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2427 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2428 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2429
2430 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2431 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2432 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2433 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2434
2435
6cadb320 2436 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
a41b2ff2
PB		 2437
2438 return ret;
2439}
2440
2441static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2442{
2443 uint16_t ret = s->CSCR;
2444
6cadb320 2445 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
a41b2ff2
PB		 2446
2447 return ret;
2448}
2449
2450static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2451{
6cadb320 2452 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
a41b2ff2 2453
290a0933 2454 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2455}
2456
2457static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2458{
290a0933 2459 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2460
6cadb320 2461 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
a41b2ff2
PB		 2462
2463 return ret;
2464}
2465
2466static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2467{
6cadb320 2468 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
a41b2ff2
PB		 2469
2470 /* this value is off by 16 */
2471 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2472
6cadb320
FB		 2473 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2474 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 2475}
2476
2477static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2478{
2479 /* this value is off by 16 */
2480 uint32_t ret = s->RxBufPtr - 0x10;
2481
6cadb320
FB		 2482 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2483
2484 return ret;
2485}
2486
2487static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2488{
2489 /* this value is NOT off by 16 */
2490 uint32_t ret = s->RxBufAddr;
2491
2492 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
a41b2ff2
PB		 2493
2494 return ret;
2495}
2496
2497static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2498{
6cadb320 2499 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
a41b2ff2
PB		 2500
2501 s->RxBuf = val;
2502
2503 /* may need to reset rxring here */
2504}
2505
2506static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2507{
2508 uint32_t ret = s->RxBuf;
2509
6cadb320 2510 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
a41b2ff2
PB		 2511
2512 return ret;
2513}
2514
2515static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2516{
6cadb320 2517 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2518
2519 /* mask unwriteable bits */
2520 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2521
2522 s->IntrMask = val;
2523
2524 rtl8139_update_irq(s);
2525}
2526
2527static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2528{
2529 uint32_t ret = s->IntrMask;
2530
6cadb320 2531 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2532
2533 return ret;
2534}
2535
2536static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2537{
6cadb320 2538 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2539
2540#if 0
2541
2542 /* writing to ISR has no effect */
2543
2544 return;
2545
2546#else
2547 uint16_t newStatus = s->IntrStatus & ~val;
2548
2549 /* mask unwriteable bits */
2550 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2551
2552 /* writing 1 to interrupt status register bit clears it */
2553 s->IntrStatus = 0;
2554 rtl8139_update_irq(s);
2555
2556 s->IntrStatus = newStatus;
2557 rtl8139_update_irq(s);
2558#endif
2559}
2560
2561static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2562{
2563 uint32_t ret = s->IntrStatus;
2564
6cadb320 2565 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2566
2567#if 0
2568
2569 /* reading ISR clears all interrupts */
2570 s->IntrStatus = 0;
2571
2572 rtl8139_update_irq(s);
2573
2574#endif
2575
2576 return ret;
2577}
2578
2579static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2580{
6cadb320 2581 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2582
2583 /* mask unwriteable bits */
2584 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2585
2586 s->MultiIntr = val;
2587}
2588
2589static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2590{
2591 uint32_t ret = s->MultiIntr;
2592
6cadb320 2593 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2594
2595 return ret;
2596}
2597
2598static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2599{
2600 RTL8139State *s = opaque;
2601
2602 addr &= 0xff;
2603
2604 switch (addr)
2605 {
2606 case MAC0 ... MAC0+5:
2607 s->phys[addr - MAC0] = val;
2608 break;
2609 case MAC0+6 ... MAC0+7:
2610 /* reserved */
2611 break;
2612 case MAR0 ... MAR0+7:
2613 s->mult[addr - MAR0] = val;
2614 break;
2615 case ChipCmd:
2616 rtl8139_ChipCmd_write(s, val);
2617 break;
2618 case Cfg9346:
2619 rtl8139_Cfg9346_write(s, val);
2620 break;
2621 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2622 rtl8139_TxConfig_writeb(s, val);
2623 break;
2624 case Config0:
2625 rtl8139_Config0_write(s, val);
2626 break;
2627 case Config1:
2628 rtl8139_Config1_write(s, val);
2629 break;
2630 case Config3:
2631 rtl8139_Config3_write(s, val);
2632 break;
2633 case Config4:
2634 rtl8139_Config4_write(s, val);
2635 break;
2636 case Config5:
2637 rtl8139_Config5_write(s, val);
2638 break;
2639 case MediaStatus:
2640 /* ignore */
6cadb320 2641 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
a41b2ff2
PB		 2642 break;
2643
2644 case HltClk:
6cadb320 2645 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
a41b2ff2
PB		 2646 if (val == 'R')
2647 {
2648 s->clock_enabled = 1;
2649 }
2650 else if (val == 'H')
2651 {
2652 s->clock_enabled = 0;
2653 }
2654 break;
2655
2656 case TxThresh:
6cadb320 2657 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2658 s->TxThresh = val;
2659 break;
2660
2661 case TxPoll:
6cadb320 2662 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2663 if (val & (1 << 7))
2664 {
6cadb320 2665 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
a41b2ff2
PB		 2666 //rtl8139_cplus_transmit(s);
2667 }
2668 if (val & (1 << 6))
2669 {
6cadb320 2670 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
a41b2ff2
PB		 2671 rtl8139_cplus_transmit(s);
2672 }
2673
2674 break;
2675
2676 default:
6cadb320 2677 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
a41b2ff2
PB		 2678 break;
2679 }
2680}
2681
2682static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2683{
2684 RTL8139State *s = opaque;
2685
2686 addr &= 0xfe;
2687
2688 switch (addr)
2689 {
2690 case IntrMask:
2691 rtl8139_IntrMask_write(s, val);
2692 break;
2693
2694 case IntrStatus:
2695 rtl8139_IntrStatus_write(s, val);
2696 break;
2697
2698 case MultiIntr:
2699 rtl8139_MultiIntr_write(s, val);
2700 break;
2701
2702 case RxBufPtr:
2703 rtl8139_RxBufPtr_write(s, val);
2704 break;
2705
2706 case BasicModeCtrl:
2707 rtl8139_BasicModeCtrl_write(s, val);
2708 break;
2709 case BasicModeStatus:
2710 rtl8139_BasicModeStatus_write(s, val);
2711 break;
2712 case NWayAdvert:
6cadb320 2713 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2714 s->NWayAdvert = val;
2715 break;
2716 case NWayLPAR:
6cadb320 2717 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2718 break;
2719 case NWayExpansion:
6cadb320 2720 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2721 s->NWayExpansion = val;
2722 break;
2723
2724 case CpCmd:
2725 rtl8139_CpCmd_write(s, val);
2726 break;
2727
6cadb320
FB		 2728 case IntrMitigate:
2729 rtl8139_IntrMitigate_write(s, val);
2730 break;
2731
a41b2ff2 2732 default:
6cadb320 2733 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
a41b2ff2
PB		 2734
2735#ifdef TARGET_WORDS_BIGENDIAN
2736 rtl8139_io_writeb(opaque, addr, (val >> 8) & 0xff);
2737 rtl8139_io_writeb(opaque, addr + 1, val & 0xff);
2738#else
2739 rtl8139_io_writeb(opaque, addr, val & 0xff);
2740 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2741#endif
2742 break;
2743 }
2744}
2745
2746static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2747{
2748 RTL8139State *s = opaque;
2749
2750 addr &= 0xfc;
2751
2752 switch (addr)
2753 {
2754 case RxMissed:
6cadb320 2755 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
a41b2ff2
PB		 2756 s->RxMissed = 0;
2757 break;
2758
2759 case TxConfig:
2760 rtl8139_TxConfig_write(s, val);
2761 break;
2762
2763 case RxConfig:
2764 rtl8139_RxConfig_write(s, val);
2765 break;
2766
2767 case TxStatus0 ... TxStatus0+4*4-1:
2768 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2769 break;
2770
2771 case TxAddr0 ... TxAddr0+4*4-1:
2772 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2773 break;
2774
2775 case RxBuf:
2776 rtl8139_RxBuf_write(s, val);
2777 break;
2778
2779 case RxRingAddrLO:
6cadb320 2780 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
a41b2ff2
PB		 2781 s->RxRingAddrLO = val;
2782 break;
2783
2784 case RxRingAddrHI:
6cadb320 2785 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
a41b2ff2
PB		 2786 s->RxRingAddrHI = val;
2787 break;
2788
6cadb320
FB		 2789 case Timer:
2790 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2791 s->TCTR = 0;
2792 s->TCTR_base = qemu_get_clock(vm_clock);
2793 break;
2794
2795 case FlashReg:
2796 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2797 s->TimerInt = val;
2798 break;
2799
a41b2ff2 2800 default:
6cadb320 2801 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
a41b2ff2
PB		 2802#ifdef TARGET_WORDS_BIGENDIAN
2803 rtl8139_io_writeb(opaque, addr, (val >> 24) & 0xff);
2804 rtl8139_io_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2805 rtl8139_io_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2806 rtl8139_io_writeb(opaque, addr + 3, val & 0xff);
2807#else
2808 rtl8139_io_writeb(opaque, addr, val & 0xff);
2809 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2810 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2811 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2812#endif
2813 break;
2814 }
2815}
2816
2817static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2818{
2819 RTL8139State *s = opaque;
2820 int ret;
2821
2822 addr &= 0xff;
2823
2824 switch (addr)
2825 {
2826 case MAC0 ... MAC0+5:
2827 ret = s->phys[addr - MAC0];
2828 break;
2829 case MAC0+6 ... MAC0+7:
2830 ret = 0;
2831 break;
2832 case MAR0 ... MAR0+7:
2833 ret = s->mult[addr - MAR0];
2834 break;
2835 case ChipCmd:
2836 ret = rtl8139_ChipCmd_read(s);
2837 break;
2838 case Cfg9346:
2839 ret = rtl8139_Cfg9346_read(s);
2840 break;
2841 case Config0:
2842 ret = rtl8139_Config0_read(s);
2843 break;
2844 case Config1:
2845 ret = rtl8139_Config1_read(s);
2846 break;
2847 case Config3:
2848 ret = rtl8139_Config3_read(s);
2849 break;
2850 case Config4:
2851 ret = rtl8139_Config4_read(s);
2852 break;
2853 case Config5:
2854 ret = rtl8139_Config5_read(s);
2855 break;
2856
2857 case MediaStatus:
2858 ret = 0xd0;
6cadb320 2859 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
a41b2ff2
PB		 2860 break;
2861
2862 case HltClk:
2863 ret = s->clock_enabled;
6cadb320 2864 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
a41b2ff2
PB		 2865 break;
2866
2867 case PCIRevisionID:
6cadb320
FB		 2868 ret = RTL8139_PCI_REVID;
2869 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
a41b2ff2
PB		 2870 break;
2871
2872 case TxThresh:
2873 ret = s->TxThresh;
6cadb320 2874 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2875 break;
2876
2877 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2878 ret = s->TxConfig >> 24;
6cadb320 2879 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2880 break;
2881
2882 default:
6cadb320 2883 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
a41b2ff2
PB		 2884 ret = 0;
2885 break;
2886 }
2887
2888 return ret;
2889}
2890
2891static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2892{
2893 RTL8139State *s = opaque;
2894 uint32_t ret;
2895
2896 addr &= 0xfe; /* mask lower bit */
2897
2898 switch (addr)
2899 {
2900 case IntrMask:
2901 ret = rtl8139_IntrMask_read(s);
2902 break;
2903
2904 case IntrStatus:
2905 ret = rtl8139_IntrStatus_read(s);
2906 break;
2907
2908 case MultiIntr:
2909 ret = rtl8139_MultiIntr_read(s);
2910 break;
2911
2912 case RxBufPtr:
2913 ret = rtl8139_RxBufPtr_read(s);
2914 break;
2915
6cadb320
FB		 2916 case RxBufAddr:
2917 ret = rtl8139_RxBufAddr_read(s);
2918 break;
2919
a41b2ff2
PB		 2920 case BasicModeCtrl:
2921 ret = rtl8139_BasicModeCtrl_read(s);
2922 break;
2923 case BasicModeStatus:
2924 ret = rtl8139_BasicModeStatus_read(s);
2925 break;
2926 case NWayAdvert:
2927 ret = s->NWayAdvert;
6cadb320 2928 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2929 break;
2930 case NWayLPAR:
2931 ret = s->NWayLPAR;
6cadb320 2932 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2933 break;
2934 case NWayExpansion:
2935 ret = s->NWayExpansion;
6cadb320 2936 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2937 break;
2938
2939 case CpCmd:
2940 ret = rtl8139_CpCmd_read(s);
2941 break;
2942
6cadb320
FB		 2943 case IntrMitigate:
2944 ret = rtl8139_IntrMitigate_read(s);
2945 break;
2946
a41b2ff2
PB		 2947 case TxSummary:
2948 ret = rtl8139_TSAD_read(s);
2949 break;
2950
2951 case CSCR:
2952 ret = rtl8139_CSCR_read(s);
2953 break;
2954
2955 default:
6cadb320 2956 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
a41b2ff2
PB		 2957
2958#ifdef TARGET_WORDS_BIGENDIAN
2959 ret = rtl8139_io_readb(opaque, addr) << 8;
2960 ret |= rtl8139_io_readb(opaque, addr + 1);
2961#else
2962 ret = rtl8139_io_readb(opaque, addr);
2963 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2964#endif
2965
6cadb320 2966 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
a41b2ff2
PB		 2967 break;
2968 }
2969
2970 return ret;
2971}
2972
2973static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2974{
2975 RTL8139State *s = opaque;
2976 uint32_t ret;
2977
2978 addr &= 0xfc; /* also mask low 2 bits */
2979
2980 switch (addr)
2981 {
2982 case RxMissed:
2983 ret = s->RxMissed;
2984
6cadb320 2985 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
a41b2ff2
PB		 2986 break;
2987
2988 case TxConfig:
2989 ret = rtl8139_TxConfig_read(s);
2990 break;
2991
2992 case RxConfig:
2993 ret = rtl8139_RxConfig_read(s);
2994 break;
2995
2996 case TxStatus0 ... TxStatus0+4*4-1:
2997 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
2998 break;
2999
3000 case TxAddr0 ... TxAddr0+4*4-1:
3001 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3002 break;
3003
3004 case RxBuf:
3005 ret = rtl8139_RxBuf_read(s);
3006 break;
3007
3008 case RxRingAddrLO:
3009 ret = s->RxRingAddrLO;
6cadb320 3010 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
a41b2ff2
PB		 3011 break;
3012
3013 case RxRingAddrHI:
3014 ret = s->RxRingAddrHI;
6cadb320
FB		 3015 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3016 break;
3017
3018 case Timer:
3019 ret = s->TCTR;
3020 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3021 break;
3022
3023 case FlashReg:
3024 ret = s->TimerInt;
3025 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
a41b2ff2
PB		 3026 break;
3027
3028 default:
6cadb320 3029 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
a41b2ff2
PB		 3030
3031#ifdef TARGET_WORDS_BIGENDIAN
3032 ret = rtl8139_io_readb(opaque, addr) << 24;
3033 ret |= rtl8139_io_readb(opaque, addr + 1) << 16;
3034 ret |= rtl8139_io_readb(opaque, addr + 2) << 8;
3035 ret |= rtl8139_io_readb(opaque, addr + 3);
3036#else
3037 ret = rtl8139_io_readb(opaque, addr);
3038 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3039 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3040 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3041#endif
3042
6cadb320 3043 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
a41b2ff2
PB		 3044 break;
3045 }
3046
3047 return ret;
3048}
3049
3050/* */
3051
3052static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3053{
3054 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3055}
3056
3057static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3058{
3059 rtl8139_io_writew(opaque, addr & 0xFF, val);
3060}
3061
3062static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3063{
3064 rtl8139_io_writel(opaque, addr & 0xFF, val);
3065}
3066
3067static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3068{
3069 return rtl8139_io_readb(opaque, addr & 0xFF);
3070}
3071
3072static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3073{
3074 return rtl8139_io_readw(opaque, addr & 0xFF);
3075}
3076
3077static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3078{
3079 return rtl8139_io_readl(opaque, addr & 0xFF);
3080}
3081
3082/* */
3083
3084static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3085{
3086 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3087}
3088
3089static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3090{
3091 rtl8139_io_writew(opaque, addr & 0xFF, val);
3092}
3093
3094static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3095{
3096 rtl8139_io_writel(opaque, addr & 0xFF, val);
3097}
3098
3099static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3100{
3101 return rtl8139_io_readb(opaque, addr & 0xFF);
3102}
3103
3104static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3105{
3106 return rtl8139_io_readw(opaque, addr & 0xFF);
3107}
3108
3109static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3110{
3111 return rtl8139_io_readl(opaque, addr & 0xFF);
3112}
3113
3114/* */
3115
3116static void rtl8139_save(QEMUFile* f,void* opaque)
3117{
3118 RTL8139State* s=(RTL8139State*)opaque;
3119 int i;
3120
1941d19c
FB		 3121 pci_device_save(s->pci_dev, f);
3122
a41b2ff2
PB		 3123 qemu_put_buffer(f, s->phys, 6);
3124 qemu_put_buffer(f, s->mult, 8);
3125
3126 for (i=0; i<4; ++i)
3127 {
3128 qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3129 }
3130 for (i=0; i<4; ++i)
3131 {
3132 qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3133 }
3134
3135 qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
3136 qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3137 qemu_put_be32s(f, &s->RxBufPtr);
3138 qemu_put_be32s(f, &s->RxBufAddr);
3139
3140 qemu_put_be16s(f, &s->IntrStatus);
3141 qemu_put_be16s(f, &s->IntrMask);
3142
3143 qemu_put_be32s(f, &s->TxConfig);
3144 qemu_put_be32s(f, &s->RxConfig);
3145 qemu_put_be32s(f, &s->RxMissed);
3146 qemu_put_be16s(f, &s->CSCR);
3147
3148 qemu_put_8s(f, &s->Cfg9346);
3149 qemu_put_8s(f, &s->Config0);
3150 qemu_put_8s(f, &s->Config1);
3151 qemu_put_8s(f, &s->Config3);
3152 qemu_put_8s(f, &s->Config4);
3153 qemu_put_8s(f, &s->Config5);
3154
3155 qemu_put_8s(f, &s->clock_enabled);
3156 qemu_put_8s(f, &s->bChipCmdState);
3157
3158 qemu_put_be16s(f, &s->MultiIntr);
3159
3160 qemu_put_be16s(f, &s->BasicModeCtrl);
3161 qemu_put_be16s(f, &s->BasicModeStatus);
3162 qemu_put_be16s(f, &s->NWayAdvert);
3163 qemu_put_be16s(f, &s->NWayLPAR);
3164 qemu_put_be16s(f, &s->NWayExpansion);
3165
3166 qemu_put_be16s(f, &s->CpCmd);
3167 qemu_put_8s(f, &s->TxThresh);
3168
80a34d67
PB		 3169 i = 0;
3170 qemu_put_be32s(f, &i); /* unused. */
a41b2ff2
PB		 3171 qemu_put_buffer(f, s->macaddr, 6);
3172 qemu_put_be32s(f, &s->rtl8139_mmio_io_addr);
3173
3174 qemu_put_be32s(f, &s->currTxDesc);
3175 qemu_put_be32s(f, &s->currCPlusRxDesc);
3176 qemu_put_be32s(f, &s->currCPlusTxDesc);
3177 qemu_put_be32s(f, &s->RxRingAddrLO);
3178 qemu_put_be32s(f, &s->RxRingAddrHI);
3179
3180 for (i=0; i<EEPROM_9346_SIZE; ++i)
3181 {
3182 qemu_put_be16s(f, &s->eeprom.contents[i]);
3183 }
3184 qemu_put_be32s(f, &s->eeprom.mode);
3185 qemu_put_be32s(f, &s->eeprom.tick);
3186 qemu_put_8s(f, &s->eeprom.address);
3187 qemu_put_be16s(f, &s->eeprom.input);
3188 qemu_put_be16s(f, &s->eeprom.output);
3189
3190 qemu_put_8s(f, &s->eeprom.eecs);
3191 qemu_put_8s(f, &s->eeprom.eesk);
3192 qemu_put_8s(f, &s->eeprom.eedi);
3193 qemu_put_8s(f, &s->eeprom.eedo);
6cadb320
FB		 3194
3195 qemu_put_be32s(f, &s->TCTR);
3196 qemu_put_be32s(f, &s->TimerInt);
3197 qemu_put_be64s(f, &s->TCTR_base);
3198
3199 RTL8139TallyCounters_save(f, &s->tally_counters);
a41b2ff2
PB		 3200}
3201
3202static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
3203{
3204 RTL8139State* s=(RTL8139State*)opaque;
1941d19c 3205 int i, ret;
a41b2ff2 3206
6cadb320 3207 /* just 2 versions for now */
1941d19c 3208 if (version_id > 3)
a41b2ff2
PB		 3209 return -EINVAL;
3210
1941d19c
FB		 3211 if (version_id >= 3) {
3212 ret = pci_device_load(s->pci_dev, f);
3213 if (ret < 0)
3214 return ret;
3215 }
3216
6cadb320 3217 /* saved since version 1 */
a41b2ff2
PB		 3218 qemu_get_buffer(f, s->phys, 6);
3219 qemu_get_buffer(f, s->mult, 8);
3220
3221 for (i=0; i<4; ++i)
3222 {
3223 qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3224 }
3225 for (i=0; i<4; ++i)
3226 {
3227 qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3228 }
3229
3230 qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
3231 qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3232 qemu_get_be32s(f, &s->RxBufPtr);
3233 qemu_get_be32s(f, &s->RxBufAddr);
3234
3235 qemu_get_be16s(f, &s->IntrStatus);
3236 qemu_get_be16s(f, &s->IntrMask);
3237
3238 qemu_get_be32s(f, &s->TxConfig);
3239 qemu_get_be32s(f, &s->RxConfig);
3240 qemu_get_be32s(f, &s->RxMissed);
3241 qemu_get_be16s(f, &s->CSCR);
3242
3243 qemu_get_8s(f, &s->Cfg9346);
3244 qemu_get_8s(f, &s->Config0);
3245 qemu_get_8s(f, &s->Config1);
3246 qemu_get_8s(f, &s->Config3);
3247 qemu_get_8s(f, &s->Config4);
3248 qemu_get_8s(f, &s->Config5);
3249
3250 qemu_get_8s(f, &s->clock_enabled);
3251 qemu_get_8s(f, &s->bChipCmdState);
3252
3253 qemu_get_be16s(f, &s->MultiIntr);
3254
3255 qemu_get_be16s(f, &s->BasicModeCtrl);
3256 qemu_get_be16s(f, &s->BasicModeStatus);
3257 qemu_get_be16s(f, &s->NWayAdvert);
3258 qemu_get_be16s(f, &s->NWayLPAR);
3259 qemu_get_be16s(f, &s->NWayExpansion);
3260
3261 qemu_get_be16s(f, &s->CpCmd);
3262 qemu_get_8s(f, &s->TxThresh);
3263
80a34d67 3264 qemu_get_be32s(f, &i); /* unused. */
a41b2ff2
PB		 3265 qemu_get_buffer(f, s->macaddr, 6);
3266 qemu_get_be32s(f, &s->rtl8139_mmio_io_addr);
3267
3268 qemu_get_be32s(f, &s->currTxDesc);
3269 qemu_get_be32s(f, &s->currCPlusRxDesc);
3270 qemu_get_be32s(f, &s->currCPlusTxDesc);
3271 qemu_get_be32s(f, &s->RxRingAddrLO);
3272 qemu_get_be32s(f, &s->RxRingAddrHI);
3273
3274 for (i=0; i<EEPROM_9346_SIZE; ++i)
3275 {
3276 qemu_get_be16s(f, &s->eeprom.contents[i]);
3277 }
3278 qemu_get_be32s(f, &s->eeprom.mode);
3279 qemu_get_be32s(f, &s->eeprom.tick);
3280 qemu_get_8s(f, &s->eeprom.address);
3281 qemu_get_be16s(f, &s->eeprom.input);
3282 qemu_get_be16s(f, &s->eeprom.output);
3283
3284 qemu_get_8s(f, &s->eeprom.eecs);
3285 qemu_get_8s(f, &s->eeprom.eesk);
3286 qemu_get_8s(f, &s->eeprom.eedi);
3287 qemu_get_8s(f, &s->eeprom.eedo);
3288
6cadb320
FB		 3289 /* saved since version 2 */
3290 if (version_id >= 2)
3291 {
3292 qemu_get_be32s(f, &s->TCTR);
3293 qemu_get_be32s(f, &s->TimerInt);
3294 qemu_get_be64s(f, &s->TCTR_base);
3295
3296 RTL8139TallyCounters_load(f, &s->tally_counters);
3297 }
3298 else
3299 {
3300 /* not saved, use default */
3301 s->TCTR = 0;
3302 s->TimerInt = 0;
3303 s->TCTR_base = 0;
3304
3305 RTL8139TallyCounters_clear(&s->tally_counters);
3306 }
3307
a41b2ff2
PB		 3308 return 0;
3309}
3310
3311/***********************************************************/
3312/* PCI RTL8139 definitions */
3313
3314typedef struct PCIRTL8139State {
3315 PCIDevice dev;
3316 RTL8139State rtl8139;
3317} PCIRTL8139State;
3318
3319static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3320 uint32_t addr, uint32_t size, int type)
3321{
3322 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3323 RTL8139State *s = &d->rtl8139;
3324
3325 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3326}
3327
3328static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3329 uint32_t addr, uint32_t size, int type)
3330{
3331 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3332 RTL8139State *s = &d->rtl8139;
3333
3334 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3335 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3336
3337 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3338 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3339
3340 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3341 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3342}
3343
3344static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
3345 rtl8139_mmio_readb,
3346 rtl8139_mmio_readw,
3347 rtl8139_mmio_readl,
3348};
3349
3350static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
3351 rtl8139_mmio_writeb,
3352 rtl8139_mmio_writew,
3353 rtl8139_mmio_writel,
3354};
3355
6cadb320
FB		 3356static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3357{
3358 int64_t next_time = current_time +
3359 muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
3360 if (next_time <= current_time)
3361 next_time = current_time + 1;
3362 return next_time;
3363}
3364
3365#if RTL8139_ONBOARD_TIMER
3366static void rtl8139_timer(void *opaque)
3367{
3368 RTL8139State *s = opaque;
3369
3370 int is_timeout = 0;
3371
3372 int64_t curr_time;
3373 uint32_t curr_tick;
3374
3375 if (!s->clock_enabled)
3376 {
3377 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3378 return;
3379 }
3380
3381 curr_time = qemu_get_clock(vm_clock);
3382
3383 curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
3384
3385 if (s->TimerInt && curr_tick >= s->TimerInt)
3386 {
3387 if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3388 {
3389 is_timeout = 1;
3390 }
3391 }
3392
3393 s->TCTR = curr_tick;
3394
3395// DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3396
3397 if (is_timeout)
3398 {
3399 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3400 s->IntrStatus |= PCSTimeout;
3401 rtl8139_update_irq(s);
3402 }
3403
3404 qemu_mod_timer(s->timer,
3405 rtl8139_get_next_tctr_time(s,curr_time));
3406}
3407#endif /* RTL8139_ONBOARD_TIMER */
3408
abcebc7e 3409void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
a41b2ff2
PB		 3410{
3411 PCIRTL8139State *d;
3412 RTL8139State *s;
3413 uint8_t *pci_conf;
3414
3415 d = (PCIRTL8139State *)pci_register_device(bus,
3416 "RTL8139", sizeof(PCIRTL8139State),
abcebc7e 3417 devfn,
a41b2ff2
PB		 3418 NULL, NULL);
3419 pci_conf = d->dev.config;
3420 pci_conf[0x00] = 0xec; /* Realtek 8139 */
3421 pci_conf[0x01] = 0x10;
3422 pci_conf[0x02] = 0x39;
3423 pci_conf[0x03] = 0x81;
3424 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
6cadb320 3425 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
a41b2ff2
PB		 3426 pci_conf[0x0a] = 0x00; /* ethernet network controller */
3427 pci_conf[0x0b] = 0x02;
3428 pci_conf[0x0e] = 0x00; /* header_type */
3429 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3430 pci_conf[0x34] = 0xdc;
3431
3432 s = &d->rtl8139;
3433
3434 /* I/O handler for memory-mapped I/O */
3435 s->rtl8139_mmio_io_addr =
3436 cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
3437
3438 pci_register_io_region(&d->dev, 0, 0x100,
3439 PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3440
3441 pci_register_io_region(&d->dev, 1, 0x100,
3442 PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
3443
a41b2ff2
PB		 3444 s->pci_dev = (PCIDevice *)d;
3445 memcpy(s->macaddr, nd->macaddr, 6);
3446 rtl8139_reset(s);
3447 s->vc = qemu_new_vlan_client(nd->vlan, rtl8139_receive,
3448 rtl8139_can_receive, s);
3449
3450 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
3451 "rtl8139 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
3452 s->macaddr[0],
3453 s->macaddr[1],
3454 s->macaddr[2],
3455 s->macaddr[3],
3456 s->macaddr[4],
3457 s->macaddr[5]);
6cadb320
FB		 3458
3459 s->cplus_txbuffer = NULL;
3460 s->cplus_txbuffer_len = 0;
3461 s->cplus_txbuffer_offset = 0;
a41b2ff2
PB		 3462
3463 /* XXX: instance number ? */
1941d19c 3464 register_savevm("rtl8139", 0, 3, rtl8139_save, rtl8139_load, s);
6cadb320
FB		 3465
3466#if RTL8139_ONBOARD_TIMER
3467 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3468
3469 qemu_mod_timer(s->timer,
3470 rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3471#endif /* RTL8139_ONBOARD_TIMER */
a41b2ff2 3472}
6cadb320 3473
Qemu copy for testing