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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f
BP		 51/* For crc32 */
52#include <zlib.h>
53
87ecb68b
PB		 54#include "hw.h"
55#include "pci.h"
3ada003a 56#include "dma.h"
87ecb68b
PB		 57#include "qemu-timer.h"
58#include "net.h"
254111ec 59#include "loader.h"
1ca4d09a 60#include "sysemu.h"
bf6b87a8 61#include "iov.h"
a41b2ff2 62
a41b2ff2
PB		 63/* debug RTL8139 card */
64//#define DEBUG_RTL8139 1
65
6cadb320
FB		 66#define PCI_FREQUENCY 33000000L
67
a41b2ff2
PB		 68#define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71/* arg % size for size which is a power of 2 */
72#define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
18dabfd1
BP		 75#define ETHER_ADDR_LEN 6
76#define ETHER_TYPE_LEN 2
77#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
78#define ETH_P_IP 0x0800 /* Internet Protocol packet */
79#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
80#define ETH_MTU 1500
81
82#define VLAN_TCI_LEN 2
83#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
6cadb320 85#if defined (DEBUG_RTL8139)
7cdeb319
BP		 86# define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 88#else
c6a0487b 89static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
ec48c774
BP		 90{
91 return 0;
92}
6cadb320
FB		 93#endif
94
a41b2ff2
PB		 95/* Symbolic offsets to registers. */
96enum RTL8139_registers {
97 MAC0 = 0, /* Ethernet hardware address. */
98 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 99 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
100 /* Dump Tally Conter control register(64bit). C+ mode only */
101 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 102 RxBuf = 0x30,
103 ChipCmd = 0x37,
104 RxBufPtr = 0x38,
105 RxBufAddr = 0x3A,
106 IntrMask = 0x3C,
107 IntrStatus = 0x3E,
108 TxConfig = 0x40,
109 RxConfig = 0x44,
110 Timer = 0x48, /* A general-purpose counter. */
111 RxMissed = 0x4C, /* 24 bits valid, write clears. */
112 Cfg9346 = 0x50,
113 Config0 = 0x51,
114 Config1 = 0x52,
115 FlashReg = 0x54,
116 MediaStatus = 0x58,
117 Config3 = 0x59,
118 Config4 = 0x5A, /* absent on RTL-8139A */
119 HltClk = 0x5B,
120 MultiIntr = 0x5C,
121 PCIRevisionID = 0x5E,
122 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
123 BasicModeCtrl = 0x62,
124 BasicModeStatus = 0x64,
125 NWayAdvert = 0x66,
126 NWayLPAR = 0x68,
127 NWayExpansion = 0x6A,
128 /* Undocumented registers, but required for proper operation. */
129 FIFOTMS = 0x70, /* FIFO Control and test. */
130 CSCR = 0x74, /* Chip Status and Configuration Register. */
131 PARA78 = 0x78,
132 PARA7c = 0x7c, /* Magic transceiver parameter register. */
133 Config5 = 0xD8, /* absent on RTL-8139A */
134 /* C+ mode */
135 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
136 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
137 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
138 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
139 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
140 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
141 TxThresh = 0xEC, /* Early Tx threshold */
142};
143
144enum ClearBitMasks {
145 MultiIntrClear = 0xF000,
146 ChipCmdClear = 0xE2,
147 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
148};
149
150enum ChipCmdBits {
151 CmdReset = 0x10,
152 CmdRxEnb = 0x08,
153 CmdTxEnb = 0x04,
154 RxBufEmpty = 0x01,
155};
156
157/* C+ mode */
158enum CplusCmdBits {
6cadb320
FB		 159 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
160 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
161 CPlusRxEnb = 0x0002,
162 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 163};
164
165/* Interrupt register bits, using my own meaningful names. */
166enum IntrStatusBits {
167 PCIErr = 0x8000,
168 PCSTimeout = 0x4000,
169 RxFIFOOver = 0x40,
170 RxUnderrun = 0x20,
171 RxOverflow = 0x10,
172 TxErr = 0x08,
173 TxOK = 0x04,
174 RxErr = 0x02,
175 RxOK = 0x01,
176
177 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
178};
179
180enum TxStatusBits {
181 TxHostOwns = 0x2000,
182 TxUnderrun = 0x4000,
183 TxStatOK = 0x8000,
184 TxOutOfWindow = 0x20000000,
185 TxAborted = 0x40000000,
186 TxCarrierLost = 0x80000000,
187};
188enum RxStatusBits {
189 RxMulticast = 0x8000,
190 RxPhysical = 0x4000,
191 RxBroadcast = 0x2000,
192 RxBadSymbol = 0x0020,
193 RxRunt = 0x0010,
194 RxTooLong = 0x0008,
195 RxCRCErr = 0x0004,
196 RxBadAlign = 0x0002,
197 RxStatusOK = 0x0001,
198};
199
200/* Bits in RxConfig. */
201enum rx_mode_bits {
202 AcceptErr = 0x20,
203 AcceptRunt = 0x10,
204 AcceptBroadcast = 0x08,
205 AcceptMulticast = 0x04,
206 AcceptMyPhys = 0x02,
207 AcceptAllPhys = 0x01,
208};
209
210/* Bits in TxConfig. */
211enum tx_config_bits {
212
213 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
214 TxIFGShift = 24,
215 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
216 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
217 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
218 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
219
220 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
221 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
222 TxClearAbt = (1 << 0), /* Clear abort (WO) */
223 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
224 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
225
226 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
227};
228
229
230/* Transmit Status of All Descriptors (TSAD) Register */
231enum TSAD_bits {
232 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
233 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
234 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
235 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
236 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
237 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
238 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
239 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
240 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
241 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
242 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
243 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
244 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
245 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
246 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
247 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
248};
249
250
251/* Bits in Config1 */
252enum Config1Bits {
253 Cfg1_PM_Enable = 0x01,
254 Cfg1_VPD_Enable = 0x02,
255 Cfg1_PIO = 0x04,
256 Cfg1_MMIO = 0x08,
257 LWAKE = 0x10, /* not on 8139, 8139A */
258 Cfg1_Driver_Load = 0x20,
259 Cfg1_LED0 = 0x40,
260 Cfg1_LED1 = 0x80,
261 SLEEP = (1 << 1), /* only on 8139, 8139A */
262 PWRDN = (1 << 0), /* only on 8139, 8139A */
263};
264
265/* Bits in Config3 */
266enum Config3Bits {
267 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
268 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
269 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
270 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
271 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
272 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
273 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
274 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
275};
276
277/* Bits in Config4 */
278enum Config4Bits {
279 LWPTN = (1 << 2), /* not on 8139, 8139A */
280};
281
282/* Bits in Config5 */
283enum Config5Bits {
284 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
285 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
286 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
287 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
288 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
289 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
290 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
291};
292
293enum RxConfigBits {
294 /* rx fifo threshold */
295 RxCfgFIFOShift = 13,
296 RxCfgFIFONone = (7 << RxCfgFIFOShift),
297
298 /* Max DMA burst */
299 RxCfgDMAShift = 8,
300 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
301
302 /* rx ring buffer length */
303 RxCfgRcv8K = 0,
304 RxCfgRcv16K = (1 << 11),
305 RxCfgRcv32K = (1 << 12),
306 RxCfgRcv64K = (1 << 11) | (1 << 12),
307
308 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
309 RxNoWrap = (1 << 7),
310};
311
312/* Twister tuning parameters from RealTek.
313 Completely undocumented, but required to tune bad links on some boards. */
314/*
315enum CSCRBits {
316 CSCR_LinkOKBit = 0x0400,
317 CSCR_LinkChangeBit = 0x0800,
318 CSCR_LinkStatusBits = 0x0f000,
319 CSCR_LinkDownOffCmd = 0x003c0,
320 CSCR_LinkDownCmd = 0x0f3c0,
321*/
322enum CSCRBits {
5fafdf24 323 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 324 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
325 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
326 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 327 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 328 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
329 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
330 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
331 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
332};
333
334enum Cfg9346Bits {
eb46c5ed
JW		 335 Cfg9346_Normal = 0x00,
336 Cfg9346_Autoload = 0x40,
337 Cfg9346_Programming = 0x80,
338 Cfg9346_ConfigWrite = 0xC0,
a41b2ff2
PB		 339};
340
341typedef enum {
342 CH_8139 = 0,
343 CH_8139_K,
344 CH_8139A,
345 CH_8139A_G,
346 CH_8139B,
347 CH_8130,
348 CH_8139C,
349 CH_8100,
350 CH_8100B_8139D,
351 CH_8101,
c227f099 352} chip_t;
a41b2ff2
PB		 353
354enum chip_flags {
355 HasHltClk = (1 << 0),
356 HasLWake = (1 << 1),
357};
358
359#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
360 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
361#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
362
6cadb320
FB		 363#define RTL8139_PCI_REVID_8139 0x10
364#define RTL8139_PCI_REVID_8139CPLUS 0x20
365
366#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
367
a41b2ff2
PB		 368/* Size is 64 * 16bit words */
369#define EEPROM_9346_ADDR_BITS 6
370#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
371#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
372
373enum Chip9346Operation
374{
375 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
376 Chip9346_op_read = 0x80, /* 10 AAAAAA */
377 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
378 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
379 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
380 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
381 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
382};
383
384enum Chip9346Mode
385{
386 Chip9346_none = 0,
387 Chip9346_enter_command_mode,
388 Chip9346_read_command,
389 Chip9346_data_read, /* from output register */
390 Chip9346_data_write, /* to input register, then to contents at specified address */
391 Chip9346_data_write_all, /* to input register, then filling contents */
392};
393
394typedef struct EEprom9346
395{
396 uint16_t contents[EEPROM_9346_SIZE];
397 int mode;
398 uint32_t tick;
399 uint8_t address;
400 uint16_t input;
401 uint16_t output;
402
403 uint8_t eecs;
404 uint8_t eesk;
405 uint8_t eedi;
406 uint8_t eedo;
407} EEprom9346;
408
6cadb320
FB		 409typedef struct RTL8139TallyCounters
410{
411 /* Tally counters */
412 uint64_t TxOk;
413 uint64_t RxOk;
414 uint64_t TxERR;
415 uint32_t RxERR;
416 uint16_t MissPkt;
417 uint16_t FAE;
418 uint32_t Tx1Col;
419 uint32_t TxMCol;
420 uint64_t RxOkPhy;
421 uint64_t RxOkBrd;
422 uint32_t RxOkMul;
423 uint16_t TxAbt;
424 uint16_t TxUndrn;
425} RTL8139TallyCounters;
426
427/* Clears all tally counters */
428static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
429
a41b2ff2 430typedef struct RTL8139State {
efd6dd45 431 PCIDevice dev;
a41b2ff2
PB		 432 uint8_t phys[8]; /* mac address */
433 uint8_t mult[8]; /* multicast mask array */
434
6cadb320 435 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 436 uint32_t TxAddr[4]; /* TxAddr0 */
437 uint32_t RxBuf; /* Receive buffer */
438 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
439 uint32_t RxBufPtr;
440 uint32_t RxBufAddr;
441
442 uint16_t IntrStatus;
443 uint16_t IntrMask;
444
445 uint32_t TxConfig;
446 uint32_t RxConfig;
447 uint32_t RxMissed;
448
449 uint16_t CSCR;
450
451 uint8_t Cfg9346;
452 uint8_t Config0;
453 uint8_t Config1;
454 uint8_t Config3;
455 uint8_t Config4;
456 uint8_t Config5;
457
458 uint8_t clock_enabled;
459 uint8_t bChipCmdState;
460
461 uint16_t MultiIntr;
462
463 uint16_t BasicModeCtrl;
464 uint16_t BasicModeStatus;
465 uint16_t NWayAdvert;
466 uint16_t NWayLPAR;
467 uint16_t NWayExpansion;
468
469 uint16_t CpCmd;
470 uint8_t TxThresh;
471
1673ad51 472 NICState *nic;
254111ec 473 NICConf conf;
a41b2ff2
PB		 474
475 /* C ring mode */
476 uint32_t currTxDesc;
477
478 /* C+ mode */
2c3891ab
AL		 479 uint32_t cplus_enabled;
480
a41b2ff2
PB		 481 uint32_t currCPlusRxDesc;
482 uint32_t currCPlusTxDesc;
483
484 uint32_t RxRingAddrLO;
485 uint32_t RxRingAddrHI;
486
487 EEprom9346 eeprom;
6cadb320
FB		 488
489 uint32_t TCTR;
490 uint32_t TimerInt;
491 int64_t TCTR_base;
492
493 /* Tally counters */
494 RTL8139TallyCounters tally_counters;
495
496 /* Non-persistent data */
497 uint8_t *cplus_txbuffer;
498 int cplus_txbuffer_len;
499 int cplus_txbuffer_offset;
500
501 /* PCI interrupt timer */
502 QEMUTimer *timer;
05447803 503 int64_t TimerExpire;
6cadb320 504
bd80f3fc
AK		 505 MemoryRegion bar_io;
506 MemoryRegion bar_mem;
507
c574ba5a
AW		 508 /* Support migration to/from old versions */
509 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 510} RTL8139State;
511
3ada003a
EGM		 512/* Writes tally counters to memory via DMA */
513static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
514
05447803
FZ		 515static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
516
9596ebb7 517static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 518{
7cdeb319 519 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 520
521 switch (command & Chip9346_op_mask)
522 {
523 case Chip9346_op_read:
524 {
525 eeprom->address = command & EEPROM_9346_ADDR_MASK;
526 eeprom->output = eeprom->contents[eeprom->address];
527 eeprom->eedo = 0;
528 eeprom->tick = 0;
529 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 530 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
531 eeprom->address, eeprom->output);
a41b2ff2
PB		 532 }
533 break;
534
535 case Chip9346_op_write:
536 {
537 eeprom->address = command & EEPROM_9346_ADDR_MASK;
538 eeprom->input = 0;
539 eeprom->tick = 0;
540 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 541 DPRINTF("eeprom begin write to address 0x%02x\n",
542 eeprom->address);
a41b2ff2
PB		 543 }
544 break;
545 default:
546 eeprom->mode = Chip9346_none;
547 switch (command & Chip9346_op_ext_mask)
548 {
549 case Chip9346_op_write_enable:
7cdeb319 550 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 551 break;
552 case Chip9346_op_write_all:
7cdeb319 553 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 554 break;
555 case Chip9346_op_write_disable:
7cdeb319 556 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 557 break;
558 }
559 break;
560 }
561}
562
9596ebb7 563static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 564{
565 int bit = eeprom->eedi?1:0;
566
567 ++ eeprom->tick;
568
7cdeb319
BP		 569 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
570 eeprom->eedo);
a41b2ff2
PB		 571
572 switch (eeprom->mode)
573 {
574 case Chip9346_enter_command_mode:
575 if (bit)
576 {
577 eeprom->mode = Chip9346_read_command;
578 eeprom->tick = 0;
579 eeprom->input = 0;
7cdeb319 580 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 581 }
582 break;
583
584 case Chip9346_read_command:
585 eeprom->input = (eeprom->input << 1) | (bit & 1);
586 if (eeprom->tick == 8)
587 {
588 prom9346_decode_command(eeprom, eeprom->input & 0xff);
589 }
590 break;
591
592 case Chip9346_data_read:
593 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
594 eeprom->output <<= 1;
595 if (eeprom->tick == 16)
596 {
6cadb320
FB		 597#if 1
598 // the FreeBSD drivers (rl and re) don't explicitly toggle
599 // CS between reads (or does setting Cfg9346 to 0 count too?),
600 // so we need to enter wait-for-command state here
601 eeprom->mode = Chip9346_enter_command_mode;
602 eeprom->input = 0;
603 eeprom->tick = 0;
604
7cdeb319 605 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 606#else
607 // original behaviour
a41b2ff2
PB		 608 ++eeprom->address;
609 eeprom->address &= EEPROM_9346_ADDR_MASK;
610 eeprom->output = eeprom->contents[eeprom->address];
611 eeprom->tick = 0;
612
7cdeb319
BP		 613 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
614 eeprom->address, eeprom->output);
a41b2ff2
PB		 615#endif
616 }
617 break;
618
619 case Chip9346_data_write:
620 eeprom->input = (eeprom->input << 1) | (bit & 1);
621 if (eeprom->tick == 16)
622 {
7cdeb319
BP		 623 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
624 eeprom->address, eeprom->input);
6cadb320 625
a41b2ff2
PB		 626 eeprom->contents[eeprom->address] = eeprom->input;
627 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
628 eeprom->tick = 0;
629 eeprom->input = 0;
630 }
631 break;
632
633 case Chip9346_data_write_all:
634 eeprom->input = (eeprom->input << 1) | (bit & 1);
635 if (eeprom->tick == 16)
636 {
637 int i;
638 for (i = 0; i < EEPROM_9346_SIZE; i++)
639 {
640 eeprom->contents[i] = eeprom->input;
641 }
7cdeb319 642 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 643
a41b2ff2
PB		 644 eeprom->mode = Chip9346_enter_command_mode;
645 eeprom->tick = 0;
646 eeprom->input = 0;
647 }
648 break;
649
650 default:
651 break;
652 }
653}
654
9596ebb7 655static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 656{
657 EEprom9346 *eeprom = &s->eeprom;
658 if (!eeprom->eecs)
659 return 0;
660
661 return eeprom->eedo;
662}
663
9596ebb7
PB		 664/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
665static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 666{
667 EEprom9346 *eeprom = &s->eeprom;
668 uint8_t old_eecs = eeprom->eecs;
669 uint8_t old_eesk = eeprom->eesk;
670
671 eeprom->eecs = eecs;
672 eeprom->eesk = eesk;
673 eeprom->eedi = eedi;
674
7cdeb319
BP		 675 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
676 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 677
678 if (!old_eecs && eecs)
679 {
680 /* Synchronize start */
681 eeprom->tick = 0;
682 eeprom->input = 0;
683 eeprom->output = 0;
684 eeprom->mode = Chip9346_enter_command_mode;
685
7cdeb319 686 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 687 }
688
689 if (!eecs)
690 {
7cdeb319 691 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 692 return;
693 }
694
695 if (!old_eesk && eesk)
696 {
697 /* SK front rules */
698 prom9346_shift_clock(eeprom);
699 }
700}
701
702static void rtl8139_update_irq(RTL8139State *s)
703{
704 int isr;
705 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 706
7cdeb319
BP		 707 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
708 s->IntrMask);
6cadb320 709
efd6dd45 710 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 711}
712
a41b2ff2
PB		 713static int rtl8139_RxWrap(RTL8139State *s)
714{
715 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
716 return (s->RxConfig & (1 << 7));
717}
718
719static int rtl8139_receiver_enabled(RTL8139State *s)
720{
721 return s->bChipCmdState & CmdRxEnb;
722}
723
724static int rtl8139_transmitter_enabled(RTL8139State *s)
725{
726 return s->bChipCmdState & CmdTxEnb;
727}
728
729static int rtl8139_cp_receiver_enabled(RTL8139State *s)
730{
731 return s->CpCmd & CPlusRxEnb;
732}
733
734static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
735{
736 return s->CpCmd & CPlusTxEnb;
737}
738
739static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
740{
741 if (s->RxBufAddr + size > s->RxBufferSize)
742 {
743 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
744
745 /* write packet data */
ccf1d14a 746 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 747 {
7cdeb319 748 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 749
750 if (size > wrapped)
751 {
3ada003a
EGM		 752 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
753 buf, size-wrapped);
a41b2ff2
PB		 754 }
755
756 /* reset buffer pointer */
757 s->RxBufAddr = 0;
758
3ada003a
EGM		 759 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
760 buf + (size-wrapped), wrapped);
a41b2ff2
PB		 761
762 s->RxBufAddr = wrapped;
763
764 return;
765 }
766 }
767
768 /* non-wrapping path or overwrapping enabled */
3ada003a 769 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size);
a41b2ff2
PB		 770
771 s->RxBufAddr += size;
772}
773
774#define MIN_BUF_SIZE 60
3ada003a 775static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 776{
777#if TARGET_PHYS_ADDR_BITS > 32
c227f099 778 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 779#else
780 return low;
781#endif
782}
783
1673ad51 784static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 785{
1673ad51 786 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 787 int avail;
788
aa1f17c1 789 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 790 if (!s->clock_enabled)
791 return 1;
792 if (!rtl8139_receiver_enabled(s))
793 return 1;
794
795 if (rtl8139_cp_receiver_enabled(s)) {
796 /* ??? Flow control not implemented in c+ mode.
797 This is a hack to work around slirp deficiencies anyway. */
798 return 1;
799 } else {
800 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
801 s->RxBufferSize);
802 return (avail == 0 || avail >= 1514);
803 }
804}
805
1673ad51 806static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 807{
1673ad51 808 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
18dabfd1 809 /* size is the length of the buffer passed to the driver */
4f1c942b 810 int size = size_;
18dabfd1 811 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 812
813 uint32_t packet_header = 0;
814
18dabfd1 815 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 816 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 817 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
818
7cdeb319 819 DPRINTF(">>> received len=%d\n", size);
a41b2ff2
PB		 820
821 /* test if board clock is stopped */
822 if (!s->clock_enabled)
823 {
7cdeb319 824 DPRINTF("stopped ==========================\n");
4f1c942b 825 return -1;
a41b2ff2
PB		 826 }
827
828 /* first check if receiver is enabled */
829
830 if (!rtl8139_receiver_enabled(s))
831 {
7cdeb319 832 DPRINTF("receiver disabled ================\n");
4f1c942b 833 return -1;
a41b2ff2
PB		 834 }
835
836 /* XXX: check this */
837 if (s->RxConfig & AcceptAllPhys) {
838 /* promiscuous: receive all */
7cdeb319 839 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 840
841 } else {
842 if (!memcmp(buf, broadcast_macaddr, 6)) {
843 /* broadcast address */
844 if (!(s->RxConfig & AcceptBroadcast))
845 {
7cdeb319 846 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 847
848 /* update tally counter */
849 ++s->tally_counters.RxERR;
850
4f1c942b 851 return size;
a41b2ff2
PB		 852 }
853
854 packet_header |= RxBroadcast;
855
7cdeb319 856 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 857
858 /* update tally counter */
859 ++s->tally_counters.RxOkBrd;
860
a41b2ff2
PB		 861 } else if (buf[0] & 0x01) {
862 /* multicast */
863 if (!(s->RxConfig & AcceptMulticast))
864 {
7cdeb319 865 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 866
867 /* update tally counter */
868 ++s->tally_counters.RxERR;
869
4f1c942b 870 return size;
a41b2ff2
PB		 871 }
872
873 int mcast_idx = compute_mcast_idx(buf);
874
875 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
876 {
7cdeb319 877 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 878
879 /* update tally counter */
880 ++s->tally_counters.RxERR;
881
4f1c942b 882 return size;
a41b2ff2
PB		 883 }
884
885 packet_header |= RxMulticast;
886
7cdeb319 887 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 888
889 /* update tally counter */
890 ++s->tally_counters.RxOkMul;
891
a41b2ff2 892 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 893 s->phys[1] == buf[1] &&
894 s->phys[2] == buf[2] &&
895 s->phys[3] == buf[3] &&
896 s->phys[4] == buf[4] &&
a41b2ff2
PB		 897 s->phys[5] == buf[5]) {
898 /* match */
899 if (!(s->RxConfig & AcceptMyPhys))
900 {
7cdeb319 901 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 902
903 /* update tally counter */
904 ++s->tally_counters.RxERR;
905
4f1c942b 906 return size;
a41b2ff2
PB		 907 }
908
909 packet_header |= RxPhysical;
910
7cdeb319 911 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 912
913 /* update tally counter */
914 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 915
916 } else {
917
7cdeb319 918 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 919
920 /* update tally counter */
921 ++s->tally_counters.RxERR;
922
4f1c942b 923 return size;
a41b2ff2
PB		 924 }
925 }
926
18dabfd1
BP		 927 /* if too small buffer, then expand it
928 * Include some tailroom in case a vlan tag is later removed. */
929 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 930 memcpy(buf1, buf, size);
18dabfd1 931 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 932 buf = buf1;
18dabfd1
BP		 933 if (size < MIN_BUF_SIZE) {
934 size = MIN_BUF_SIZE;
935 }
a41b2ff2
PB		 936 }
937
938 if (rtl8139_cp_receiver_enabled(s))
939 {
7cdeb319 940 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 941
942 /* begin C+ receiver mode */
943
944/* w0 ownership flag */
945#define CP_RX_OWN (1<<31)
946/* w0 end of ring flag */
947#define CP_RX_EOR (1<<30)
948/* w0 bits 0...12 : buffer size */
949#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
950/* w1 tag available flag */
951#define CP_RX_TAVA (1<<16)
952/* w1 bits 0...15 : VLAN tag */
953#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
954/* w2 low 32bit of Rx buffer ptr */
955/* w3 high 32bit of Rx buffer ptr */
956
957 int descriptor = s->currCPlusRxDesc;
3ada003a 958 dma_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 959
960 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
961 cplus_rx_ring_desc += 16 * descriptor;
962
7cdeb319 963 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
3ada003a 964 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
7cdeb319 965 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 966
967 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
968
a6a29eea 969 pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
a41b2ff2 970 rxdw0 = le32_to_cpu(val);
a6a29eea 971 pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4);
a41b2ff2 972 rxdw1 = le32_to_cpu(val);
a6a29eea 973 pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4);
a41b2ff2 974 rxbufLO = le32_to_cpu(val);
a6a29eea 975 pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4);
a41b2ff2
PB		 976 rxbufHI = le32_to_cpu(val);
977
7cdeb319
BP		 978 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
979 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 980
981 if (!(rxdw0 & CP_RX_OWN))
982 {
7cdeb319
BP		 983 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
984 descriptor);
6cadb320 985
a41b2ff2
PB		 986 s->IntrStatus |= RxOverflow;
987 ++s->RxMissed;
6cadb320
FB		 988
989 /* update tally counter */
990 ++s->tally_counters.RxERR;
991 ++s->tally_counters.MissPkt;
992
a41b2ff2 993 rtl8139_update_irq(s);
4f1c942b 994 return size_;
a41b2ff2
PB		 995 }
996
997 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
998
18dabfd1
BP		 999 /* write VLAN info to descriptor variables. */
1000 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1001 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1002 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1003 size -= VLAN_HLEN;
1004 /* if too small buffer, use the tailroom added duing expansion */
1005 if (size < MIN_BUF_SIZE) {
1006 size = MIN_BUF_SIZE;
1007 }
1008
1009 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1010 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1011 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1012 &dot1q_buf[ETHER_TYPE_LEN]);
1013
7cdeb319
BP		 1014 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1015 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1016 } else {
1017 /* reset VLAN tag flag */
1018 rxdw1 &= ~CP_RX_TAVA;
1019 }
1020
6cadb320
FB		 1021 /* TODO: scatter the packet over available receive ring descriptors space */
1022
a41b2ff2
PB		 1023 if (size+4 > rx_space)
1024 {
7cdeb319
BP		 1025 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1026 descriptor, rx_space, size);
6cadb320 1027
a41b2ff2
PB		 1028 s->IntrStatus |= RxOverflow;
1029 ++s->RxMissed;
6cadb320
FB		 1030
1031 /* update tally counter */
1032 ++s->tally_counters.RxERR;
1033 ++s->tally_counters.MissPkt;
1034
a41b2ff2 1035 rtl8139_update_irq(s);
4f1c942b 1036 return size_;
a41b2ff2
PB		 1037 }
1038
3ada003a 1039 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1040
1041 /* receive/copy to target memory */
18dabfd1 1042 if (dot1q_buf) {
3ada003a
EGM		 1043 pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1044 pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
1045 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1046 size - 2 * ETHER_ADDR_LEN);
18dabfd1 1047 } else {
3ada003a 1048 pci_dma_write(&s->dev, rx_addr, buf, size);
18dabfd1 1049 }
a41b2ff2 1050
6cadb320
FB		 1051 if (s->CpCmd & CPlusRxChkSum)
1052 {
1053 /* do some packet checksumming */
1054 }
1055
a41b2ff2 1056 /* write checksum */
18dabfd1 1057 val = cpu_to_le32(crc32(0, buf, size_));
3ada003a 1058 pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);
a41b2ff2
PB		 1059
1060/* first segment of received packet flag */
1061#define CP_RX_STATUS_FS (1<<29)
1062/* last segment of received packet flag */
1063#define CP_RX_STATUS_LS (1<<28)
1064/* multicast packet flag */
1065#define CP_RX_STATUS_MAR (1<<26)
1066/* physical-matching packet flag */
1067#define CP_RX_STATUS_PAM (1<<25)
1068/* broadcast packet flag */
1069#define CP_RX_STATUS_BAR (1<<24)
1070/* runt packet flag */
1071#define CP_RX_STATUS_RUNT (1<<19)
1072/* crc error flag */
1073#define CP_RX_STATUS_CRC (1<<18)
1074/* IP checksum error flag */
1075#define CP_RX_STATUS_IPF (1<<15)
1076/* UDP checksum error flag */
1077#define CP_RX_STATUS_UDPF (1<<14)
1078/* TCP checksum error flag */
1079#define CP_RX_STATUS_TCPF (1<<13)
1080
1081 /* transfer ownership to target */
1082 rxdw0 &= ~CP_RX_OWN;
1083
1084 /* set first segment bit */
1085 rxdw0 |= CP_RX_STATUS_FS;
1086
1087 /* set last segment bit */
1088 rxdw0 |= CP_RX_STATUS_LS;
1089
1090 /* set received packet type flags */
1091 if (packet_header & RxBroadcast)
1092 rxdw0 |= CP_RX_STATUS_BAR;
1093 if (packet_header & RxMulticast)
1094 rxdw0 |= CP_RX_STATUS_MAR;
1095 if (packet_header & RxPhysical)
1096 rxdw0 |= CP_RX_STATUS_PAM;
1097
1098 /* set received size */
1099 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1100 rxdw0 |= (size+4);
1101
a41b2ff2
PB		 1102 /* update ring data */
1103 val = cpu_to_le32(rxdw0);
3ada003a 1104 pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1105 val = cpu_to_le32(rxdw1);
3ada003a 1106 pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1107
6cadb320
FB		 1108 /* update tally counter */
1109 ++s->tally_counters.RxOk;
1110
a41b2ff2
PB		 1111 /* seek to next Rx descriptor */
1112 if (rxdw0 & CP_RX_EOR)
1113 {
1114 s->currCPlusRxDesc = 0;
1115 }
1116 else
1117 {
1118 ++s->currCPlusRxDesc;
1119 }
1120
7cdeb319 1121 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1122
1123 }
1124 else
1125 {
7cdeb319 1126 DPRINTF("in ring Rx mode ================\n");
6cadb320 1127
a41b2ff2
PB		 1128 /* begin ring receiver mode */
1129 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1130
1131 /* if receiver buffer is empty then avail == 0 */
1132
1133 if (avail != 0 && size + 8 >= avail)
1134 {
7cdeb319
BP		 1135 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1136 "read 0x%04x === available 0x%04x need 0x%04x\n",
1137 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1138
a41b2ff2
PB		 1139 s->IntrStatus |= RxOverflow;
1140 ++s->RxMissed;
1141 rtl8139_update_irq(s);
4f1c942b 1142 return size_;
a41b2ff2
PB		 1143 }
1144
1145 packet_header |= RxStatusOK;
1146
1147 packet_header |= (((size+4) << 16) & 0xffff0000);
1148
1149 /* write header */
1150 uint32_t val = cpu_to_le32(packet_header);
1151
1152 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1153
1154 rtl8139_write_buffer(s, buf, size);
1155
1156 /* write checksum */
ccf1d14a 1157 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1158 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1159
1160 /* correct buffer write pointer */
1161 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1162
1163 /* now we can signal we have received something */
1164
7cdeb319
BP		 1165 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1166 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1167 }
1168
1169 s->IntrStatus |= RxOK;
6cadb320
FB		 1170
1171 if (do_interrupt)
1172 {
1173 rtl8139_update_irq(s);
1174 }
4f1c942b
MM		 1175
1176 return size_;
6cadb320
FB		 1177}
1178
1673ad51 1179static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1180{
1673ad51 1181 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1182}
1183
1184static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1185{
1186 s->RxBufferSize = bufferSize;
1187 s->RxBufPtr = 0;
1188 s->RxBufAddr = 0;
1189}
1190
7f23f812 1191static void rtl8139_reset(DeviceState *d)
a41b2ff2 1192{
7f23f812 1193 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1194 int i;
1195
1196 /* restore MAC address */
254111ec 1197 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1198
1199 /* reset interrupt mask */
1200 s->IntrStatus = 0;
1201 s->IntrMask = 0;
1202
1203 rtl8139_update_irq(s);
1204
a41b2ff2
PB		 1205 /* mark all status registers as owned by host */
1206 for (i = 0; i < 4; ++i)
1207 {
1208 s->TxStatus[i] = TxHostOwns;
1209 }
1210
1211 s->currTxDesc = 0;
1212 s->currCPlusRxDesc = 0;
1213 s->currCPlusTxDesc = 0;
1214
1215 s->RxRingAddrLO = 0;
1216 s->RxRingAddrHI = 0;
1217
1218 s->RxBuf = 0;
1219
1220 rtl8139_reset_rxring(s, 8192);
1221
1222 /* ACK the reset */
1223 s->TxConfig = 0;
1224
1225#if 0
1226// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1227 s->clock_enabled = 0;
1228#else
6cadb320 1229 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1230 s->clock_enabled = 1;
1231#endif
1232
1233 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1234
1235 /* set initial state data */
1236 s->Config0 = 0x0; /* No boot ROM */
1237 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1238 s->Config3 = 0x1; /* fast back-to-back compatible */
1239 s->Config5 = 0x0;
1240
5fafdf24 1241 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1242
1243 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1244 s->cplus_enabled = 0;
1245
a41b2ff2
PB		 1246
1247// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1248// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1249 s->BasicModeCtrl = 0x1000; // autonegotiation
1250
1251 s->BasicModeStatus = 0x7809;
1252 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1253 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1254 s->BasicModeStatus |= 0x0004; /* link is up */
1255
1256 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1257 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1258 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1259
1260 /* also reset timer and disable timer interrupt */
1261 s->TCTR = 0;
1262 s->TimerInt = 0;
1263 s->TCTR_base = 0;
1264
1265 /* reset tally counters */
1266 RTL8139TallyCounters_clear(&s->tally_counters);
1267}
1268
b1d8e52e 1269static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1270{
1271 counters->TxOk = 0;
1272 counters->RxOk = 0;
1273 counters->TxERR = 0;
1274 counters->RxERR = 0;
1275 counters->MissPkt = 0;
1276 counters->FAE = 0;
1277 counters->Tx1Col = 0;
1278 counters->TxMCol = 0;
1279 counters->RxOkPhy = 0;
1280 counters->RxOkBrd = 0;
1281 counters->RxOkMul = 0;
1282 counters->TxAbt = 0;
1283 counters->TxUndrn = 0;
1284}
1285
3ada003a 1286static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
6cadb320 1287{
3ada003a 1288 RTL8139TallyCounters *tally_counters = &s->tally_counters;
6cadb320
FB		 1289 uint16_t val16;
1290 uint32_t val32;
1291 uint64_t val64;
1292
1293 val64 = cpu_to_le64(tally_counters->TxOk);
3ada003a 1294 pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);
6cadb320
FB		 1295
1296 val64 = cpu_to_le64(tally_counters->RxOk);
3ada003a 1297 pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);
6cadb320
FB		 1298
1299 val64 = cpu_to_le64(tally_counters->TxERR);
3ada003a 1300 pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);
6cadb320
FB		 1301
1302 val32 = cpu_to_le32(tally_counters->RxERR);
3ada003a 1303 pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);
6cadb320
FB		 1304
1305 val16 = cpu_to_le16(tally_counters->MissPkt);
3ada003a 1306 pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);
6cadb320
FB		 1307
1308 val16 = cpu_to_le16(tally_counters->FAE);
3ada003a 1309 pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);
6cadb320
FB		 1310
1311 val32 = cpu_to_le32(tally_counters->Tx1Col);
3ada003a 1312 pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);
6cadb320
FB		 1313
1314 val32 = cpu_to_le32(tally_counters->TxMCol);
3ada003a 1315 pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);
6cadb320
FB		 1316
1317 val64 = cpu_to_le64(tally_counters->RxOkPhy);
3ada003a 1318 pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);
6cadb320
FB		 1319
1320 val64 = cpu_to_le64(tally_counters->RxOkBrd);
3ada003a 1321 pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);
6cadb320
FB		 1322
1323 val32 = cpu_to_le32(tally_counters->RxOkMul);
3ada003a 1324 pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);
6cadb320
FB		 1325
1326 val16 = cpu_to_le16(tally_counters->TxAbt);
3ada003a 1327 pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);
6cadb320
FB		 1328
1329 val16 = cpu_to_le16(tally_counters->TxUndrn);
3ada003a 1330 pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);
6cadb320
FB		 1331}
1332
1333/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1334
1335static const VMStateDescription vmstate_tally_counters = {
1336 .name = "tally_counters",
1337 .version_id = 1,
1338 .minimum_version_id = 1,
1339 .minimum_version_id_old = 1,
1340 .fields = (VMStateField []) {
1341 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1342 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1343 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1344 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1345 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1346 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1347 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1348 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1349 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1350 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1351 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1352 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1353 VMSTATE_END_OF_LIST()
1354 }
1355};
a41b2ff2
PB		 1356
1357static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1358{
1359 val &= 0xff;
1360
7cdeb319 1361 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1362
1363 if (val & CmdReset)
1364 {
7cdeb319 1365 DPRINTF("ChipCmd reset\n");
7f23f812 1366 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1367 }
1368 if (val & CmdRxEnb)
1369 {
7cdeb319 1370 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1371
1372 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1373 }
1374 if (val & CmdTxEnb)
1375 {
7cdeb319 1376 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1377
1378 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1379 }
1380
ebabb67a 1381 /* mask unwritable bits */
a41b2ff2
PB		 1382 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1383
1384 /* Deassert reset pin before next read */
1385 val &= ~CmdReset;
1386
1387 s->bChipCmdState = val;
1388}
1389
1390static int rtl8139_RxBufferEmpty(RTL8139State *s)
1391{
1392 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1393
1394 if (unread != 0)
1395 {
7cdeb319 1396 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1397 return 0;
1398 }
1399
7cdeb319 1400 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1401
1402 return 1;
1403}
1404
1405static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1406{
1407 uint32_t ret = s->bChipCmdState;
1408
1409 if (rtl8139_RxBufferEmpty(s))
1410 ret |= RxBufEmpty;
1411
7cdeb319 1412 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1413
1414 return ret;
1415}
1416
1417static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1418{
1419 val &= 0xffff;
1420
7cdeb319 1421 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1422
2c3891ab
AL		 1423 s->cplus_enabled = 1;
1424
ebabb67a 1425 /* mask unwritable bits */
a41b2ff2
PB		 1426 val = SET_MASKED(val, 0xff84, s->CpCmd);
1427
1428 s->CpCmd = val;
1429}
1430
1431static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1432{
1433 uint32_t ret = s->CpCmd;
1434
7cdeb319 1435 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1436
1437 return ret;
1438}
1439
1440static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1441{
7cdeb319 1442 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1443}
1444
1445static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1446{
1447 uint32_t ret = 0;
1448
7cdeb319 1449 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1450
1451 return ret;
1452}
1453
ebabb67a 1454static int rtl8139_config_writable(RTL8139State *s)
a41b2ff2 1455{
eb46c5ed 1456 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
a41b2ff2
PB		 1457 {
1458 return 1;
1459 }
1460
7cdeb319 1461 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1462
1463 return 0;
1464}
1465
1466static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1467{
1468 val &= 0xffff;
1469
7cdeb319 1470 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2 1471
ebabb67a 1472 /* mask unwritable bits */
e3d7e843 1473 uint32_t mask = 0x4cff;
a41b2ff2 1474
ebabb67a 1475 if (1 || !rtl8139_config_writable(s))
a41b2ff2
PB		 1476 {
1477 /* Speed setting and autonegotiation enable bits are read-only */
1478 mask |= 0x3000;
1479 /* Duplex mode setting is read-only */
1480 mask |= 0x0100;
1481 }
1482
1483 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1484
1485 s->BasicModeCtrl = val;
1486}
1487
1488static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1489{
1490 uint32_t ret = s->BasicModeCtrl;
1491
7cdeb319 1492 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1493
1494 return ret;
1495}
1496
1497static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1498{
1499 val &= 0xffff;
1500
7cdeb319 1501 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2 1502
ebabb67a 1503 /* mask unwritable bits */
a41b2ff2
PB		 1504 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1505
1506 s->BasicModeStatus = val;
1507}
1508
1509static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1510{
1511 uint32_t ret = s->BasicModeStatus;
1512
7cdeb319 1513 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1514
1515 return ret;
1516}
1517
1518static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1519{
1520 val &= 0xff;
1521
7cdeb319 1522 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2 1523
ebabb67a 1524 /* mask unwritable bits */
a41b2ff2
PB		 1525 val = SET_MASKED(val, 0x31, s->Cfg9346);
1526
1527 uint32_t opmode = val & 0xc0;
1528 uint32_t eeprom_val = val & 0xf;
1529
1530 if (opmode == 0x80) {
1531 /* eeprom access */
1532 int eecs = (eeprom_val & 0x08)?1:0;
1533 int eesk = (eeprom_val & 0x04)?1:0;
1534 int eedi = (eeprom_val & 0x02)?1:0;
1535 prom9346_set_wire(s, eecs, eesk, eedi);
1536 } else if (opmode == 0x40) {
1537 /* Reset. */
1538 val = 0;
7f23f812 1539 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1540 }
1541
1542 s->Cfg9346 = val;
1543}
1544
1545static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1546{
1547 uint32_t ret = s->Cfg9346;
1548
1549 uint32_t opmode = ret & 0xc0;
1550
1551 if (opmode == 0x80)
1552 {
1553 /* eeprom access */
1554 int eedo = prom9346_get_wire(s);
1555 if (eedo)
1556 {
1557 ret |= 0x01;
1558 }
1559 else
1560 {
1561 ret &= ~0x01;
1562 }
1563 }
1564
7cdeb319 1565 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1566
1567 return ret;
1568}
1569
1570static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1571{
1572 val &= 0xff;
1573
7cdeb319 1574 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2 1575
ebabb67a 1576 if (!rtl8139_config_writable(s)) {
a41b2ff2 1577 return;
ebabb67a 1578 }
a41b2ff2 1579
ebabb67a 1580 /* mask unwritable bits */
a41b2ff2
PB		 1581 val = SET_MASKED(val, 0xf8, s->Config0);
1582
1583 s->Config0 = val;
1584}
1585
1586static uint32_t rtl8139_Config0_read(RTL8139State *s)
1587{
1588 uint32_t ret = s->Config0;
1589
7cdeb319 1590 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1591
1592 return ret;
1593}
1594
1595static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1596{
1597 val &= 0xff;
1598
7cdeb319 1599 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2 1600
ebabb67a 1601 if (!rtl8139_config_writable(s)) {
a41b2ff2 1602 return;
ebabb67a 1603 }
a41b2ff2 1604
ebabb67a 1605 /* mask unwritable bits */
a41b2ff2
PB		 1606 val = SET_MASKED(val, 0xC, s->Config1);
1607
1608 s->Config1 = val;
1609}
1610
1611static uint32_t rtl8139_Config1_read(RTL8139State *s)
1612{
1613 uint32_t ret = s->Config1;
1614
7cdeb319 1615 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1616
1617 return ret;
1618}
1619
1620static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1621{
1622 val &= 0xff;
1623
7cdeb319 1624 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2 1625
ebabb67a 1626 if (!rtl8139_config_writable(s)) {
a41b2ff2 1627 return;
ebabb67a 1628 }
a41b2ff2 1629
ebabb67a 1630 /* mask unwritable bits */
a41b2ff2
PB		 1631 val = SET_MASKED(val, 0x8F, s->Config3);
1632
1633 s->Config3 = val;
1634}
1635
1636static uint32_t rtl8139_Config3_read(RTL8139State *s)
1637{
1638 uint32_t ret = s->Config3;
1639
7cdeb319 1640 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1641
1642 return ret;
1643}
1644
1645static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1646{
1647 val &= 0xff;
1648
7cdeb319 1649 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2 1650
ebabb67a 1651 if (!rtl8139_config_writable(s)) {
a41b2ff2 1652 return;
ebabb67a 1653 }
a41b2ff2 1654
ebabb67a 1655 /* mask unwritable bits */
a41b2ff2
PB		 1656 val = SET_MASKED(val, 0x0a, s->Config4);
1657
1658 s->Config4 = val;
1659}
1660
1661static uint32_t rtl8139_Config4_read(RTL8139State *s)
1662{
1663 uint32_t ret = s->Config4;
1664
7cdeb319 1665 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1666
1667 return ret;
1668}
1669
1670static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1671{
1672 val &= 0xff;
1673
7cdeb319 1674 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2 1675
ebabb67a 1676 /* mask unwritable bits */
a41b2ff2
PB		 1677 val = SET_MASKED(val, 0x80, s->Config5);
1678
1679 s->Config5 = val;
1680}
1681
1682static uint32_t rtl8139_Config5_read(RTL8139State *s)
1683{
1684 uint32_t ret = s->Config5;
1685
7cdeb319 1686 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1687
1688 return ret;
1689}
1690
1691static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1692{
1693 if (!rtl8139_transmitter_enabled(s))
1694 {
7cdeb319 1695 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1696 return;
1697 }
1698
7cdeb319 1699 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1700
1701 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1702
1703 s->TxConfig = val;
1704}
1705
1706static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1707{
7cdeb319 1708 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1709
1710 uint32_t tc = s->TxConfig;
1711 tc &= 0xFFFFFF00;
1712 tc |= (val & 0x000000FF);
1713 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1714}
1715
1716static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1717{
1718 uint32_t ret = s->TxConfig;
1719
7cdeb319 1720 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1721
1722 return ret;
1723}
1724
1725static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1726{
7cdeb319 1727 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2 1728
ebabb67a 1729 /* mask unwritable bits */
a41b2ff2
PB		 1730 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1731
1732 s->RxConfig = val;
1733
1734 /* reset buffer size and read/write pointers */
1735 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1736
7cdeb319 1737 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1738}
1739
1740static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1741{
1742 uint32_t ret = s->RxConfig;
1743
7cdeb319 1744 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1745
1746 return ret;
1747}
1748
bf6b87a8
BP		 1749static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1750 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1751{
bf6b87a8
BP		 1752 struct iovec *iov = NULL;
1753
718da2b9
FB		 1754 if (!size)
1755 {
7cdeb319 1756 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1757 return;
1758 }
1759
bf6b87a8
BP		 1760 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1761 iov = (struct iovec[3]) {
1762 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1763 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1764 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1765 .iov_len = size - ETHER_ADDR_LEN * 2 },
1766 };
1767 }
1768
718da2b9
FB		 1769 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1770 {
bf6b87a8
BP		 1771 size_t buf2_size;
1772 uint8_t *buf2;
1773
1774 if (iov) {
1775 buf2_size = iov_size(iov, 3);
7267c094 1776 buf2 = g_malloc(buf2_size);
bf6b87a8
BP		 1777 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1778 buf = buf2;
1779 }
1780
7cdeb319 1781 DPRINTF("+++ transmit loopback mode\n");
1673ad51 1782 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
bf6b87a8
BP		 1783
1784 if (iov) {
7267c094 1785 g_free(buf2);
bf6b87a8 1786 }
718da2b9
FB		 1787 }
1788 else
1789 {
bf6b87a8
BP		 1790 if (iov) {
1791 qemu_sendv_packet(&s->nic->nc, iov, 3);
1792 } else {
1793 qemu_send_packet(&s->nic->nc, buf, size);
1794 }
718da2b9
FB		 1795 }
1796}
1797
a41b2ff2
PB		 1798static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1799{
1800 if (!rtl8139_transmitter_enabled(s))
1801 {
7cdeb319
BP		 1802 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1803 "disabled\n", descriptor);
a41b2ff2
PB		 1804 return 0;
1805 }
1806
1807 if (s->TxStatus[descriptor] & TxHostOwns)
1808 {
7cdeb319
BP		 1809 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1810 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1811 return 0;
1812 }
1813
7cdeb319 1814 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2
PB		 1815
1816 int txsize = s->TxStatus[descriptor] & 0x1fff;
1817 uint8_t txbuffer[0x2000];
1818
7cdeb319
BP		 1819 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1820 txsize, s->TxAddr[descriptor]);
a41b2ff2 1821
3ada003a 1822 pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1823
1824 /* Mark descriptor as transferred */
1825 s->TxStatus[descriptor] |= TxHostOwns;
1826 s->TxStatus[descriptor] |= TxStatOK;
1827
bf6b87a8 1828 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1829
7cdeb319
BP		 1830 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1831 descriptor);
a41b2ff2
PB		 1832
1833 /* update interrupt */
1834 s->IntrStatus |= TxOK;
1835 rtl8139_update_irq(s);
1836
1837 return 1;
1838}
1839
718da2b9
FB		 1840/* structures and macros for task offloading */
1841typedef struct ip_header
1842{
1843 uint8_t ip_ver_len; /* version and header length */
1844 uint8_t ip_tos; /* type of service */
1845 uint16_t ip_len; /* total length */
1846 uint16_t ip_id; /* identification */
1847 uint16_t ip_off; /* fragment offset field */
1848 uint8_t ip_ttl; /* time to live */
1849 uint8_t ip_p; /* protocol */
1850 uint16_t ip_sum; /* checksum */
1851 uint32_t ip_src,ip_dst; /* source and dest address */
1852} ip_header;
1853
1854#define IP_HEADER_VERSION_4 4
1855#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1856#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1857
1858typedef struct tcp_header
1859{
1860 uint16_t th_sport; /* source port */
1861 uint16_t th_dport; /* destination port */
1862 uint32_t th_seq; /* sequence number */
1863 uint32_t th_ack; /* acknowledgement number */
1864 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1865 uint16_t th_win; /* window */
1866 uint16_t th_sum; /* checksum */
1867 uint16_t th_urp; /* urgent pointer */
1868} tcp_header;
1869
1870typedef struct udp_header
1871{
1872 uint16_t uh_sport; /* source port */
1873 uint16_t uh_dport; /* destination port */
1874 uint16_t uh_ulen; /* udp length */
1875 uint16_t uh_sum; /* udp checksum */
1876} udp_header;
1877
1878typedef struct ip_pseudo_header
1879{
1880 uint32_t ip_src;
1881 uint32_t ip_dst;
1882 uint8_t zeros;
1883 uint8_t ip_proto;
1884 uint16_t ip_payload;
1885} ip_pseudo_header;
1886
1887#define IP_PROTO_TCP 6
1888#define IP_PROTO_UDP 17
1889
1890#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1891#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1892#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1893
1894#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1895
1896#define TCP_FLAG_FIN 0x01
1897#define TCP_FLAG_PUSH 0x08
1898
1899/* produces ones' complement sum of data */
1900static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1901{
1902 uint32_t result = 0;
1903
1904 for (; len > 1; data+=2, len-=2)
1905 {
1906 result += *(uint16_t*)data;
1907 }
1908
1909 /* add the remainder byte */
1910 if (len)
1911 {
1912 uint8_t odd[2] = {*data, 0};
1913 result += *(uint16_t*)odd;
1914 }
1915
1916 while (result>>16)
1917 result = (result & 0xffff) + (result >> 16);
1918
1919 return result;
1920}
1921
1922static uint16_t ip_checksum(void *data, size_t len)
1923{
1924 return ~ones_complement_sum((uint8_t*)data, len);
1925}
1926
a41b2ff2
PB		 1927static int rtl8139_cplus_transmit_one(RTL8139State *s)
1928{
1929 if (!rtl8139_transmitter_enabled(s))
1930 {
7cdeb319 1931 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1932 return 0;
1933 }
1934
1935 if (!rtl8139_cp_transmitter_enabled(s))
1936 {
7cdeb319 1937 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1938 return 0 ;
1939 }
1940
1941 int descriptor = s->currCPlusTxDesc;
1942
3ada003a 1943 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
a41b2ff2
PB		 1944
1945 /* Normal priority ring */
1946 cplus_tx_ring_desc += 16 * descriptor;
1947
7cdeb319 1948 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
4abf12f4 1949 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
7cdeb319 1950 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1951
1952 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1953
3ada003a 1954 pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1955 txdw0 = le32_to_cpu(val);
3ada003a 1956 pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1957 txdw1 = le32_to_cpu(val);
3ada003a 1958 pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
a41b2ff2 1959 txbufLO = le32_to_cpu(val);
3ada003a 1960 pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
a41b2ff2
PB		 1961 txbufHI = le32_to_cpu(val);
1962
7cdeb319
BP		 1963 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1964 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1965
1966/* w0 ownership flag */
1967#define CP_TX_OWN (1<<31)
1968/* w0 end of ring flag */
1969#define CP_TX_EOR (1<<30)
1970/* first segment of received packet flag */
1971#define CP_TX_FS (1<<29)
1972/* last segment of received packet flag */
1973#define CP_TX_LS (1<<28)
1974/* large send packet flag */
1975#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1976/* large send MSS mask, bits 16...25 */
1977#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1978
a41b2ff2
PB		 1979/* IP checksum offload flag */
1980#define CP_TX_IPCS (1<<18)
1981/* UDP checksum offload flag */
1982#define CP_TX_UDPCS (1<<17)
1983/* TCP checksum offload flag */
1984#define CP_TX_TCPCS (1<<16)
1985
1986/* w0 bits 0...15 : buffer size */
1987#define CP_TX_BUFFER_SIZE (1<<16)
1988#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 1989/* w1 add tag flag */
1990#define CP_TX_TAGC (1<<17)
1991/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 1992#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1993/* w2 low 32bit of Rx buffer ptr */
1994/* w3 high 32bit of Rx buffer ptr */
1995
1996/* set after transmission */
1997/* FIFO underrun flag */
1998#define CP_TX_STATUS_UNF (1<<25)
1999/* transmit error summary flag, valid if set any of three below */
2000#define CP_TX_STATUS_TES (1<<23)
2001/* out-of-window collision flag */
2002#define CP_TX_STATUS_OWC (1<<22)
2003/* link failure flag */
2004#define CP_TX_STATUS_LNKF (1<<21)
2005/* excessive collisions flag */
2006#define CP_TX_STATUS_EXC (1<<20)
2007
2008 if (!(txdw0 & CP_TX_OWN))
2009 {
7cdeb319 2010 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 2011 return 0 ;
2012 }
2013
7cdeb319 2014 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 2015
2016 if (txdw0 & CP_TX_FS)
2017 {
7cdeb319
BP		 2018 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2019 "descriptor\n", descriptor);
6cadb320
FB		 2020
2021 /* reset internal buffer offset */
2022 s->cplus_txbuffer_offset = 0;
2023 }
a41b2ff2
PB		 2024
2025 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
3ada003a 2026 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 2027
6cadb320
FB		 2028 /* make sure we have enough space to assemble the packet */
2029 if (!s->cplus_txbuffer)
2030 {
2031 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
7267c094 2032 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
6cadb320 2033 s->cplus_txbuffer_offset = 0;
718da2b9 2034
7cdeb319
BP		 2035 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2036 s->cplus_txbuffer_len);
6cadb320
FB		 2037 }
2038
cde31a0e 2039 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
6cadb320 2040 {
cde31a0e
JW		 2041 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2042 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2043 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2044 "length to %d\n", txsize);
6cadb320
FB		 2045 }
2046
2047 if (!s->cplus_txbuffer)
2048 {
2049 /* out of memory */
a41b2ff2 2050
7cdeb319
BP		 2051 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2052 s->cplus_txbuffer_len);
6cadb320
FB		 2053
2054 /* update tally counter */
2055 ++s->tally_counters.TxERR;
2056 ++s->tally_counters.TxAbt;
2057
2058 return 0;
2059 }
2060
2061 /* append more data to the packet */
2062
7cdeb319 2063 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
3ada003a
EGM		 2064 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2065 s->cplus_txbuffer_offset);
6cadb320 2066
3ada003a
EGM		 2067 pci_dma_read(&s->dev, tx_addr,
2068 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
6cadb320
FB		 2069 s->cplus_txbuffer_offset += txsize;
2070
2071 /* seek to next Rx descriptor */
2072 if (txdw0 & CP_TX_EOR)
2073 {
2074 s->currCPlusTxDesc = 0;
2075 }
2076 else
2077 {
2078 ++s->currCPlusTxDesc;
2079 if (s->currCPlusTxDesc >= 64)
2080 s->currCPlusTxDesc = 0;
2081 }
a41b2ff2
PB		 2082
2083 /* transfer ownership to target */
2084 txdw0 &= ~CP_RX_OWN;
2085
2086 /* reset error indicator bits */
2087 txdw0 &= ~CP_TX_STATUS_UNF;
2088 txdw0 &= ~CP_TX_STATUS_TES;
2089 txdw0 &= ~CP_TX_STATUS_OWC;
2090 txdw0 &= ~CP_TX_STATUS_LNKF;
2091 txdw0 &= ~CP_TX_STATUS_EXC;
2092
2093 /* update ring data */
2094 val = cpu_to_le32(txdw0);
3ada003a 2095 pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2096
6cadb320
FB		 2097 /* Now decide if descriptor being processed is holding the last segment of packet */
2098 if (txdw0 & CP_TX_LS)
a41b2ff2 2099 {
bf6b87a8
BP		 2100 uint8_t dot1q_buffer_space[VLAN_HLEN];
2101 uint16_t *dot1q_buffer;
2102
7cdeb319
BP		 2103 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2104 descriptor);
6cadb320
FB		 2105
2106 /* can transfer fully assembled packet */
2107
2108 uint8_t *saved_buffer = s->cplus_txbuffer;
2109 int saved_size = s->cplus_txbuffer_offset;
2110 int saved_buffer_len = s->cplus_txbuffer_len;
2111
bf6b87a8
BP		 2112 /* create vlan tag */
2113 if (txdw1 & CP_TX_TAGC) {
2114 /* the vlan tag is in BE byte order in the descriptor
2115 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2116 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2117 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2118
2119 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2120 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2121 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2122 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2123 } else {
2124 dot1q_buffer = NULL;
2125 }
2126
6cadb320
FB		 2127 /* reset the card space to protect from recursive call */
2128 s->cplus_txbuffer = NULL;
2129 s->cplus_txbuffer_offset = 0;
2130 s->cplus_txbuffer_len = 0;
2131
718da2b9 2132 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2133 {
7cdeb319 2134 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2135
6cadb320 2136 /* ip packet header */
660f11be 2137 ip_header *ip = NULL;
6cadb320 2138 int hlen = 0;
718da2b9
FB		 2139 uint8_t ip_protocol = 0;
2140 uint16_t ip_data_len = 0;
6cadb320 2141
660f11be 2142 uint8_t *eth_payload_data = NULL;
718da2b9 2143 size_t eth_payload_len = 0;
6cadb320 2144
718da2b9 2145 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2146 if (proto == ETH_P_IP)
2147 {
7cdeb319 2148 DPRINTF("+++ C+ mode has IP packet\n");
6cadb320
FB		 2149
2150 /* not aligned */
718da2b9
FB		 2151 eth_payload_data = saved_buffer + ETH_HLEN;
2152 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2153
718da2b9 2154 ip = (ip_header*)eth_payload_data;
6cadb320 2155
718da2b9 2156 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
7cdeb319
BP		 2157 DPRINTF("+++ C+ mode packet has bad IP version %d "
2158 "expected %d\n", IP_HEADER_VERSION(ip),
2159 IP_HEADER_VERSION_4);
6cadb320
FB		 2160 ip = NULL;
2161 } else {
718da2b9
FB		 2162 hlen = IP_HEADER_LENGTH(ip);
2163 ip_protocol = ip->ip_p;
2164 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2165 }
2166 }
2167
2168 if (ip)
2169 {
2170 if (txdw0 & CP_TX_IPCS)
2171 {
7cdeb319 2172 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2173
718da2b9 2174 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2175 /* bad packet header len */
2176 /* or packet too short */
2177 }
2178 else
2179 {
2180 ip->ip_sum = 0;
718da2b9 2181 ip->ip_sum = ip_checksum(ip, hlen);
7cdeb319
BP		 2182 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2183 hlen, ip->ip_sum);
6cadb320
FB		 2184 }
2185 }
2186
718da2b9 2187 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2188 {
718da2b9 2189 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
ec48c774 2190
7cdeb319
BP		 2191 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2192 "frame data %d specified MSS=%d\n", ETH_MTU,
2193 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2194
718da2b9
FB		 2195 int tcp_send_offset = 0;
2196 int send_count = 0;
6cadb320
FB		 2197
2198 /* maximum IP header length is 60 bytes */
2199 uint8_t saved_ip_header[60];
6cadb320 2200
718da2b9
FB		 2201 /* save IP header template; data area is used in tcp checksum calculation */
2202 memcpy(saved_ip_header, eth_payload_data, hlen);
2203
2204 /* a placeholder for checksum calculation routine in tcp case */
2205 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2206 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2207
2208 /* pointer to TCP header */
2209 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2210
2211 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2212
2213 /* ETH_MTU = ip header len + tcp header len + payload */
2214 int tcp_data_len = ip_data_len - tcp_hlen;
2215 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2216
7cdeb319
BP		 2217 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2218 "data len %d TCP chunk size %d\n", ip_data_len,
2219 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9
FB		 2220
2221 /* note the cycle below overwrites IP header data,
2222 but restores it from saved_ip_header before sending packet */
2223
2224 int is_last_frame = 0;
2225
2226 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2227 {
2228 uint16_t chunk_size = tcp_chunk_size;
2229
2230 /* check if this is the last frame */
2231 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2232 {
2233 is_last_frame = 1;
2234 chunk_size = tcp_data_len - tcp_send_offset;
2235 }
2236
7cdeb319
BP		 2237 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2238 be32_to_cpu(p_tcp_hdr->th_seq));
718da2b9
FB		 2239
2240 /* add 4 TCP pseudoheader fields */
2241 /* copy IP source and destination fields */
2242 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2243
7cdeb319
BP		 2244 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2245 "packet with %d bytes data\n", tcp_hlen +
2246 chunk_size);
718da2b9
FB		 2247
2248 if (tcp_send_offset)
2249 {
2250 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2251 }
2252
2253 /* keep PUSH and FIN flags only for the last frame */
2254 if (!is_last_frame)
2255 {
2256 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2257 }
6cadb320 2258
718da2b9
FB		 2259 /* recalculate TCP checksum */
2260 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2261 p_tcpip_hdr->zeros = 0;
2262 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2263 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2264
2265 p_tcp_hdr->th_sum = 0;
2266
2267 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
7cdeb319
BP		 2268 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2269 tcp_checksum);
718da2b9
FB		 2270
2271 p_tcp_hdr->th_sum = tcp_checksum;
2272
2273 /* restore IP header */
2274 memcpy(eth_payload_data, saved_ip_header, hlen);
2275
2276 /* set IP data length and recalculate IP checksum */
2277 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2278
2279 /* increment IP id for subsequent frames */
2280 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2281
2282 ip->ip_sum = 0;
2283 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
7cdeb319
BP		 2284 DPRINTF("+++ C+ mode TSO IP header len=%d "
2285 "checksum=%04x\n", hlen, ip->ip_sum);
718da2b9
FB		 2286
2287 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
7cdeb319
BP		 2288 DPRINTF("+++ C+ mode TSO transferring packet size "
2289 "%d\n", tso_send_size);
bf6b87a8
BP		 2290 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2291 0, (uint8_t *) dot1q_buffer);
718da2b9
FB		 2292
2293 /* add transferred count to TCP sequence number */
2294 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2295 ++send_count;
2296 }
2297
2298 /* Stop sending this frame */
2299 saved_size = 0;
2300 }
2301 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2302 {
7cdeb319 2303 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
718da2b9
FB		 2304
2305 /* maximum IP header length is 60 bytes */
2306 uint8_t saved_ip_header[60];
2307 memcpy(saved_ip_header, eth_payload_data, hlen);
2308
2309 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2310 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2311
2312 /* add 4 TCP pseudoheader fields */
2313 /* copy IP source and destination fields */
718da2b9 2314 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2315
718da2b9 2316 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320 2317 {
7cdeb319
BP		 2318 DPRINTF("+++ C+ mode calculating TCP checksum for "
2319 "packet with %d bytes data\n", ip_data_len);
6cadb320 2320
718da2b9
FB		 2321 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2322 p_tcpip_hdr->zeros = 0;
2323 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2324 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2325
718da2b9 2326 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2327
2328 p_tcp_hdr->th_sum = 0;
2329
718da2b9 2330 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2331 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2332 tcp_checksum);
6cadb320
FB		 2333
2334 p_tcp_hdr->th_sum = tcp_checksum;
2335 }
718da2b9 2336 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320 2337 {
7cdeb319
BP		 2338 DPRINTF("+++ C+ mode calculating UDP checksum for "
2339 "packet with %d bytes data\n", ip_data_len);
6cadb320 2340
718da2b9
FB		 2341 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2342 p_udpip_hdr->zeros = 0;
2343 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2344 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2345
718da2b9 2346 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2347
6cadb320
FB		 2348 p_udp_hdr->uh_sum = 0;
2349
718da2b9 2350 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2351 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2352 udp_checksum);
6cadb320 2353
6cadb320
FB		 2354 p_udp_hdr->uh_sum = udp_checksum;
2355 }
2356
2357 /* restore IP header */
718da2b9 2358 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2359 }
2360 }
2361 }
2362
2363 /* update tally counter */
2364 ++s->tally_counters.TxOk;
2365
7cdeb319 2366 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2367
bf6b87a8
BP		 2368 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2369 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2370
2371 /* restore card space if there was no recursion and reset offset */
2372 if (!s->cplus_txbuffer)
2373 {
2374 s->cplus_txbuffer = saved_buffer;
2375 s->cplus_txbuffer_len = saved_buffer_len;
2376 s->cplus_txbuffer_offset = 0;
2377 }
2378 else
2379 {
7267c094 2380 g_free(saved_buffer);
6cadb320 2381 }
a41b2ff2
PB		 2382 }
2383 else
2384 {
7cdeb319 2385 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2386 }
2387
a41b2ff2
PB		 2388 return 1;
2389}
2390
2391static void rtl8139_cplus_transmit(RTL8139State *s)
2392{
2393 int txcount = 0;
2394
2395 while (rtl8139_cplus_transmit_one(s))
2396 {
2397 ++txcount;
2398 }
2399
2400 /* Mark transfer completed */
2401 if (!txcount)
2402 {
7cdeb319
BP		 2403 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2404 s->currCPlusTxDesc);
a41b2ff2
PB		 2405 }
2406 else
2407 {
2408 /* update interrupt status */
2409 s->IntrStatus |= TxOK;
2410 rtl8139_update_irq(s);
2411 }
2412}
2413
2414static void rtl8139_transmit(RTL8139State *s)
2415{
2416 int descriptor = s->currTxDesc, txcount = 0;
2417
2418 /*while*/
2419 if (rtl8139_transmit_one(s, descriptor))
2420 {
2421 ++s->currTxDesc;
2422 s->currTxDesc %= 4;
2423 ++txcount;
2424 }
2425
2426 /* Mark transfer completed */
2427 if (!txcount)
2428 {
7cdeb319
BP		 2429 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2430 s->currTxDesc);
a41b2ff2
PB		 2431 }
2432}
2433
2434static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2435{
2436
2437 int descriptor = txRegOffset/4;
6cadb320
FB		 2438
2439 /* handle C+ transmit mode register configuration */
2440
2c3891ab 2441 if (s->cplus_enabled)
6cadb320 2442 {
7cdeb319
BP		 2443 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2444 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2445
2446 /* handle Dump Tally Counters command */
2447 s->TxStatus[descriptor] = val;
2448
2449 if (descriptor == 0 && (val & 0x8))
2450 {
c227f099 2451 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2452
2453 /* dump tally counters to specified memory location */
3ada003a 2454 RTL8139TallyCounters_dma_write(s, tc_addr);
6cadb320
FB		 2455
2456 /* mark dump completed */
2457 s->TxStatus[0] &= ~0x8;
2458 }
2459
2460 return;
2461 }
2462
7cdeb319
BP		 2463 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2464 txRegOffset, val, descriptor);
a41b2ff2
PB		 2465
2466 /* mask only reserved bits */
2467 val &= ~0xff00c000; /* these bits are reset on write */
2468 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2469
2470 s->TxStatus[descriptor] = val;
2471
2472 /* attempt to start transmission */
2473 rtl8139_transmit(s);
2474}
2475
3e48dd4a
SH		 2476static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2477 uint32_t base, uint8_t addr,
2478 int size)
a41b2ff2 2479{
3e48dd4a 2480 uint32_t reg = (addr - base) / 4;
afe0a595
JW		 2481 uint32_t offset = addr & 0x3;
2482 uint32_t ret = 0;
2483
2484 if (addr & (size - 1)) {
3e48dd4a
SH		 2485 DPRINTF("not implemented read for TxStatus/TxAddr "
2486 "addr=0x%x size=0x%x\n", addr, size);
afe0a595
JW		 2487 return ret;
2488 }
a41b2ff2 2489
afe0a595
JW		 2490 switch (size) {
2491 case 1: /* fall through */
2492 case 2: /* fall through */
2493 case 4:
bdc62e62 2494 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
3e48dd4a
SH		 2495 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2496 reg, addr, size, ret);
afe0a595
JW		 2497 break;
2498 default:
3e48dd4a 2499 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
afe0a595
JW		 2500 break;
2501 }
a41b2ff2
PB		 2502
2503 return ret;
2504}
2505
2506static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2507{
2508 uint16_t ret = 0;
2509
2510 /* Simulate TSAD, it is read only anyway */
2511
2512 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2513 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2514 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2515 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2516
2517 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2518 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2519 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2520 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2521
a41b2ff2
PB		 2522 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2523 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2524 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2525 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2526
a41b2ff2
PB		 2527 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2528 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2529 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2530 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2531
a41b2ff2 2532
7cdeb319 2533 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2534
2535 return ret;
2536}
2537
2538static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2539{
2540 uint16_t ret = s->CSCR;
2541
7cdeb319 2542 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2543
2544 return ret;
2545}
2546
2547static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2548{
7cdeb319 2549 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2550
290a0933 2551 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2552}
2553
2554static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2555{
290a0933 2556 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2557
7cdeb319 2558 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2559
2560 return ret;
2561}
2562
2563static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2564{
7cdeb319 2565 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2566
2567 /* this value is off by 16 */
2568 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2569
7cdeb319
BP		 2570 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2571 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2572}
2573
2574static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2575{
2576 /* this value is off by 16 */
2577 uint32_t ret = s->RxBufPtr - 0x10;
2578
7cdeb319 2579 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2580
2581 return ret;
2582}
2583
2584static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2585{
2586 /* this value is NOT off by 16 */
2587 uint32_t ret = s->RxBufAddr;
2588
7cdeb319 2589 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2590
2591 return ret;
2592}
2593
2594static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2595{
7cdeb319 2596 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2597
2598 s->RxBuf = val;
2599
2600 /* may need to reset rxring here */
2601}
2602
2603static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2604{
2605 uint32_t ret = s->RxBuf;
2606
7cdeb319 2607 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2608
2609 return ret;
2610}
2611
2612static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2613{
7cdeb319 2614 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2 2615
ebabb67a 2616 /* mask unwritable bits */
a41b2ff2
PB		 2617 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2618
2619 s->IntrMask = val;
2620
74475455 2621 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2622 rtl8139_update_irq(s);
05447803 2623
a41b2ff2
PB		 2624}
2625
2626static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2627{
2628 uint32_t ret = s->IntrMask;
2629
7cdeb319 2630 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2631
2632 return ret;
2633}
2634
2635static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2636{
7cdeb319 2637 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2638
2639#if 0
2640
2641 /* writing to ISR has no effect */
2642
2643 return;
2644
2645#else
2646 uint16_t newStatus = s->IntrStatus & ~val;
2647
ebabb67a 2648 /* mask unwritable bits */
a41b2ff2
PB		 2649 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2650
2651 /* writing 1 to interrupt status register bit clears it */
2652 s->IntrStatus = 0;
2653 rtl8139_update_irq(s);
2654
2655 s->IntrStatus = newStatus;
05447803
FZ		 2656 /*
2657 * Computing if we miss an interrupt here is not that correct but
2658 * considered that we should have had already an interrupt
2659 * and probably emulated is slower is better to assume this resetting was
26404edc 2660 * done before testing on previous rtl8139_update_irq lead to IRQ losing
05447803 2661 */
74475455 2662 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2663 rtl8139_update_irq(s);
05447803 2664
a41b2ff2
PB		 2665#endif
2666}
2667
2668static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2669{
74475455 2670 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2671
a41b2ff2
PB		 2672 uint32_t ret = s->IntrStatus;
2673
7cdeb319 2674 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2675
2676#if 0
2677
2678 /* reading ISR clears all interrupts */
2679 s->IntrStatus = 0;
2680
2681 rtl8139_update_irq(s);
2682
2683#endif
2684
2685 return ret;
2686}
2687
2688static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2689{
7cdeb319 2690 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2 2691
ebabb67a 2692 /* mask unwritable bits */
a41b2ff2
PB		 2693 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2694
2695 s->MultiIntr = val;
2696}
2697
2698static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2699{
2700 uint32_t ret = s->MultiIntr;
2701
7cdeb319 2702 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2703
2704 return ret;
2705}
2706
2707static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2708{
2709 RTL8139State *s = opaque;
2710
a41b2ff2
PB		 2711 switch (addr)
2712 {
2713 case MAC0 ... MAC0+5:
2714 s->phys[addr - MAC0] = val;
2715 break;
2716 case MAC0+6 ... MAC0+7:
2717 /* reserved */
2718 break;
2719 case MAR0 ... MAR0+7:
2720 s->mult[addr - MAR0] = val;
2721 break;
2722 case ChipCmd:
2723 rtl8139_ChipCmd_write(s, val);
2724 break;
2725 case Cfg9346:
2726 rtl8139_Cfg9346_write(s, val);
2727 break;
2728 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2729 rtl8139_TxConfig_writeb(s, val);
2730 break;
2731 case Config0:
2732 rtl8139_Config0_write(s, val);
2733 break;
2734 case Config1:
2735 rtl8139_Config1_write(s, val);
2736 break;
2737 case Config3:
2738 rtl8139_Config3_write(s, val);
2739 break;
2740 case Config4:
2741 rtl8139_Config4_write(s, val);
2742 break;
2743 case Config5:
2744 rtl8139_Config5_write(s, val);
2745 break;
2746 case MediaStatus:
2747 /* ignore */
7cdeb319
BP		 2748 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2749 val);
a41b2ff2
PB		 2750 break;
2751
2752 case HltClk:
7cdeb319 2753 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2754 if (val == 'R')
2755 {
2756 s->clock_enabled = 1;
2757 }
2758 else if (val == 'H')
2759 {
2760 s->clock_enabled = 0;
2761 }
2762 break;
2763
2764 case TxThresh:
7cdeb319 2765 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2766 s->TxThresh = val;
2767 break;
2768
2769 case TxPoll:
7cdeb319 2770 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2771 if (val & (1 << 7))
2772 {
7cdeb319
BP		 2773 DPRINTF("C+ TxPoll high priority transmission (not "
2774 "implemented)\n");
a41b2ff2
PB		 2775 //rtl8139_cplus_transmit(s);
2776 }
2777 if (val & (1 << 6))
2778 {
7cdeb319 2779 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2780 rtl8139_cplus_transmit(s);
2781 }
2782
2783 break;
2784
2785 default:
7cdeb319
BP		 2786 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2787 val);
a41b2ff2
PB		 2788 break;
2789 }
2790}
2791
2792static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2793{
2794 RTL8139State *s = opaque;
2795
a41b2ff2
PB		 2796 switch (addr)
2797 {
2798 case IntrMask:
2799 rtl8139_IntrMask_write(s, val);
2800 break;
2801
2802 case IntrStatus:
2803 rtl8139_IntrStatus_write(s, val);
2804 break;
2805
2806 case MultiIntr:
2807 rtl8139_MultiIntr_write(s, val);
2808 break;
2809
2810 case RxBufPtr:
2811 rtl8139_RxBufPtr_write(s, val);
2812 break;
2813
2814 case BasicModeCtrl:
2815 rtl8139_BasicModeCtrl_write(s, val);
2816 break;
2817 case BasicModeStatus:
2818 rtl8139_BasicModeStatus_write(s, val);
2819 break;
2820 case NWayAdvert:
7cdeb319 2821 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2822 s->NWayAdvert = val;
2823 break;
2824 case NWayLPAR:
7cdeb319 2825 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2826 break;
2827 case NWayExpansion:
7cdeb319 2828 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2829 s->NWayExpansion = val;
2830 break;
2831
2832 case CpCmd:
2833 rtl8139_CpCmd_write(s, val);
2834 break;
2835
6cadb320
FB		 2836 case IntrMitigate:
2837 rtl8139_IntrMitigate_write(s, val);
2838 break;
2839
a41b2ff2 2840 default:
7cdeb319
BP		 2841 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2842 addr, val);
a41b2ff2 2843
a41b2ff2
PB		 2844 rtl8139_io_writeb(opaque, addr, val & 0xff);
2845 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2846 break;
2847 }
2848}
2849
05447803
FZ		 2850static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2851{
2852 int64_t pci_time, next_time;
2853 uint32_t low_pci;
2854
7cdeb319 2855 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803
FZ		 2856
2857 if (s->TimerExpire && current_time >= s->TimerExpire) {
2858 s->IntrStatus |= PCSTimeout;
2859 rtl8139_update_irq(s);
2860 }
2861
2862 /* Set QEMU timer only if needed that is
2863 * - TimerInt <> 0 (we have a timer)
2864 * - mask = 1 (we want an interrupt timer)
2865 * - irq = 0 (irq is not already active)
2866 * If any of above change we need to compute timer again
2867 * Also we must check if timer is passed without QEMU timer
2868 */
2869 s->TimerExpire = 0;
2870 if (!s->TimerInt) {
2871 return;
2872 }
2873
2874 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2875 get_ticks_per_sec());
2876 low_pci = pci_time & 0xffffffff;
2877 pci_time = pci_time - low_pci + s->TimerInt;
2878 if (low_pci >= s->TimerInt) {
2879 pci_time += 0x100000000LL;
2880 }
2881 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2882 PCI_FREQUENCY);
2883 s->TimerExpire = next_time;
2884
2885 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2886 qemu_mod_timer(s->timer, next_time);
2887 }
2888}
2889
a41b2ff2
PB		 2890static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2891{
2892 RTL8139State *s = opaque;
2893
a41b2ff2
PB		 2894 switch (addr)
2895 {
2896 case RxMissed:
7cdeb319 2897 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2898 s->RxMissed = 0;
2899 break;
2900
2901 case TxConfig:
2902 rtl8139_TxConfig_write(s, val);
2903 break;
2904
2905 case RxConfig:
2906 rtl8139_RxConfig_write(s, val);
2907 break;
2908
2909 case TxStatus0 ... TxStatus0+4*4-1:
2910 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2911 break;
2912
2913 case TxAddr0 ... TxAddr0+4*4-1:
2914 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2915 break;
2916
2917 case RxBuf:
2918 rtl8139_RxBuf_write(s, val);
2919 break;
2920
2921 case RxRingAddrLO:
7cdeb319 2922 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2923 s->RxRingAddrLO = val;
2924 break;
2925
2926 case RxRingAddrHI:
7cdeb319 2927 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2928 s->RxRingAddrHI = val;
2929 break;
2930
6cadb320 2931 case Timer:
7cdeb319 2932 DPRINTF("TCTR Timer reset on write\n");
74475455 2933 s->TCTR_base = qemu_get_clock_ns(vm_clock);
05447803 2934 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2935 break;
2936
2937 case FlashReg:
7cdeb319 2938 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2939 if (s->TimerInt != val) {
2940 s->TimerInt = val;
74475455 2941 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2942 }
6cadb320
FB		 2943 break;
2944
a41b2ff2 2945 default:
7cdeb319
BP		 2946 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2947 addr, val);
a41b2ff2
PB		 2948 rtl8139_io_writeb(opaque, addr, val & 0xff);
2949 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2950 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2951 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2952 break;
2953 }
2954}
2955
2956static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2957{
2958 RTL8139State *s = opaque;
2959 int ret;
2960
a41b2ff2
PB		 2961 switch (addr)
2962 {
2963 case MAC0 ... MAC0+5:
2964 ret = s->phys[addr - MAC0];
2965 break;
2966 case MAC0+6 ... MAC0+7:
2967 ret = 0;
2968 break;
2969 case MAR0 ... MAR0+7:
2970 ret = s->mult[addr - MAR0];
2971 break;
afe0a595 2972 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 2973 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2974 addr, 1);
afe0a595 2975 break;
a41b2ff2
PB		 2976 case ChipCmd:
2977 ret = rtl8139_ChipCmd_read(s);
2978 break;
2979 case Cfg9346:
2980 ret = rtl8139_Cfg9346_read(s);
2981 break;
2982 case Config0:
2983 ret = rtl8139_Config0_read(s);
2984 break;
2985 case Config1:
2986 ret = rtl8139_Config1_read(s);
2987 break;
2988 case Config3:
2989 ret = rtl8139_Config3_read(s);
2990 break;
2991 case Config4:
2992 ret = rtl8139_Config4_read(s);
2993 break;
2994 case Config5:
2995 ret = rtl8139_Config5_read(s);
2996 break;
2997
2998 case MediaStatus:
2999 ret = 0xd0;
7cdeb319 3000 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 3001 break;
3002
3003 case HltClk:
3004 ret = s->clock_enabled;
7cdeb319 3005 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 3006 break;
3007
3008 case PCIRevisionID:
6cadb320 3009 ret = RTL8139_PCI_REVID;
7cdeb319 3010 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 3011 break;
3012
3013 case TxThresh:
3014 ret = s->TxThresh;
7cdeb319 3015 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3016 break;
3017
3018 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3019 ret = s->TxConfig >> 24;
7cdeb319 3020 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3021 break;
3022
3023 default:
7cdeb319 3024 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 3025 ret = 0;
3026 break;
3027 }
3028
3029 return ret;
3030}
3031
3032static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3033{
3034 RTL8139State *s = opaque;
3035 uint32_t ret;
3036
a41b2ff2
PB		 3037 switch (addr)
3038 {
afe0a595 3039 case TxAddr0 ... TxAddr0+4*4-1:
3e48dd4a 3040 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
afe0a595 3041 break;
a41b2ff2
PB		 3042 case IntrMask:
3043 ret = rtl8139_IntrMask_read(s);
3044 break;
3045
3046 case IntrStatus:
3047 ret = rtl8139_IntrStatus_read(s);
3048 break;
3049
3050 case MultiIntr:
3051 ret = rtl8139_MultiIntr_read(s);
3052 break;
3053
3054 case RxBufPtr:
3055 ret = rtl8139_RxBufPtr_read(s);
3056 break;
3057
6cadb320
FB		 3058 case RxBufAddr:
3059 ret = rtl8139_RxBufAddr_read(s);
3060 break;
3061
a41b2ff2
PB		 3062 case BasicModeCtrl:
3063 ret = rtl8139_BasicModeCtrl_read(s);
3064 break;
3065 case BasicModeStatus:
3066 ret = rtl8139_BasicModeStatus_read(s);
3067 break;
3068 case NWayAdvert:
3069 ret = s->NWayAdvert;
7cdeb319 3070 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3071 break;
3072 case NWayLPAR:
3073 ret = s->NWayLPAR;
7cdeb319 3074 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3075 break;
3076 case NWayExpansion:
3077 ret = s->NWayExpansion;
7cdeb319 3078 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3079 break;
3080
3081 case CpCmd:
3082 ret = rtl8139_CpCmd_read(s);
3083 break;
3084
6cadb320
FB		 3085 case IntrMitigate:
3086 ret = rtl8139_IntrMitigate_read(s);
3087 break;
3088
a41b2ff2
PB		 3089 case TxSummary:
3090 ret = rtl8139_TSAD_read(s);
3091 break;
3092
3093 case CSCR:
3094 ret = rtl8139_CSCR_read(s);
3095 break;
3096
3097 default:
7cdeb319 3098 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3099
a41b2ff2
PB		 3100 ret = rtl8139_io_readb(opaque, addr);
3101 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3102
7cdeb319 3103 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3104 break;
3105 }
3106
3107 return ret;
3108}
3109
3110static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3111{
3112 RTL8139State *s = opaque;
3113 uint32_t ret;
3114
a41b2ff2
PB		 3115 switch (addr)
3116 {
3117 case RxMissed:
3118 ret = s->RxMissed;
3119
7cdeb319 3120 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3121 break;
3122
3123 case TxConfig:
3124 ret = rtl8139_TxConfig_read(s);
3125 break;
3126
3127 case RxConfig:
3128 ret = rtl8139_RxConfig_read(s);
3129 break;
3130
3131 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 3132 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3133 addr, 4);
a41b2ff2
PB		 3134 break;
3135
3136 case TxAddr0 ... TxAddr0+4*4-1:
3137 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3138 break;
3139
3140 case RxBuf:
3141 ret = rtl8139_RxBuf_read(s);
3142 break;
3143
3144 case RxRingAddrLO:
3145 ret = s->RxRingAddrLO;
7cdeb319 3146 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3147 break;
3148
3149 case RxRingAddrHI:
3150 ret = s->RxRingAddrHI;
7cdeb319 3151 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3152 break;
3153
3154 case Timer:
74475455 3155 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
05447803 3156 PCI_FREQUENCY, get_ticks_per_sec());
7cdeb319 3157 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3158 break;
3159
3160 case FlashReg:
3161 ret = s->TimerInt;
7cdeb319 3162 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3163 break;
3164
3165 default:
7cdeb319 3166 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3167
a41b2ff2
PB		 3168 ret = rtl8139_io_readb(opaque, addr);
3169 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3170 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3171 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3172
7cdeb319 3173 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3174 break;
3175 }
3176
3177 return ret;
3178}
3179
3180/* */
3181
3182static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3183{
3184 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3185}
3186
3187static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3188{
3189 rtl8139_io_writew(opaque, addr & 0xFF, val);
3190}
3191
3192static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3193{
3194 rtl8139_io_writel(opaque, addr & 0xFF, val);
3195}
3196
3197static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3198{
3199 return rtl8139_io_readb(opaque, addr & 0xFF);
3200}
3201
3202static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3203{
3204 return rtl8139_io_readw(opaque, addr & 0xFF);
3205}
3206
3207static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3208{
3209 return rtl8139_io_readl(opaque, addr & 0xFF);
3210}
3211
3212/* */
3213
c227f099 3214static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3215{
3216 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3217}
3218
c227f099 3219static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3220{
3221 rtl8139_io_writew(opaque, addr & 0xFF, val);
3222}
3223
c227f099 3224static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3225{
3226 rtl8139_io_writel(opaque, addr & 0xFF, val);
3227}
3228
c227f099 3229static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3230{
3231 return rtl8139_io_readb(opaque, addr & 0xFF);
3232}
3233
c227f099 3234static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3235{
5fedc612 3236 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3237 return val;
a41b2ff2
PB		 3238}
3239
c227f099 3240static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3241{
5fedc612 3242 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3243 return val;
a41b2ff2
PB		 3244}
3245
060110c3 3246static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3247{
6597ebbb 3248 RTL8139State* s = opaque;
74475455 3249 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
060110c3 3250 if (version_id < 4) {
2c3891ab
AL		 3251 s->cplus_enabled = s->CpCmd != 0;
3252 }
3253
a41b2ff2
PB		 3254 return 0;
3255}
3256
c574ba5a
AW		 3257static bool rtl8139_hotplug_ready_needed(void *opaque)
3258{
3259 return qdev_machine_modified();
3260}
3261
3262static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3263 .name = "rtl8139/hotplug_ready",
3264 .version_id = 1,
3265 .minimum_version_id = 1,
3266 .minimum_version_id_old = 1,
3267 .fields = (VMStateField []) {
3268 VMSTATE_END_OF_LIST()
3269 }
3270};
3271
05447803
FZ		 3272static void rtl8139_pre_save(void *opaque)
3273{
3274 RTL8139State* s = opaque;
74475455 3275 int64_t current_time = qemu_get_clock_ns(vm_clock);
05447803
FZ		 3276
3277 /* set IntrStatus correctly */
3278 rtl8139_set_next_tctr_time(s, current_time);
3279 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3280 get_ticks_per_sec());
bd80f3fc 3281 s->rtl8139_mmio_io_addr_dummy = 0;
05447803
FZ		 3282}
3283
060110c3
JQ		 3284static const VMStateDescription vmstate_rtl8139 = {
3285 .name = "rtl8139",
3286 .version_id = 4,
3287 .minimum_version_id = 3,
3288 .minimum_version_id_old = 3,
3289 .post_load = rtl8139_post_load,
05447803 3290 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3291 .fields = (VMStateField []) {
3292 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3293 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3294 VMSTATE_BUFFER(mult, RTL8139State),
3295 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3296 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3297
3298 VMSTATE_UINT32(RxBuf, RTL8139State),
3299 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3300 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3301 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3302
3303 VMSTATE_UINT16(IntrStatus, RTL8139State),
3304 VMSTATE_UINT16(IntrMask, RTL8139State),
3305
3306 VMSTATE_UINT32(TxConfig, RTL8139State),
3307 VMSTATE_UINT32(RxConfig, RTL8139State),
3308 VMSTATE_UINT32(RxMissed, RTL8139State),
3309 VMSTATE_UINT16(CSCR, RTL8139State),
3310
3311 VMSTATE_UINT8(Cfg9346, RTL8139State),
3312 VMSTATE_UINT8(Config0, RTL8139State),
3313 VMSTATE_UINT8(Config1, RTL8139State),
3314 VMSTATE_UINT8(Config3, RTL8139State),
3315 VMSTATE_UINT8(Config4, RTL8139State),
3316 VMSTATE_UINT8(Config5, RTL8139State),
3317
3318 VMSTATE_UINT8(clock_enabled, RTL8139State),
3319 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3320
3321 VMSTATE_UINT16(MultiIntr, RTL8139State),
3322
3323 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3324 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3325 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3326 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3327 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3328
3329 VMSTATE_UINT16(CpCmd, RTL8139State),
3330 VMSTATE_UINT8(TxThresh, RTL8139State),
3331
3332 VMSTATE_UNUSED(4),
3333 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3334 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3335
3336 VMSTATE_UINT32(currTxDesc, RTL8139State),
3337 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3338 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3339 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3340 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3341
3342 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3343 VMSTATE_INT32(eeprom.mode, RTL8139State),
3344 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3345 VMSTATE_UINT8(eeprom.address, RTL8139State),
3346 VMSTATE_UINT16(eeprom.input, RTL8139State),
3347 VMSTATE_UINT16(eeprom.output, RTL8139State),
3348
3349 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3350 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3351 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3352 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3353
3354 VMSTATE_UINT32(TCTR, RTL8139State),
3355 VMSTATE_UINT32(TimerInt, RTL8139State),
3356 VMSTATE_INT64(TCTR_base, RTL8139State),
3357
3358 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3359 vmstate_tally_counters, RTL8139TallyCounters),
3360
3361 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3362 VMSTATE_END_OF_LIST()
c574ba5a
AW		 3363 },
3364 .subsections = (VMStateSubsection []) {
3365 {
3366 .vmsd = &vmstate_rtl8139_hotplug_ready,
3367 .needed = rtl8139_hotplug_ready_needed,
3368 }, {
3369 /* empty */
3370 }
060110c3
JQ		 3371 }
3372};
3373
a41b2ff2
PB		 3374/***********************************************************/
3375/* PCI RTL8139 definitions */
3376
bd80f3fc
AK		 3377static const MemoryRegionPortio rtl8139_portio[] = {
3378 { 0, 0x100, 1, .read = rtl8139_ioport_readb, },
3379 { 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
3380 { 0, 0x100, 2, .read = rtl8139_ioport_readw, },
3381 { 0, 0x100, 2, .write = rtl8139_ioport_writew, },
3382 { 0, 0x100, 4, .read = rtl8139_ioport_readl, },
3383 { 0, 0x100, 4, .write = rtl8139_ioport_writel, },
3384 PORTIO_END_OF_LIST()
3385};
a41b2ff2 3386
bd80f3fc
AK		 3387static const MemoryRegionOps rtl8139_io_ops = {
3388 .old_portio = rtl8139_portio,
3389 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3390};
3391
bd80f3fc
AK		 3392static const MemoryRegionOps rtl8139_mmio_ops = {
3393 .old_mmio = {
3394 .read = {
3395 rtl8139_mmio_readb,
3396 rtl8139_mmio_readw,
3397 rtl8139_mmio_readl,
3398 },
3399 .write = {
3400 rtl8139_mmio_writeb,
3401 rtl8139_mmio_writew,
3402 rtl8139_mmio_writel,
3403 },
3404 },
3405 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3406};
3407
6cadb320
FB		 3408static void rtl8139_timer(void *opaque)
3409{
3410 RTL8139State *s = opaque;
3411
6cadb320
FB		 3412 if (!s->clock_enabled)
3413 {
7cdeb319 3414 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3415 return;
3416 }
3417
05447803
FZ		 3418 s->IntrStatus |= PCSTimeout;
3419 rtl8139_update_irq(s);
74475455 3420 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
6cadb320 3421}
6cadb320 3422
1673ad51 3423static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3424{
1673ad51 3425 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3426
1673ad51 3427 s->nic = NULL;
254111ec
GH		 3428}
3429
3430static int pci_rtl8139_uninit(PCIDevice *dev)
3431{
3432 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3433
bd80f3fc
AK		 3434 memory_region_destroy(&s->bar_io);
3435 memory_region_destroy(&s->bar_mem);
b946a153 3436 if (s->cplus_txbuffer) {
7267c094 3437 g_free(s->cplus_txbuffer);
b946a153
AL		 3438 s->cplus_txbuffer = NULL;
3439 }
b946a153
AL		 3440 qemu_del_timer(s->timer);
3441 qemu_free_timer(s->timer);
1673ad51 3442 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3443 return 0;
3444}
3445
1673ad51
MM		 3446static NetClientInfo net_rtl8139_info = {
3447 .type = NET_CLIENT_TYPE_NIC,
3448 .size = sizeof(NICState),
3449 .can_receive = rtl8139_can_receive,
3450 .receive = rtl8139_receive,
3451 .cleanup = rtl8139_cleanup,
3452};
3453
81a322d4 3454static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3455{
efd6dd45 3456 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3457 uint8_t *pci_conf;
3b46e624 3458
efd6dd45 3459 pci_conf = s->dev.config;
817e0b6f 3460 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
0b5b3547
MT		 3461 /* TODO: start of capability list, but no capability
3462 * list bit in status register, and offset 0xdc seems unused. */
3463 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3464
bd80f3fc
AK		 3465 memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
3466 memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
e824b2cc
AK		 3467 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3468 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
a41b2ff2 3469
254111ec 3470 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3471
7165448a
WD		 3472 /* prepare eeprom */
3473 s->eeprom.contents[0] = 0x8129;
3474#if 1
3475 /* PCI vendor and device ID should be mirrored here */
3476 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3477 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3478#endif
3479 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3480 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3481 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3482
1673ad51 3483 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
f79f2bfc 3484 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
1673ad51 3485 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3486
3487 s->cplus_txbuffer = NULL;
3488 s->cplus_txbuffer_len = 0;
3489 s->cplus_txbuffer_offset = 0;
3b46e624 3490
05447803 3491 s->TimerExpire = 0;
74475455
PB		 3492 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3493 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
1ca4d09a
GN		 3494
3495 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3496
81a322d4 3497 return 0;
a41b2ff2 3498}
9d07d757 3499
40021f08
AL		 3500static Property rtl8139_properties[] = {
3501 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3502 DEFINE_PROP_END_OF_LIST(),
3503};
3504
3505static void rtl8139_class_init(ObjectClass *klass, void *data)
3506{
39bffca2 3507 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3508 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3509
3510 k->init = pci_rtl8139_init;
3511 k->exit = pci_rtl8139_uninit;
3512 k->romfile = "pxe-rtl8139.rom";
3513 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3514 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3515 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3516 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2
AL		 3517 dc->reset = rtl8139_reset;
3518 dc->vmsd = &vmstate_rtl8139;
3519 dc->props = rtl8139_properties;
40021f08
AL		 3520}
3521
39bffca2
AL		 3522static TypeInfo rtl8139_info = {
3523 .name = "rtl8139",
3524 .parent = TYPE_PCI_DEVICE,
3525 .instance_size = sizeof(RTL8139State),
3526 .class_init = rtl8139_class_init,
0aab0d3a
GH		 3527};
3528
83f7d43a 3529static void rtl8139_register_types(void)
9d07d757 3530{
39bffca2 3531 type_register_static(&rtl8139_info);
9d07d757
PB		 3532}
3533
83f7d43a 3534type_init(rtl8139_register_types)
Qemu copy for testing