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Merge git://github.com/hw-claudio/qemu-aarch64-queue into tcg-next
[qemu.git] / hw / sd / sdhci.c
CommitLineData
d7dfca08
IM		 1/*
2 * SD Association Host Standard Specification v2.0 controller emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
7 *
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
83c9f4ca 25#include "hw/hw.h"
d7dfca08
IM		 26#include "sysemu/blockdev.h"
27#include "sysemu/dma.h"
28#include "qemu/timer.h"
29#include "block/block_int.h"
30#include "qemu/bitops.h"
31
47b43a1f 32#include "sdhci.h"
d7dfca08
IM		 33
34/* host controller debug messages */
35#ifndef SDHC_DEBUG
36#define SDHC_DEBUG 0
37#endif
38
39#if SDHC_DEBUG == 0
40 #define DPRINT_L1(fmt, args...) do { } while (0)
41 #define DPRINT_L2(fmt, args...) do { } while (0)
42 #define ERRPRINT(fmt, args...) do { } while (0)
43#elif SDHC_DEBUG == 1
44 #define DPRINT_L1(fmt, args...) \
45 do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0)
46 #define DPRINT_L2(fmt, args...) do { } while (0)
47 #define ERRPRINT(fmt, args...) \
48 do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0)
49#else
50 #define DPRINT_L1(fmt, args...) \
51 do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0)
52 #define DPRINT_L2(fmt, args...) \
53 do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0)
54 #define ERRPRINT(fmt, args...) \
55 do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0)
56#endif
57
58/* Default SD/MMC host controller features information, which will be
59 * presented in CAPABILITIES register of generic SD host controller at reset.
60 * If not stated otherwise:
61 * 0 - not supported, 1 - supported, other - prohibited.
62 */
63#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
64#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
65#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
66#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
67#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
68#define SDHC_CAPAB_SDMA 1ul /* SDMA support */
69#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
70#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
71#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
72/* Maximum host controller R/W buffers size
73 * Possible values: 512, 1024, 2048 bytes */
74#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
75/* Maximum clock frequency for SDclock in MHz
76 * value in range 10-63 MHz, 0 - not defined */
77#define SDHC_CAPAB_BASECLKFREQ 0ul
78#define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
79/* Timeout clock frequency 1-63, 0 - not defined */
80#define SDHC_CAPAB_TOCLKFREQ 0ul
81
82/* Now check all parameters and calculate CAPABILITIES REGISTER value */
83#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
84 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
85 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
86 SDHC_CAPAB_TOUNIT > 1
87#error Capabilities features can have value 0 or 1 only!
88#endif
89
90#if SDHC_CAPAB_MAXBLOCKLENGTH == 512
91#define MAX_BLOCK_LENGTH 0ul
92#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
93#define MAX_BLOCK_LENGTH 1ul
94#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
95#define MAX_BLOCK_LENGTH 2ul
96#else
97#error Max host controller block size can have value 512, 1024 or 2048 only!
98#endif
99
100#if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
101 SDHC_CAPAB_BASECLKFREQ > 63
102#error SDclock frequency can have value in range 0, 10-63 only!
103#endif
104
105#if SDHC_CAPAB_TOCLKFREQ > 63
106#error Timeout clock frequency can have value in range 0-63 only!
107#endif
108
109#define SDHC_CAPAB_REG_DEFAULT \
110 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
111 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
112 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
113 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
114 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
115 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
116 (SDHC_CAPAB_TOCLKFREQ))
117
118#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
119
120static uint8_t sdhci_slotint(SDHCIState *s)
121{
122 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
123 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) ||
124 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
125}
126
127static inline void sdhci_update_irq(SDHCIState *s)
128{
129 qemu_set_irq(s->irq, sdhci_slotint(s));
130}
131
132static void sdhci_raise_insertion_irq(void *opaque)
133{
134 SDHCIState *s = (SDHCIState *)opaque;
135
136 if (s->norintsts & SDHC_NIS_REMOVE) {
137 qemu_mod_timer(s->insert_timer,
138 qemu_get_clock_ns(vm_clock) + SDHC_INSERTION_DELAY);
139 } else {
140 s->prnsts = 0x1ff0000;
141 if (s->norintstsen & SDHC_NISEN_INSERT) {
142 s->norintsts |= SDHC_NIS_INSERT;
143 }
144 sdhci_update_irq(s);
145 }
146}
147
148static void sdhci_insert_eject_cb(void *opaque, int irq, int level)
149{
150 SDHCIState *s = (SDHCIState *)opaque;
151 DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject");
152
153 if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
154 /* Give target some time to notice card ejection */
155 qemu_mod_timer(s->insert_timer,
156 qemu_get_clock_ns(vm_clock) + SDHC_INSERTION_DELAY);
157 } else {
158 if (level) {
159 s->prnsts = 0x1ff0000;
160 if (s->norintstsen & SDHC_NISEN_INSERT) {
161 s->norintsts |= SDHC_NIS_INSERT;
162 }
163 } else {
164 s->prnsts = 0x1fa0000;
165 s->pwrcon &= ~SDHC_POWER_ON;
166 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
167 if (s->norintstsen & SDHC_NISEN_REMOVE) {
168 s->norintsts |= SDHC_NIS_REMOVE;
169 }
170 }
171 sdhci_update_irq(s);
172 }
173}
174
175static void sdhci_card_readonly_cb(void *opaque, int irq, int level)
176{
177 SDHCIState *s = (SDHCIState *)opaque;
178
179 if (level) {
180 s->prnsts &= ~SDHC_WRITE_PROTECT;
181 } else {
182 /* Write enabled */
183 s->prnsts |= SDHC_WRITE_PROTECT;
184 }
185}
186
187static void sdhci_reset(SDHCIState *s)
188{
189 qemu_del_timer(s->insert_timer);
190 qemu_del_timer(s->transfer_timer);
191 /* Set all registers to 0. Capabilities registers are not cleared
192 * and assumed to always preserve their value, given to them during
193 * initialization */
194 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
195
196 sd_set_cb(s->card, s->ro_cb, s->eject_cb);
197 s->data_count = 0;
198 s->stopped_state = sdhc_not_stopped;
199}
200
201static void sdhci_do_data_transfer(void *opaque)
202{
203 SDHCIState *s = (SDHCIState *)opaque;
204
205 SDHCI_GET_CLASS(s)->data_transfer(s);
206}
207
208static void sdhci_send_command(SDHCIState *s)
209{
210 SDRequest request;
211 uint8_t response[16];
212 int rlen;
213
214 s->errintsts = 0;
215 s->acmd12errsts = 0;
216 request.cmd = s->cmdreg >> 8;
217 request.arg = s->argument;
218 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg);
219 rlen = sd_do_command(s->card, &request, response);
220
221 if (s->cmdreg & SDHC_CMD_RESPONSE) {
222 if (rlen == 4) {
223 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) |
224 (response[2] << 8) | response[3];
225 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
226 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]);
227 } else if (rlen == 16) {
228 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) |
229 (response[13] << 8) | response[14];
230 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) |
231 (response[9] << 8) | response[10];
232 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) |
233 (response[5] << 8) | response[6];
234 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
235 response[2];
236 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
237 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
238 s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]);
239 } else {
240 ERRPRINT("Timeout waiting for command response\n");
241 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
242 s->errintsts |= SDHC_EIS_CMDTIMEOUT;
243 s->norintsts |= SDHC_NIS_ERR;
244 }
245 }
246
247 if ((s->norintstsen & SDHC_NISEN_TRSCMP) &&
248 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
249 s->norintsts |= SDHC_NIS_TRSCMP;
250 }
251 } else if (rlen != 0 && (s->errintstsen & SDHC_EISEN_CMDIDX)) {
252 s->errintsts |= SDHC_EIS_CMDIDX;
253 s->norintsts |= SDHC_NIS_ERR;
254 }
255
256 if (s->norintstsen & SDHC_NISEN_CMDCMP) {
257 s->norintsts |= SDHC_NIS_CMDCMP;
258 }
259
260 sdhci_update_irq(s);
261
262 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
656f416c 263 s->data_count = 0;
d7dfca08
IM		 264 sdhci_do_data_transfer(s);
265 }
266}
267
268static void sdhci_end_transfer(SDHCIState *s)
269{
270 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
271 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
272 SDRequest request;
273 uint8_t response[16];
274
275 request.cmd = 0x0C;
276 request.arg = 0;
277 DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg);
278 sd_do_command(s->card, &request, response);
279 /* Auto CMD12 response goes to the upper Response register */
280 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) |
281 (response[2] << 8) | response[3];
282 }
283
284 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE |
285 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT |
286 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE);
287
288 if (s->norintstsen & SDHC_NISEN_TRSCMP) {
289 s->norintsts |= SDHC_NIS_TRSCMP;
290 }
291
292 sdhci_update_irq(s);
293}
294
295/*
296 * Programmed i/o data transfer
297 */
298
299/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
300static void sdhci_read_block_from_card(SDHCIState *s)
301{
302 int index = 0;
303
304 if ((s->trnmod & SDHC_TRNS_MULTI) &&
305 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
306 return;
307 }
308
309 for (index = 0; index < (s->blksize & 0x0fff); index++) {
310 s->fifo_buffer[index] = sd_read_data(s->card);
311 }
312
313 /* New data now available for READ through Buffer Port Register */
314 s->prnsts |= SDHC_DATA_AVAILABLE;
315 if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
316 s->norintsts |= SDHC_NIS_RBUFRDY;
317 }
318
319 /* Clear DAT line active status if that was the last block */
320 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
321 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
322 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
323 }
324
325 /* If stop at block gap request was set and it's not the last block of
326 * data - generate Block Event interrupt */
327 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
328 s->blkcnt != 1) {
329 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
330 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
331 s->norintsts |= SDHC_EIS_BLKGAP;
332 }
333 }
334
335 sdhci_update_irq(s);
336}
337
338/* Read @size byte of data from host controller @s BUFFER DATA PORT register */
339static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
340{
341 uint32_t value = 0;
342 int i;
343
344 /* first check that a valid data exists in host controller input buffer */
345 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
346 ERRPRINT("Trying to read from empty buffer\n");
347 return 0;
348 }
349
350 for (i = 0; i < size; i++) {
351 value |= s->fifo_buffer[s->data_count] << i * 8;
352 s->data_count++;
353 /* check if we've read all valid data (blksize bytes) from buffer */
354 if ((s->data_count) >= (s->blksize & 0x0fff)) {
355 DPRINT_L2("All %u bytes of data have been read from input buffer\n",
356 s->data_count);
357 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
358 s->data_count = 0; /* next buff read must start at position [0] */
359
360 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
361 s->blkcnt--;
362 }
363
364 /* if that was the last block of data */
365 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
366 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
367 /* stop at gap request */
368 (s->stopped_state == sdhc_gap_read &&
369 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
370 SDHCI_GET_CLASS(s)->end_data_transfer(s);
371 } else { /* if there are more data, read next block from card */
372 SDHCI_GET_CLASS(s)->read_block_from_card(s);
373 }
374 break;
375 }
376 }
377
378 return value;
379}
380
381/* Write data from host controller FIFO to card */
382static void sdhci_write_block_to_card(SDHCIState *s)
383{
384 int index = 0;
385
386 if (s->prnsts & SDHC_SPACE_AVAILABLE) {
387 if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
388 s->norintsts |= SDHC_NIS_WBUFRDY;
389 }
390 sdhci_update_irq(s);
391 return;
392 }
393
394 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
395 if (s->blkcnt == 0) {
396 return;
397 } else {
398 s->blkcnt--;
399 }
400 }
401
402 for (index = 0; index < (s->blksize & 0x0fff); index++) {
403 sd_write_data(s->card, s->fifo_buffer[index]);
404 }
405
406 /* Next data can be written through BUFFER DATORT register */
407 s->prnsts |= SDHC_SPACE_AVAILABLE;
d7dfca08
IM		 408
409 /* Finish transfer if that was the last block of data */
410 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
411 ((s->trnmod & SDHC_TRNS_MULTI) &&
412 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
413 SDHCI_GET_CLASS(s)->end_data_transfer(s);
dcdb4cd8
PC		 414 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
415 s->norintsts |= SDHC_NIS_WBUFRDY;
d7dfca08
IM		 416 }
417
418 /* Generate Block Gap Event if requested and if not the last block */
419 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
420 s->blkcnt > 0) {
421 s->prnsts &= ~SDHC_DOING_WRITE;
422 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
423 s->norintsts |= SDHC_EIS_BLKGAP;
424 }
425 SDHCI_GET_CLASS(s)->end_data_transfer(s);
426 }
427
428 sdhci_update_irq(s);
429}
430
431/* Write @size bytes of @value data to host controller @s Buffer Data Port
432 * register */
433static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
434{
435 unsigned i;
436
437 /* Check that there is free space left in a buffer */
438 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
439 ERRPRINT("Can't write to data buffer: buffer full\n");
440 return;
441 }
442
443 for (i = 0; i < size; i++) {
444 s->fifo_buffer[s->data_count] = value & 0xFF;
445 s->data_count++;
446 value >>= 8;
447 if (s->data_count >= (s->blksize & 0x0fff)) {
448 DPRINT_L2("write buffer filled with %u bytes of data\n",
449 s->data_count);
450 s->data_count = 0;
451 s->prnsts &= ~SDHC_SPACE_AVAILABLE;
452 if (s->prnsts & SDHC_DOING_WRITE) {
453 SDHCI_GET_CLASS(s)->write_block_to_card(s);
454 }
455 }
456 }
457}
458
459/*
460 * Single DMA data transfer
461 */
462
463/* Multi block SDMA transfer */
464static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
465{
466 bool page_aligned = false;
467 unsigned int n, begin;
468 const uint16_t block_size = s->blksize & 0x0fff;
469 uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12);
470 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
471
472 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
473 * possible stop at page boundary if initial address is not page aligned,
474 * allow them to work properly */
475 if ((s->sdmasysad % boundary_chk) == 0) {
476 page_aligned = true;
477 }
478
479 if (s->trnmod & SDHC_TRNS_READ) {
480 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
481 SDHC_DAT_LINE_ACTIVE;
482 while (s->blkcnt) {
483 if (s->data_count == 0) {
484 for (n = 0; n < block_size; n++) {
485 s->fifo_buffer[n] = sd_read_data(s->card);
486 }
487 }
488 begin = s->data_count;
489 if (((boundary_count + begin) < block_size) && page_aligned) {
490 s->data_count = boundary_count + begin;
491 boundary_count = 0;
492 } else {
493 s->data_count = block_size;
494 boundary_count -= block_size - begin;
495 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
496 s->blkcnt--;
497 }
498 }
df32fd1c 499 dma_memory_write(&address_space_memory, s->sdmasysad,
d7dfca08
IM		 500 &s->fifo_buffer[begin], s->data_count - begin);
501 s->sdmasysad += s->data_count - begin;
502 if (s->data_count == block_size) {
503 s->data_count = 0;
504 }
505 if (page_aligned && boundary_count == 0) {
506 break;
507 }
508 }
509 } else {
510 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT |
511 SDHC_DAT_LINE_ACTIVE;
512 while (s->blkcnt) {
513 begin = s->data_count;
514 if (((boundary_count + begin) < block_size) && page_aligned) {
515 s->data_count = boundary_count + begin;
516 boundary_count = 0;
517 } else {
518 s->data_count = block_size;
519 boundary_count -= block_size - begin;
520 }
df32fd1c 521 dma_memory_read(&address_space_memory, s->sdmasysad,
d7dfca08
IM		 522 &s->fifo_buffer[begin], s->data_count);
523 s->sdmasysad += s->data_count - begin;
524 if (s->data_count == block_size) {
525 for (n = 0; n < block_size; n++) {
526 sd_write_data(s->card, s->fifo_buffer[n]);
527 }
528 s->data_count = 0;
529 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
530 s->blkcnt--;
531 }
532 }
533 if (page_aligned && boundary_count == 0) {
534 break;
535 }
536 }
537 }
538
539 if (s->blkcnt == 0) {
540 SDHCI_GET_CLASS(s)->end_data_transfer(s);
541 } else {
542 if (s->norintstsen & SDHC_NISEN_DMA) {
543 s->norintsts |= SDHC_NIS_DMA;
544 }
545 sdhci_update_irq(s);
546 }
547}
548
549/* single block SDMA transfer */
550
551static void sdhci_sdma_transfer_single_block(SDHCIState *s)
552{
553 int n;
554 uint32_t datacnt = s->blksize & 0x0fff;
555
556 if (s->trnmod & SDHC_TRNS_READ) {
557 for (n = 0; n < datacnt; n++) {
558 s->fifo_buffer[n] = sd_read_data(s->card);
559 }
df32fd1c 560 dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer,
d7dfca08
IM		 561 datacnt);
562 } else {
df32fd1c 563 dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer,
d7dfca08
IM		 564 datacnt);
565 for (n = 0; n < datacnt; n++) {
566 sd_write_data(s->card, s->fifo_buffer[n]);
567 }
568 }
569
570 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
571 s->blkcnt--;
572 }
573
574 SDHCI_GET_CLASS(s)->end_data_transfer(s);
575}
576
577typedef struct ADMADescr {
578 hwaddr addr;
579 uint16_t length;
580 uint8_t attr;
581 uint8_t incr;
582} ADMADescr;
583
584static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
585{
586 uint32_t adma1 = 0;
587 uint64_t adma2 = 0;
588 hwaddr entry_addr = (hwaddr)s->admasysaddr;
589 switch (SDHC_DMA_TYPE(s->hostctl)) {
590 case SDHC_CTRL_ADMA2_32:
df32fd1c 591 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2,
d7dfca08
IM		 592 sizeof(adma2));
593 adma2 = le64_to_cpu(adma2);
594 /* The spec does not specify endianness of descriptor table.
595 * We currently assume that it is LE.
596 */
597 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
598 dscr->length = (uint16_t)extract64(adma2, 16, 16);
599 dscr->attr = (uint8_t)extract64(adma2, 0, 7);
600 dscr->incr = 8;
601 break;
602 case SDHC_CTRL_ADMA1_32:
df32fd1c 603 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1,
d7dfca08
IM		 604 sizeof(adma1));
605 adma1 = le32_to_cpu(adma1);
606 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
607 dscr->attr = (uint8_t)extract32(adma1, 0, 7);
608 dscr->incr = 4;
609 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
610 dscr->length = (uint16_t)extract32(adma1, 12, 16);
611 } else {
612 dscr->length = 4096;
613 }
614 break;
615 case SDHC_CTRL_ADMA2_64:
df32fd1c 616 dma_memory_read(&address_space_memory, entry_addr,
d7dfca08 617 (uint8_t *)(&dscr->attr), 1);
df32fd1c 618 dma_memory_read(&address_space_memory, entry_addr + 2,
d7dfca08
IM		 619 (uint8_t *)(&dscr->length), 2);
620 dscr->length = le16_to_cpu(dscr->length);
df32fd1c 621 dma_memory_read(&address_space_memory, entry_addr + 4,
d7dfca08
IM		 622 (uint8_t *)(&dscr->addr), 8);
623 dscr->attr = le64_to_cpu(dscr->attr);
624 dscr->attr &= 0xfffffff8;
625 dscr->incr = 12;
626 break;
627 }
628}
629
630/* Advanced DMA data transfer */
631
632static void sdhci_do_adma(SDHCIState *s)
633{
634 unsigned int n, begin, length;
635 const uint16_t block_size = s->blksize & 0x0fff;
636 ADMADescr dscr;
637 int i;
638
639 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
640 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
641
642 get_adma_description(s, &dscr);
643 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n",
644 dscr.addr, dscr.length, dscr.attr);
645
646 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
647 /* Indicate that error occurred in ST_FDS state */
648 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
649 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS;
650
651 /* Generate ADMA error interrupt */
652 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
653 s->errintsts |= SDHC_EIS_ADMAERR;
654 s->norintsts |= SDHC_NIS_ERR;
655 }
656
657 sdhci_update_irq(s);
658 return;
659 }
660
661 length = dscr.length ? dscr.length : 65536;
662
663 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
664 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
665
666 if (s->trnmod & SDHC_TRNS_READ) {
667 while (length) {
668 if (s->data_count == 0) {
669 for (n = 0; n < block_size; n++) {
670 s->fifo_buffer[n] = sd_read_data(s->card);
671 }
672 }
673 begin = s->data_count;
674 if ((length + begin) < block_size) {
675 s->data_count = length + begin;
676 length = 0;
677 } else {
678 s->data_count = block_size;
679 length -= block_size - begin;
680 }
df32fd1c 681 dma_memory_write(&address_space_memory, dscr.addr,
d7dfca08
IM		 682 &s->fifo_buffer[begin],
683 s->data_count - begin);
684 dscr.addr += s->data_count - begin;
685 if (s->data_count == block_size) {
686 s->data_count = 0;
687 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
688 s->blkcnt--;
689 if (s->blkcnt == 0) {
690 break;
691 }
692 }
693 }
694 }
695 } else {
696 while (length) {
697 begin = s->data_count;
698 if ((length + begin) < block_size) {
699 s->data_count = length + begin;
700 length = 0;
701 } else {
702 s->data_count = block_size;
703 length -= block_size - begin;
704 }
df32fd1c 705 dma_memory_read(&address_space_memory, dscr.addr,
d7dfca08
IM		 706 &s->fifo_buffer[begin], s->data_count);
707 dscr.addr += s->data_count - begin;
708 if (s->data_count == block_size) {
709 for (n = 0; n < block_size; n++) {
710 sd_write_data(s->card, s->fifo_buffer[n]);
711 }
712 s->data_count = 0;
713 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
714 s->blkcnt--;
715 if (s->blkcnt == 0) {
716 break;
717 }
718 }
719 }
720 }
721 }
722 s->admasysaddr += dscr.incr;
723 break;
724 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
725 s->admasysaddr = dscr.addr;
726 DPRINT_L1("ADMA link: admasysaddr=0x%lx\n", s->admasysaddr);
727 break;
728 default:
729 s->admasysaddr += dscr.incr;
730 break;
731 }
732
1d32c26f
PC		 733 if (dscr.attr & SDHC_ADMA_ATTR_INT) {
734 DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr);
735 if (s->norintstsen & SDHC_NISEN_DMA) {
736 s->norintsts |= SDHC_NIS_DMA;
737 }
738
739 sdhci_update_irq(s);
740 }
741
d7dfca08
IM		 742 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
743 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
744 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
745 DPRINT_L2("ADMA transfer completed\n");
746 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
747 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
748 s->blkcnt != 0)) {
749 ERRPRINT("SD/MMC host ADMA length mismatch\n");
750 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
751 SDHC_ADMAERR_STATE_ST_TFR;
752 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
753 ERRPRINT("Set ADMA error flag\n");
754 s->errintsts |= SDHC_EIS_ADMAERR;
755 s->norintsts |= SDHC_NIS_ERR;
756 }
757
758 sdhci_update_irq(s);
759 }
760 SDHCI_GET_CLASS(s)->end_data_transfer(s);
761 return;
762 }
763
d7dfca08
IM		 764 }
765
085d8134 766 /* we have unfinished business - reschedule to continue ADMA */
d7dfca08
IM		 767 qemu_mod_timer(s->transfer_timer,
768 qemu_get_clock_ns(vm_clock) + SDHC_TRANSFER_DELAY);
769}
770
771/* Perform data transfer according to controller configuration */
772
773static void sdhci_data_transfer(SDHCIState *s)
774{
775 SDHCIClass *k = SDHCI_GET_CLASS(s);
d7dfca08
IM		 776
777 if (s->trnmod & SDHC_TRNS_DMA) {
778 switch (SDHC_DMA_TYPE(s->hostctl)) {
779 case SDHC_CTRL_SDMA:
780 if ((s->trnmod & SDHC_TRNS_MULTI) &&
781 (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) {
782 break;
783 }
784
785 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
786 k->do_sdma_single(s);
787 } else {
788 k->do_sdma_multi(s);
789 }
790
791 break;
792 case SDHC_CTRL_ADMA1_32:
793 if (!(s->capareg & SDHC_CAN_DO_ADMA1)) {
794 ERRPRINT("ADMA1 not supported\n");
795 break;
796 }
797
798 k->do_adma(s);
799 break;
800 case SDHC_CTRL_ADMA2_32:
801 if (!(s->capareg & SDHC_CAN_DO_ADMA2)) {
802 ERRPRINT("ADMA2 not supported\n");
803 break;
804 }
805
806 k->do_adma(s);
807 break;
808 case SDHC_CTRL_ADMA2_64:
809 if (!(s->capareg & SDHC_CAN_DO_ADMA2) ||
810 !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) {
811 ERRPRINT("64 bit ADMA not supported\n");
812 break;
813 }
814
815 k->do_adma(s);
816 break;
817 default:
818 ERRPRINT("Unsupported DMA type\n");
819 break;
820 }
821 } else {
822 if ((s->trnmod & SDHC_TRNS_READ) && sd_data_ready(s->card)) {
823 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
824 SDHC_DAT_LINE_ACTIVE;
825 SDHCI_GET_CLASS(s)->read_block_from_card(s);
826 } else {
827 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE |
828 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT;
829 SDHCI_GET_CLASS(s)->write_block_to_card(s);
830 }
831 }
832}
833
834static bool sdhci_can_issue_command(SDHCIState *s)
835{
836 if (!SDHC_CLOCK_IS_ON(s->clkcon) || !(s->pwrcon & SDHC_POWER_ON) ||
837 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) &&
838 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) ||
839 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
840 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
841 return false;
842 }
843
844 return true;
845}
846
847/* The Buffer Data Port register must be accessed in sequential and
848 * continuous manner */
849static inline bool
850sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
851{
852 if ((s->data_count & 0x3) != byte_num) {
853 ERRPRINT("Non-sequential access to Buffer Data Port register"
854 "is prohibited\n");
855 return false;
856 }
857 return true;
858}
859
860static uint32_t sdhci_read(SDHCIState *s, unsigned int offset, unsigned size)
861{
862 uint32_t ret = 0;
863
864 switch (offset & ~0x3) {
865 case SDHC_SYSAD:
866 ret = s->sdmasysad;
867 break;
868 case SDHC_BLKSIZE:
869 ret = s->blksize | (s->blkcnt << 16);
870 break;
871 case SDHC_ARGUMENT:
872 ret = s->argument;
873 break;
874 case SDHC_TRNMOD:
875 ret = s->trnmod | (s->cmdreg << 16);
876 break;
877 case SDHC_RSPREG0 ... SDHC_RSPREG3:
878 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
879 break;
880 case SDHC_BDATA:
881 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
882 ret = SDHCI_GET_CLASS(s)->bdata_read(s, size);
677ff2ae
PC		 883 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, offset,
884 ret, ret);
d7dfca08
IM		 885 return ret;
886 }
887 break;
888 case SDHC_PRNSTS:
889 ret = s->prnsts;
890 break;
891 case SDHC_HOSTCTL:
892 ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) |
893 (s->wakcon << 24);
894 break;
895 case SDHC_CLKCON:
896 ret = s->clkcon | (s->timeoutcon << 16);
897 break;
898 case SDHC_NORINTSTS:
899 ret = s->norintsts | (s->errintsts << 16);
900 break;
901 case SDHC_NORINTSTSEN:
902 ret = s->norintstsen | (s->errintstsen << 16);
903 break;
904 case SDHC_NORINTSIGEN:
905 ret = s->norintsigen | (s->errintsigen << 16);
906 break;
907 case SDHC_ACMD12ERRSTS:
908 ret = s->acmd12errsts;
909 break;
910 case SDHC_CAPAREG:
911 ret = s->capareg;
912 break;
913 case SDHC_MAXCURR:
914 ret = s->maxcurr;
915 break;
916 case SDHC_ADMAERR:
917 ret = s->admaerr;
918 break;
919 case SDHC_ADMASYSADDR:
920 ret = (uint32_t)s->admasysaddr;
921 break;
922 case SDHC_ADMASYSADDR + 4:
923 ret = (uint32_t)(s->admasysaddr >> 32);
924 break;
925 case SDHC_SLOT_INT_STATUS:
926 ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
927 break;
928 default:
929 ERRPRINT("bad %ub read: addr[0x%04x]\n", size, offset);
930 break;
931 }
932
933 ret >>= (offset & 0x3) * 8;
934 ret &= (1ULL << (size * 8)) - 1;
935 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, offset, ret, ret);
936 return ret;
937}
938
939static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
940{
941 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
942 return;
943 }
944 s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
945
946 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
947 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
948 if (s->stopped_state == sdhc_gap_read) {
949 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ;
950 SDHCI_GET_CLASS(s)->read_block_from_card(s);
951 } else {
952 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE;
953 SDHCI_GET_CLASS(s)->write_block_to_card(s);
954 }
955 s->stopped_state = sdhc_not_stopped;
956 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
957 if (s->prnsts & SDHC_DOING_READ) {
958 s->stopped_state = sdhc_gap_read;
959 } else if (s->prnsts & SDHC_DOING_WRITE) {
960 s->stopped_state = sdhc_gap_write;
961 }
962 }
963}
964
965static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
966{
967 switch (value) {
968 case SDHC_RESET_ALL:
969 DEVICE_GET_CLASS(s)->reset(DEVICE(s));
970 break;
971 case SDHC_RESET_CMD:
972 s->prnsts &= ~SDHC_CMD_INHIBIT;
973 s->norintsts &= ~SDHC_NIS_CMDCMP;
974 break;
975 case SDHC_RESET_DATA:
976 s->data_count = 0;
977 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE |
978 SDHC_DOING_READ | SDHC_DOING_WRITE |
979 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
980 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
981 s->stopped_state = sdhc_not_stopped;
982 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
983 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
984 break;
985 }
986}
987
988static void
989sdhci_write(SDHCIState *s, unsigned int offset, uint32_t value, unsigned size)
990{
991 unsigned shift = 8 * (offset & 0x3);
992 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
993 value <<= shift;
994
995 switch (offset & ~0x3) {
996 case SDHC_SYSAD:
997 s->sdmasysad = (s->sdmasysad & mask) | value;
998 MASKED_WRITE(s->sdmasysad, mask, value);
999 /* Writing to last byte of sdmasysad might trigger transfer */
1000 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
1001 s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
1002 SDHCI_GET_CLASS(s)->do_sdma_multi(s);
1003 }
1004 break;
1005 case SDHC_BLKSIZE:
1006 if (!TRANSFERRING_DATA(s->prnsts)) {
1007 MASKED_WRITE(s->blksize, mask, value);
1008 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
1009 }
1010 break;
1011 case SDHC_ARGUMENT:
1012 MASKED_WRITE(s->argument, mask, value);
1013 break;
1014 case SDHC_TRNMOD:
1015 /* DMA can be enabled only if it is supported as indicated by
1016 * capabilities register */
1017 if (!(s->capareg & SDHC_CAN_DO_DMA)) {
1018 value &= ~SDHC_TRNS_DMA;
1019 }
1020 MASKED_WRITE(s->trnmod, mask, value);
1021 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1022
1023 /* Writing to the upper byte of CMDREG triggers SD command generation */
1024 if ((mask & 0xFF000000) || !SDHCI_GET_CLASS(s)->can_issue_command(s)) {
1025 break;
1026 }
1027
1028 SDHCI_GET_CLASS(s)->send_command(s);
1029 break;
1030 case SDHC_BDATA:
1031 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
1032 SDHCI_GET_CLASS(s)->bdata_write(s, value >> shift, size);
1033 }
1034 break;
1035 case SDHC_HOSTCTL:
1036 if (!(mask & 0xFF0000)) {
1037 sdhci_blkgap_write(s, value >> 16);
1038 }
1039 MASKED_WRITE(s->hostctl, mask, value);
1040 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1041 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1042 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
1043 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1044 s->pwrcon &= ~SDHC_POWER_ON;
1045 }
1046 break;
1047 case SDHC_CLKCON:
1048 if (!(mask & 0xFF000000)) {
1049 sdhci_reset_write(s, value >> 24);
1050 }
1051 MASKED_WRITE(s->clkcon, mask, value);
1052 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1053 if (s->clkcon & SDHC_CLOCK_INT_EN) {
1054 s->clkcon |= SDHC_CLOCK_INT_STABLE;
1055 } else {
1056 s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1057 }
1058 break;
1059 case SDHC_NORINTSTS:
1060 if (s->norintstsen & SDHC_NISEN_CARDINT) {
1061 value &= ~SDHC_NIS_CARDINT;
1062 }
1063 s->norintsts &= mask | ~value;
1064 s->errintsts &= (mask >> 16) | ~(value >> 16);
1065 if (s->errintsts) {
1066 s->norintsts |= SDHC_NIS_ERR;
1067 } else {
1068 s->norintsts &= ~SDHC_NIS_ERR;
1069 }
1070 sdhci_update_irq(s);
1071 break;
1072 case SDHC_NORINTSTSEN:
1073 MASKED_WRITE(s->norintstsen, mask, value);
1074 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1075 s->norintsts &= s->norintstsen;
1076 s->errintsts &= s->errintstsen;
1077 if (s->errintsts) {
1078 s->norintsts |= SDHC_NIS_ERR;
1079 } else {
1080 s->norintsts &= ~SDHC_NIS_ERR;
1081 }
1082 sdhci_update_irq(s);
1083 break;
1084 case SDHC_NORINTSIGEN:
1085 MASKED_WRITE(s->norintsigen, mask, value);
1086 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1087 sdhci_update_irq(s);
1088 break;
1089 case SDHC_ADMAERR:
1090 MASKED_WRITE(s->admaerr, mask, value);
1091 break;
1092 case SDHC_ADMASYSADDR:
1093 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
1094 (uint64_t)mask)) | (uint64_t)value;
1095 break;
1096 case SDHC_ADMASYSADDR + 4:
1097 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
1098 ((uint64_t)mask << 32))) | ((uint64_t)value << 32);
1099 break;
1100 case SDHC_FEAER:
1101 s->acmd12errsts |= value;
1102 s->errintsts |= (value >> 16) & s->errintstsen;
1103 if (s->acmd12errsts) {
1104 s->errintsts |= SDHC_EIS_CMD12ERR;
1105 }
1106 if (s->errintsts) {
1107 s->norintsts |= SDHC_NIS_ERR;
1108 }
1109 sdhci_update_irq(s);
1110 break;
1111 default:
1112 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
1113 size, offset, value >> shift, value >> shift);
1114 break;
1115 }
1116 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
1117 size, offset, value >> shift, value >> shift);
1118}
1119
1120static uint64_t
1121sdhci_readfn(void *opaque, hwaddr offset, unsigned size)
1122{
1123 SDHCIState *s = (SDHCIState *)opaque;
1124
1125 return SDHCI_GET_CLASS(s)->mem_read(s, offset, size);
1126}
1127
1128static void
1129sdhci_writefn(void *opaque, hwaddr off, uint64_t val, unsigned sz)
1130{
1131 SDHCIState *s = (SDHCIState *)opaque;
1132
1133 SDHCI_GET_CLASS(s)->mem_write(s, off, val, sz);
1134}
1135
1136static const MemoryRegionOps sdhci_mmio_ops = {
1137 .read = sdhci_readfn,
1138 .write = sdhci_writefn,
1139 .valid = {
1140 .min_access_size = 1,
1141 .max_access_size = 4,
1142 .unaligned = false
1143 },
1144 .endianness = DEVICE_LITTLE_ENDIAN,
1145};
1146
1147static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
1148{
1149 switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) {
1150 case 0:
1151 return 512;
1152 case 1:
1153 return 1024;
1154 case 2:
1155 return 2048;
1156 default:
1157 hw_error("SDHC: unsupported value for maximum block size\n");
1158 return 0;
1159 }
1160}
1161
1162static void sdhci_initfn(Object *obj)
1163{
1164 SDHCIState *s = SDHCI(obj);
1165 DriveInfo *di;
1166
1167 di = drive_get_next(IF_SD);
6790f59d 1168 s->card = sd_init(di ? di->bdrv : NULL, false);
d7dfca08
IM		 1169 s->eject_cb = qemu_allocate_irqs(sdhci_insert_eject_cb, s, 1)[0];
1170 s->ro_cb = qemu_allocate_irqs(sdhci_card_readonly_cb, s, 1)[0];
1171 sd_set_cb(s->card, s->ro_cb, s->eject_cb);
1172
1173 s->insert_timer = qemu_new_timer_ns(vm_clock, sdhci_raise_insertion_irq, s);
1174 s->transfer_timer = qemu_new_timer_ns(vm_clock, sdhci_do_data_transfer, s);
1175}
1176
1177static void sdhci_uninitfn(Object *obj)
1178{
1179 SDHCIState *s = SDHCI(obj);
1180
1181 qemu_del_timer(s->insert_timer);
1182 qemu_free_timer(s->insert_timer);
1183 qemu_del_timer(s->transfer_timer);
1184 qemu_free_timer(s->transfer_timer);
1185 qemu_free_irqs(&s->eject_cb);
1186 qemu_free_irqs(&s->ro_cb);
1187
1188 if (s->fifo_buffer) {
1189 g_free(s->fifo_buffer);
1190 s->fifo_buffer = NULL;
1191 }
1192}
1193
1194const VMStateDescription sdhci_vmstate = {
1195 .name = "sdhci",
1196 .version_id = 1,
1197 .minimum_version_id = 1,
1198 .fields = (VMStateField[]) {
1199 VMSTATE_UINT32(sdmasysad, SDHCIState),
1200 VMSTATE_UINT16(blksize, SDHCIState),
1201 VMSTATE_UINT16(blkcnt, SDHCIState),
1202 VMSTATE_UINT32(argument, SDHCIState),
1203 VMSTATE_UINT16(trnmod, SDHCIState),
1204 VMSTATE_UINT16(cmdreg, SDHCIState),
1205 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1206 VMSTATE_UINT32(prnsts, SDHCIState),
1207 VMSTATE_UINT8(hostctl, SDHCIState),
1208 VMSTATE_UINT8(pwrcon, SDHCIState),
1209 VMSTATE_UINT8(blkgap, SDHCIState),
1210 VMSTATE_UINT8(wakcon, SDHCIState),
1211 VMSTATE_UINT16(clkcon, SDHCIState),
1212 VMSTATE_UINT8(timeoutcon, SDHCIState),
1213 VMSTATE_UINT8(admaerr, SDHCIState),
1214 VMSTATE_UINT16(norintsts, SDHCIState),
1215 VMSTATE_UINT16(errintsts, SDHCIState),
1216 VMSTATE_UINT16(norintstsen, SDHCIState),
1217 VMSTATE_UINT16(errintstsen, SDHCIState),
1218 VMSTATE_UINT16(norintsigen, SDHCIState),
1219 VMSTATE_UINT16(errintsigen, SDHCIState),
1220 VMSTATE_UINT16(acmd12errsts, SDHCIState),
1221 VMSTATE_UINT16(data_count, SDHCIState),
1222 VMSTATE_UINT64(admasysaddr, SDHCIState),
1223 VMSTATE_UINT8(stopped_state, SDHCIState),
1224 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz),
1225 VMSTATE_TIMER(insert_timer, SDHCIState),
1226 VMSTATE_TIMER(transfer_timer, SDHCIState),
1227 VMSTATE_END_OF_LIST()
1228 }
1229};
1230
1231/* Capabilities registers provide information on supported features of this
1232 * specific host controller implementation */
1233static Property sdhci_properties[] = {
1234 DEFINE_PROP_HEX32("capareg", SDHCIState, capareg,
1235 SDHC_CAPAB_REG_DEFAULT),
1236 DEFINE_PROP_HEX32("maxcurr", SDHCIState, maxcurr, 0),
1237 DEFINE_PROP_END_OF_LIST(),
1238};
1239
1240static void sdhci_realize(DeviceState *dev, Error ** errp)
1241{
1242 SDHCIState *s = SDHCI(dev);
1243 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1244
1245 s->buf_maxsz = sdhci_get_fifolen(s);
1246 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1247 sysbus_init_irq(sbd, &s->irq);
29776739 1248 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
d7dfca08
IM		 1249 SDHC_REGISTERS_MAP_SIZE);
1250 sysbus_init_mmio(sbd, &s->iomem);
1251}
1252
1253static void sdhci_generic_reset(DeviceState *ds)
1254{
1255 SDHCIState *s = SDHCI(ds);
1256 SDHCI_GET_CLASS(s)->reset(s);
1257}
1258
1259static void sdhci_class_init(ObjectClass *klass, void *data)
1260{
1261 DeviceClass *dc = DEVICE_CLASS(klass);
1262 SDHCIClass *k = SDHCI_CLASS(klass);
1263
1264 dc->vmsd = &sdhci_vmstate;
1265 dc->props = sdhci_properties;
1266 dc->reset = sdhci_generic_reset;
1267 dc->realize = sdhci_realize;
1268
1269 k->reset = sdhci_reset;
1270 k->mem_read = sdhci_read;
1271 k->mem_write = sdhci_write;
1272 k->send_command = sdhci_send_command;
1273 k->can_issue_command = sdhci_can_issue_command;
1274 k->data_transfer = sdhci_data_transfer;
1275 k->end_data_transfer = sdhci_end_transfer;
1276 k->do_sdma_single = sdhci_sdma_transfer_single_block;
1277 k->do_sdma_multi = sdhci_sdma_transfer_multi_blocks;
1278 k->do_adma = sdhci_do_adma;
1279 k->read_block_from_card = sdhci_read_block_from_card;
1280 k->write_block_to_card = sdhci_write_block_to_card;
1281 k->bdata_read = sdhci_read_dataport;
1282 k->bdata_write = sdhci_write_dataport;
1283}
1284
1285static const TypeInfo sdhci_type_info = {
1286 .name = TYPE_SDHCI,
1287 .parent = TYPE_SYS_BUS_DEVICE,
1288 .instance_size = sizeof(SDHCIState),
1289 .instance_init = sdhci_initfn,
1290 .instance_finalize = sdhci_uninitfn,
1291 .class_init = sdhci_class_init,
1292 .class_size = sizeof(SDHCIClass)
1293};
1294
1295static void sdhci_register_types(void)
1296{
1297 type_register_static(&sdhci_type_info);
1298}
1299
1300type_init(sdhci_register_types)
Qemu copy for testing