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80cabfad FB |
1 | /* |
2 | * QEMU 16450 UART emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
80cabfad FB |
24 | #include "vl.h" |
25 | ||
26 | //#define DEBUG_SERIAL | |
27 | ||
28 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
29 | ||
30 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
31 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
32 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
33 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
34 | ||
35 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
36 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
37 | ||
38 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
39 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
40 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
41 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
42 | ||
43 | /* | |
44 | * These are the definitions for the Modem Control Register | |
45 | */ | |
46 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
47 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
48 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
49 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
50 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
51 | ||
52 | /* | |
53 | * These are the definitions for the Modem Status Register | |
54 | */ | |
55 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
56 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
57 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
58 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
59 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
60 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
61 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
62 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
63 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
64 | ||
65 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
66 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
67 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
68 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
69 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
70 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
71 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
72 | ||
b41a2cd1 | 73 | struct SerialState { |
80cabfad FB |
74 | uint8_t divider; |
75 | uint8_t rbr; /* receive register */ | |
76 | uint8_t ier; | |
77 | uint8_t iir; /* read only */ | |
78 | uint8_t lcr; | |
79 | uint8_t mcr; | |
80 | uint8_t lsr; /* read only */ | |
81 | uint8_t msr; | |
82 | uint8_t scr; | |
83 | /* NOTE: this hidden state is necessary for tx irq generation as | |
84 | it can be reset while reading iir */ | |
85 | int thr_ipending; | |
86 | int irq; | |
b41a2cd1 FB |
87 | int out_fd; |
88 | }; | |
80cabfad | 89 | |
b41a2cd1 | 90 | static void serial_update_irq(SerialState *s) |
80cabfad | 91 | { |
80cabfad FB |
92 | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) { |
93 | s->iir = UART_IIR_RDI; | |
94 | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { | |
95 | s->iir = UART_IIR_THRI; | |
96 | } else { | |
97 | s->iir = UART_IIR_NO_INT; | |
98 | } | |
99 | if (s->iir != UART_IIR_NO_INT) { | |
100 | pic_set_irq(s->irq, 1); | |
101 | } else { | |
102 | pic_set_irq(s->irq, 0); | |
103 | } | |
104 | } | |
105 | ||
b41a2cd1 | 106 | static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 107 | { |
b41a2cd1 | 108 | SerialState *s = opaque; |
80cabfad FB |
109 | unsigned char ch; |
110 | int ret; | |
111 | ||
112 | addr &= 7; | |
113 | #ifdef DEBUG_SERIAL | |
114 | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val); | |
115 | #endif | |
116 | switch(addr) { | |
117 | default: | |
118 | case 0: | |
119 | if (s->lcr & UART_LCR_DLAB) { | |
120 | s->divider = (s->divider & 0xff00) | val; | |
121 | } else { | |
122 | s->thr_ipending = 0; | |
123 | s->lsr &= ~UART_LSR_THRE; | |
b41a2cd1 | 124 | serial_update_irq(s); |
80cabfad | 125 | |
52302d72 FB |
126 | if (s->out_fd >= 0) { |
127 | ch = val; | |
128 | do { | |
129 | ret = write(s->out_fd, &ch, 1); | |
130 | } while (ret != 1); | |
131 | } | |
80cabfad FB |
132 | s->thr_ipending = 1; |
133 | s->lsr |= UART_LSR_THRE; | |
134 | s->lsr |= UART_LSR_TEMT; | |
b41a2cd1 | 135 | serial_update_irq(s); |
80cabfad FB |
136 | } |
137 | break; | |
138 | case 1: | |
139 | if (s->lcr & UART_LCR_DLAB) { | |
140 | s->divider = (s->divider & 0x00ff) | (val << 8); | |
141 | } else { | |
142 | s->ier = val; | |
b41a2cd1 | 143 | serial_update_irq(s); |
80cabfad FB |
144 | } |
145 | break; | |
146 | case 2: | |
147 | break; | |
148 | case 3: | |
149 | s->lcr = val; | |
150 | break; | |
151 | case 4: | |
152 | s->mcr = val; | |
153 | break; | |
154 | case 5: | |
155 | break; | |
156 | case 6: | |
157 | s->msr = val; | |
158 | break; | |
159 | case 7: | |
160 | s->scr = val; | |
161 | break; | |
162 | } | |
163 | } | |
164 | ||
b41a2cd1 | 165 | static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
80cabfad | 166 | { |
b41a2cd1 | 167 | SerialState *s = opaque; |
80cabfad FB |
168 | uint32_t ret; |
169 | ||
170 | addr &= 7; | |
171 | switch(addr) { | |
172 | default: | |
173 | case 0: | |
174 | if (s->lcr & UART_LCR_DLAB) { | |
175 | ret = s->divider & 0xff; | |
176 | } else { | |
177 | ret = s->rbr; | |
178 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
b41a2cd1 | 179 | serial_update_irq(s); |
80cabfad FB |
180 | } |
181 | break; | |
182 | case 1: | |
183 | if (s->lcr & UART_LCR_DLAB) { | |
184 | ret = (s->divider >> 8) & 0xff; | |
185 | } else { | |
186 | ret = s->ier; | |
187 | } | |
188 | break; | |
189 | case 2: | |
190 | ret = s->iir; | |
191 | /* reset THR pending bit */ | |
192 | if ((ret & 0x7) == UART_IIR_THRI) | |
193 | s->thr_ipending = 0; | |
b41a2cd1 | 194 | serial_update_irq(s); |
80cabfad FB |
195 | break; |
196 | case 3: | |
197 | ret = s->lcr; | |
198 | break; | |
199 | case 4: | |
200 | ret = s->mcr; | |
201 | break; | |
202 | case 5: | |
203 | ret = s->lsr; | |
204 | break; | |
205 | case 6: | |
206 | if (s->mcr & UART_MCR_LOOP) { | |
207 | /* in loopback, the modem output pins are connected to the | |
208 | inputs */ | |
209 | ret = (s->mcr & 0x0c) << 4; | |
210 | ret |= (s->mcr & 0x02) << 3; | |
211 | ret |= (s->mcr & 0x01) << 5; | |
212 | } else { | |
213 | ret = s->msr; | |
214 | } | |
215 | break; | |
216 | case 7: | |
217 | ret = s->scr; | |
218 | break; | |
219 | } | |
220 | #ifdef DEBUG_SERIAL | |
221 | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret); | |
222 | #endif | |
223 | return ret; | |
224 | } | |
225 | ||
b41a2cd1 | 226 | int serial_can_receive(SerialState *s) |
80cabfad | 227 | { |
80cabfad FB |
228 | return !(s->lsr & UART_LSR_DR); |
229 | } | |
230 | ||
b41a2cd1 | 231 | void serial_receive_byte(SerialState *s, int ch) |
80cabfad | 232 | { |
80cabfad FB |
233 | s->rbr = ch; |
234 | s->lsr |= UART_LSR_DR; | |
b41a2cd1 | 235 | serial_update_irq(s); |
80cabfad FB |
236 | } |
237 | ||
b41a2cd1 | 238 | void serial_receive_break(SerialState *s) |
80cabfad | 239 | { |
80cabfad FB |
240 | s->rbr = 0; |
241 | s->lsr |= UART_LSR_BI | UART_LSR_DR; | |
b41a2cd1 | 242 | serial_update_irq(s); |
80cabfad FB |
243 | } |
244 | ||
b41a2cd1 | 245 | static int serial_can_receive1(void *opaque) |
80cabfad | 246 | { |
b41a2cd1 FB |
247 | SerialState *s = opaque; |
248 | return serial_can_receive(s); | |
249 | } | |
250 | ||
251 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) | |
252 | { | |
253 | SerialState *s = opaque; | |
254 | serial_receive_byte(s, buf[0]); | |
255 | } | |
80cabfad | 256 | |
b41a2cd1 FB |
257 | /* If fd is zero, it means that the serial device uses the console */ |
258 | SerialState *serial_init(int base, int irq, int fd) | |
259 | { | |
260 | SerialState *s; | |
261 | ||
262 | s = qemu_mallocz(sizeof(SerialState)); | |
263 | if (!s) | |
264 | return NULL; | |
80cabfad FB |
265 | s->irq = irq; |
266 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; | |
267 | s->iir = UART_IIR_NO_INT; | |
b41a2cd1 FB |
268 | |
269 | register_ioport_write(base, 8, 1, serial_ioport_write, s); | |
270 | register_ioport_read(base, 8, 1, serial_ioport_read, s); | |
271 | ||
52302d72 FB |
272 | if (fd < 0) { |
273 | /* no associated device */ | |
274 | s->out_fd = -1; | |
275 | } else if (fd != 0) { | |
b0a21b53 | 276 | qemu_add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s); |
b41a2cd1 FB |
277 | s->out_fd = fd; |
278 | } else { | |
279 | serial_console = s; | |
280 | s->out_fd = 1; | |
281 | } | |
282 | return s; | |
80cabfad | 283 | } |