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Commit | Line | Data |
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80cabfad | 1 | /* |
81174dae | 2 | * QEMU 16550A UART emulation |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
81174dae | 5 | * Copyright (c) 2008 Citrix Systems, Inc. |
5fafdf24 | 6 | * |
80cabfad FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
87ecb68b PB |
25 | #include "hw.h" |
26 | #include "qemu-char.h" | |
27 | #include "isa.h" | |
28 | #include "pc.h" | |
6936bfe5 | 29 | #include "qemu-timer.h" |
666daa68 | 30 | #include "sysemu.h" |
80cabfad FB |
31 | |
32 | //#define DEBUG_SERIAL | |
33 | ||
34 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
35 | ||
36 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
37 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
38 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
39 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
40 | ||
41 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
42 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
43 | ||
44 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
45 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
46 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
47 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
81174dae AL |
48 | #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
49 | ||
50 | #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ | |
51 | #define UART_IIR_FE 0xC0 /* Fifo enabled */ | |
80cabfad FB |
52 | |
53 | /* | |
54 | * These are the definitions for the Modem Control Register | |
55 | */ | |
56 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
57 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
58 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
59 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
60 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
61 | ||
62 | /* | |
63 | * These are the definitions for the Modem Status Register | |
64 | */ | |
65 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
66 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
67 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
68 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
69 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
70 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
71 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
72 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
73 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
74 | ||
75 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
76 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
77 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
78 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
79 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
80 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
81 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
81174dae | 82 | #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
80cabfad | 83 | |
81174dae AL |
84 | /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */ |
85 | ||
86 | #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ | |
87 | #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ | |
88 | #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ | |
89 | #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ | |
90 | ||
91 | #define UART_FCR_DMS 0x08 /* DMA Mode Select */ | |
92 | #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ | |
93 | #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ | |
94 | #define UART_FCR_FE 0x01 /* FIFO Enable */ | |
95 | ||
96 | #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */ | |
97 | ||
98 | #define XMIT_FIFO 0 | |
99 | #define RECV_FIFO 1 | |
100 | #define MAX_XMIT_RETRY 4 | |
101 | ||
b6601141 MN |
102 | #ifdef DEBUG_SERIAL |
103 | #define DPRINTF(fmt, ...) \ | |
46411f86 | 104 | do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) |
b6601141 MN |
105 | #else |
106 | #define DPRINTF(fmt, ...) \ | |
46411f86 | 107 | do {} while (0) |
b6601141 MN |
108 | #endif |
109 | ||
2b321d69 | 110 | typedef struct SerialFIFO { |
81174dae AL |
111 | uint8_t data[UART_FIFO_LENGTH]; |
112 | uint8_t count; | |
113 | uint8_t itl; /* Interrupt Trigger Level */ | |
114 | uint8_t tail; | |
115 | uint8_t head; | |
2b321d69 | 116 | } SerialFIFO; |
6936bfe5 | 117 | |
b41a2cd1 | 118 | struct SerialState { |
508d92d0 | 119 | uint16_t divider; |
80cabfad | 120 | uint8_t rbr; /* receive register */ |
81174dae AL |
121 | uint8_t thr; /* transmit holding register */ |
122 | uint8_t tsr; /* transmit shift register */ | |
80cabfad FB |
123 | uint8_t ier; |
124 | uint8_t iir; /* read only */ | |
125 | uint8_t lcr; | |
126 | uint8_t mcr; | |
127 | uint8_t lsr; /* read only */ | |
3e749fe1 | 128 | uint8_t msr; /* read only */ |
80cabfad | 129 | uint8_t scr; |
81174dae | 130 | uint8_t fcr; |
747791f1 JQ |
131 | uint8_t fcr_vmstate; /* we can't write directly this value |
132 | it has side effects */ | |
80cabfad FB |
133 | /* NOTE: this hidden state is necessary for tx irq generation as |
134 | it can be reset while reading iir */ | |
135 | int thr_ipending; | |
d537cf6c | 136 | qemu_irq irq; |
82c643ff | 137 | CharDriverState *chr; |
f8d179e3 | 138 | int last_break_enable; |
e5d13e2f | 139 | int it_shift; |
b6cd0ea1 | 140 | int baudbase; |
81174dae | 141 | int tsr_retry; |
9826fd59 | 142 | uint32_t wakeup; |
81174dae AL |
143 | |
144 | uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */ | |
145 | SerialFIFO recv_fifo; | |
146 | SerialFIFO xmit_fifo; | |
147 | ||
148 | struct QEMUTimer *fifo_timeout_timer; | |
149 | int timeout_ipending; /* timeout interrupt pending state */ | |
150 | struct QEMUTimer *transmit_timer; | |
151 | ||
152 | ||
153 | uint64_t char_transmit_time; /* time to transmit a char in ticks*/ | |
154 | int poll_msl; | |
155 | ||
156 | struct QEMUTimer *modem_status_poll; | |
8e8ffc44 | 157 | MemoryRegion io; |
b41a2cd1 | 158 | }; |
80cabfad | 159 | |
ac0be998 GH |
160 | typedef struct ISASerialState { |
161 | ISADevice dev; | |
e8ee28fb | 162 | uint32_t index; |
ac0be998 GH |
163 | uint32_t iobase; |
164 | uint32_t isairq; | |
165 | SerialState state; | |
166 | } ISASerialState; | |
167 | ||
81174dae | 168 | static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
b2a5160c | 169 | |
81174dae | 170 | static void fifo_clear(SerialState *s, int fifo) |
80cabfad | 171 | { |
81174dae AL |
172 | SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
173 | memset(f->data, 0, UART_FIFO_LENGTH); | |
174 | f->count = 0; | |
175 | f->head = 0; | |
176 | f->tail = 0; | |
80cabfad FB |
177 | } |
178 | ||
81174dae | 179 | static int fifo_put(SerialState *s, int fifo, uint8_t chr) |
6936bfe5 | 180 | { |
81174dae | 181 | SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
6936bfe5 | 182 | |
71e605f8 JG |
183 | /* Receive overruns do not overwrite FIFO contents. */ |
184 | if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) { | |
6936bfe5 | 185 | |
71e605f8 JG |
186 | f->data[f->head++] = chr; |
187 | ||
188 | if (f->head == UART_FIFO_LENGTH) | |
189 | f->head = 0; | |
190 | } | |
191 | ||
192 | if (f->count < UART_FIFO_LENGTH) | |
193 | f->count++; | |
194 | else if (fifo == RECV_FIFO) | |
195 | s->lsr |= UART_LSR_OE; | |
81174dae AL |
196 | |
197 | return 1; | |
198 | } | |
199 | ||
200 | static uint8_t fifo_get(SerialState *s, int fifo) | |
201 | { | |
202 | SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; | |
203 | uint8_t c; | |
204 | ||
205 | if(f->count == 0) | |
206 | return 0; | |
207 | ||
208 | c = f->data[f->tail++]; | |
209 | if (f->tail == UART_FIFO_LENGTH) | |
210 | f->tail = 0; | |
211 | f->count--; | |
212 | ||
213 | return c; | |
214 | } | |
6936bfe5 | 215 | |
81174dae AL |
216 | static void serial_update_irq(SerialState *s) |
217 | { | |
218 | uint8_t tmp_iir = UART_IIR_NO_INT; | |
219 | ||
81174dae AL |
220 | if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { |
221 | tmp_iir = UART_IIR_RLSI; | |
5628a626 | 222 | } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { |
c9a33054 AZ |
223 | /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, |
224 | * this is not in the specification but is observed on existing | |
225 | * hardware. */ | |
81174dae | 226 | tmp_iir = UART_IIR_CTI; |
2d6ee8e7 JL |
227 | } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && |
228 | (!(s->fcr & UART_FCR_FE) || | |
229 | s->recv_fifo.count >= s->recv_fifo.itl)) { | |
230 | tmp_iir = UART_IIR_RDI; | |
81174dae AL |
231 | } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
232 | tmp_iir = UART_IIR_THRI; | |
233 | } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { | |
234 | tmp_iir = UART_IIR_MSI; | |
235 | } | |
236 | ||
237 | s->iir = tmp_iir | (s->iir & 0xF0); | |
238 | ||
239 | if (tmp_iir != UART_IIR_NO_INT) { | |
240 | qemu_irq_raise(s->irq); | |
241 | } else { | |
242 | qemu_irq_lower(s->irq); | |
6936bfe5 | 243 | } |
6936bfe5 AJ |
244 | } |
245 | ||
f8d179e3 FB |
246 | static void serial_update_parameters(SerialState *s) |
247 | { | |
81174dae | 248 | int speed, parity, data_bits, stop_bits, frame_size; |
2122c51a | 249 | QEMUSerialSetParams ssp; |
f8d179e3 | 250 | |
81174dae AL |
251 | if (s->divider == 0) |
252 | return; | |
253 | ||
718b8aec | 254 | /* Start bit. */ |
81174dae | 255 | frame_size = 1; |
f8d179e3 | 256 | if (s->lcr & 0x08) { |
718b8aec SW |
257 | /* Parity bit. */ |
258 | frame_size++; | |
f8d179e3 FB |
259 | if (s->lcr & 0x10) |
260 | parity = 'E'; | |
261 | else | |
262 | parity = 'O'; | |
263 | } else { | |
264 | parity = 'N'; | |
265 | } | |
5fafdf24 | 266 | if (s->lcr & 0x04) |
f8d179e3 FB |
267 | stop_bits = 2; |
268 | else | |
269 | stop_bits = 1; | |
81174dae | 270 | |
f8d179e3 | 271 | data_bits = (s->lcr & 0x03) + 5; |
81174dae | 272 | frame_size += data_bits + stop_bits; |
b6cd0ea1 | 273 | speed = s->baudbase / s->divider; |
2122c51a FB |
274 | ssp.speed = speed; |
275 | ssp.parity = parity; | |
276 | ssp.data_bits = data_bits; | |
277 | ssp.stop_bits = stop_bits; | |
6ee093c9 | 278 | s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; |
41084f1b | 279 | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
b6601141 MN |
280 | |
281 | DPRINTF("speed=%d parity=%c data=%d stop=%d\n", | |
f8d179e3 | 282 | speed, parity, data_bits, stop_bits); |
f8d179e3 FB |
283 | } |
284 | ||
81174dae AL |
285 | static void serial_update_msl(SerialState *s) |
286 | { | |
287 | uint8_t omsr; | |
288 | int flags; | |
289 | ||
290 | qemu_del_timer(s->modem_status_poll); | |
291 | ||
41084f1b | 292 | if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) { |
81174dae AL |
293 | s->poll_msl = -1; |
294 | return; | |
295 | } | |
296 | ||
297 | omsr = s->msr; | |
298 | ||
299 | s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; | |
300 | s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; | |
301 | s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; | |
302 | s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; | |
303 | ||
304 | if (s->msr != omsr) { | |
305 | /* Set delta bits */ | |
306 | s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); | |
307 | /* UART_MSR_TERI only if change was from 1 -> 0 */ | |
308 | if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) | |
309 | s->msr &= ~UART_MSR_TERI; | |
310 | serial_update_irq(s); | |
311 | } | |
312 | ||
313 | /* The real 16550A apparently has a 250ns response latency to line status changes. | |
314 | We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ | |
315 | ||
316 | if (s->poll_msl) | |
74475455 | 317 | qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100); |
81174dae AL |
318 | } |
319 | ||
320 | static void serial_xmit(void *opaque) | |
321 | { | |
322 | SerialState *s = opaque; | |
74475455 | 323 | uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock); |
81174dae AL |
324 | |
325 | if (s->tsr_retry <= 0) { | |
326 | if (s->fcr & UART_FCR_FE) { | |
327 | s->tsr = fifo_get(s,XMIT_FIFO); | |
328 | if (!s->xmit_fifo.count) | |
329 | s->lsr |= UART_LSR_THRE; | |
67c5322d AL |
330 | } else if ((s->lsr & UART_LSR_THRE)) { |
331 | return; | |
81174dae AL |
332 | } else { |
333 | s->tsr = s->thr; | |
334 | s->lsr |= UART_LSR_THRE; | |
dfe844c9 | 335 | s->lsr &= ~UART_LSR_TEMT; |
81174dae AL |
336 | } |
337 | } | |
338 | ||
339 | if (s->mcr & UART_MCR_LOOP) { | |
340 | /* in loopback mode, say that we just received a char */ | |
341 | serial_receive1(s, &s->tsr, 1); | |
2cc6e0a1 | 342 | } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) { |
67c5322d | 343 | if ((s->tsr_retry >= 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { |
81174dae AL |
344 | s->tsr_retry++; |
345 | qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time); | |
346 | return; | |
347 | } else if (s->poll_msl < 0) { | |
348 | /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then | |
349 | drop any further failed writes instantly, until we get one that goes through. | |
350 | This is to prevent guests that log to unconnected pipes or pty's from stalling. */ | |
351 | s->tsr_retry = -1; | |
352 | } | |
353 | } | |
354 | else { | |
355 | s->tsr_retry = 0; | |
356 | } | |
357 | ||
74475455 | 358 | s->last_xmit_ts = qemu_get_clock_ns(vm_clock); |
81174dae AL |
359 | if (!(s->lsr & UART_LSR_THRE)) |
360 | qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time); | |
361 | ||
362 | if (s->lsr & UART_LSR_THRE) { | |
363 | s->lsr |= UART_LSR_TEMT; | |
364 | s->thr_ipending = 1; | |
365 | serial_update_irq(s); | |
366 | } | |
367 | } | |
368 | ||
369 | ||
b41a2cd1 | 370 | static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 371 | { |
b41a2cd1 | 372 | SerialState *s = opaque; |
3b46e624 | 373 | |
80cabfad | 374 | addr &= 7; |
b6601141 | 375 | DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val); |
80cabfad FB |
376 | switch(addr) { |
377 | default: | |
378 | case 0: | |
379 | if (s->lcr & UART_LCR_DLAB) { | |
380 | s->divider = (s->divider & 0xff00) | val; | |
f8d179e3 | 381 | serial_update_parameters(s); |
80cabfad | 382 | } else { |
81174dae AL |
383 | s->thr = (uint8_t) val; |
384 | if(s->fcr & UART_FCR_FE) { | |
2f4f22bd AJ |
385 | fifo_put(s, XMIT_FIFO, s->thr); |
386 | s->thr_ipending = 0; | |
387 | s->lsr &= ~UART_LSR_TEMT; | |
388 | s->lsr &= ~UART_LSR_THRE; | |
389 | serial_update_irq(s); | |
6936bfe5 | 390 | } else { |
2f4f22bd AJ |
391 | s->thr_ipending = 0; |
392 | s->lsr &= ~UART_LSR_THRE; | |
393 | serial_update_irq(s); | |
6936bfe5 | 394 | } |
81174dae | 395 | serial_xmit(s); |
80cabfad FB |
396 | } |
397 | break; | |
398 | case 1: | |
399 | if (s->lcr & UART_LCR_DLAB) { | |
400 | s->divider = (s->divider & 0x00ff) | (val << 8); | |
f8d179e3 | 401 | serial_update_parameters(s); |
80cabfad | 402 | } else { |
60e336db | 403 | s->ier = val & 0x0f; |
81174dae AL |
404 | /* If the backend device is a real serial port, turn polling of the modem |
405 | status lines on physical port on or off depending on UART_IER_MSI state */ | |
406 | if (s->poll_msl >= 0) { | |
407 | if (s->ier & UART_IER_MSI) { | |
408 | s->poll_msl = 1; | |
409 | serial_update_msl(s); | |
410 | } else { | |
411 | qemu_del_timer(s->modem_status_poll); | |
412 | s->poll_msl = 0; | |
413 | } | |
414 | } | |
60e336db FB |
415 | if (s->lsr & UART_LSR_THRE) { |
416 | s->thr_ipending = 1; | |
81174dae | 417 | serial_update_irq(s); |
60e336db | 418 | } |
80cabfad FB |
419 | } |
420 | break; | |
421 | case 2: | |
81174dae AL |
422 | val = val & 0xFF; |
423 | ||
424 | if (s->fcr == val) | |
425 | break; | |
426 | ||
427 | /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */ | |
428 | if ((val ^ s->fcr) & UART_FCR_FE) | |
429 | val |= UART_FCR_XFR | UART_FCR_RFR; | |
430 | ||
431 | /* FIFO clear */ | |
432 | ||
433 | if (val & UART_FCR_RFR) { | |
434 | qemu_del_timer(s->fifo_timeout_timer); | |
435 | s->timeout_ipending=0; | |
436 | fifo_clear(s,RECV_FIFO); | |
437 | } | |
438 | ||
439 | if (val & UART_FCR_XFR) { | |
440 | fifo_clear(s,XMIT_FIFO); | |
441 | } | |
442 | ||
443 | if (val & UART_FCR_FE) { | |
444 | s->iir |= UART_IIR_FE; | |
445 | /* Set RECV_FIFO trigger Level */ | |
446 | switch (val & 0xC0) { | |
447 | case UART_FCR_ITL_1: | |
448 | s->recv_fifo.itl = 1; | |
449 | break; | |
450 | case UART_FCR_ITL_2: | |
451 | s->recv_fifo.itl = 4; | |
452 | break; | |
453 | case UART_FCR_ITL_3: | |
454 | s->recv_fifo.itl = 8; | |
455 | break; | |
456 | case UART_FCR_ITL_4: | |
457 | s->recv_fifo.itl = 14; | |
458 | break; | |
459 | } | |
460 | } else | |
461 | s->iir &= ~UART_IIR_FE; | |
462 | ||
463 | /* Set fcr - or at least the bits in it that are supposed to "stick" */ | |
464 | s->fcr = val & 0xC9; | |
465 | serial_update_irq(s); | |
80cabfad FB |
466 | break; |
467 | case 3: | |
f8d179e3 FB |
468 | { |
469 | int break_enable; | |
470 | s->lcr = val; | |
471 | serial_update_parameters(s); | |
472 | break_enable = (val >> 6) & 1; | |
473 | if (break_enable != s->last_break_enable) { | |
474 | s->last_break_enable = break_enable; | |
41084f1b | 475 | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
2122c51a | 476 | &break_enable); |
f8d179e3 FB |
477 | } |
478 | } | |
80cabfad FB |
479 | break; |
480 | case 4: | |
81174dae AL |
481 | { |
482 | int flags; | |
483 | int old_mcr = s->mcr; | |
484 | s->mcr = val & 0x1f; | |
485 | if (val & UART_MCR_LOOP) | |
486 | break; | |
487 | ||
488 | if (s->poll_msl >= 0 && old_mcr != s->mcr) { | |
489 | ||
41084f1b | 490 | qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); |
81174dae AL |
491 | |
492 | flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); | |
493 | ||
494 | if (val & UART_MCR_RTS) | |
495 | flags |= CHR_TIOCM_RTS; | |
496 | if (val & UART_MCR_DTR) | |
497 | flags |= CHR_TIOCM_DTR; | |
498 | ||
41084f1b | 499 | qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
81174dae AL |
500 | /* Update the modem status after a one-character-send wait-time, since there may be a response |
501 | from the device/computer at the other end of the serial line */ | |
74475455 | 502 | qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time); |
81174dae AL |
503 | } |
504 | } | |
80cabfad FB |
505 | break; |
506 | case 5: | |
507 | break; | |
508 | case 6: | |
80cabfad FB |
509 | break; |
510 | case 7: | |
511 | s->scr = val; | |
512 | break; | |
513 | } | |
514 | } | |
515 | ||
b41a2cd1 | 516 | static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
80cabfad | 517 | { |
b41a2cd1 | 518 | SerialState *s = opaque; |
80cabfad FB |
519 | uint32_t ret; |
520 | ||
521 | addr &= 7; | |
522 | switch(addr) { | |
523 | default: | |
524 | case 0: | |
525 | if (s->lcr & UART_LCR_DLAB) { | |
5fafdf24 | 526 | ret = s->divider & 0xff; |
80cabfad | 527 | } else { |
81174dae AL |
528 | if(s->fcr & UART_FCR_FE) { |
529 | ret = fifo_get(s,RECV_FIFO); | |
530 | if (s->recv_fifo.count == 0) | |
531 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
532 | else | |
74475455 | 533 | qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); |
81174dae AL |
534 | s->timeout_ipending = 0; |
535 | } else { | |
536 | ret = s->rbr; | |
537 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
538 | } | |
b41a2cd1 | 539 | serial_update_irq(s); |
b2a5160c AZ |
540 | if (!(s->mcr & UART_MCR_LOOP)) { |
541 | /* in loopback mode, don't receive any data */ | |
542 | qemu_chr_accept_input(s->chr); | |
543 | } | |
80cabfad FB |
544 | } |
545 | break; | |
546 | case 1: | |
547 | if (s->lcr & UART_LCR_DLAB) { | |
548 | ret = (s->divider >> 8) & 0xff; | |
549 | } else { | |
550 | ret = s->ier; | |
551 | } | |
552 | break; | |
553 | case 2: | |
554 | ret = s->iir; | |
cdee7bdf | 555 | if ((ret & UART_IIR_ID) == UART_IIR_THRI) { |
80cabfad | 556 | s->thr_ipending = 0; |
71e605f8 JG |
557 | serial_update_irq(s); |
558 | } | |
80cabfad FB |
559 | break; |
560 | case 3: | |
561 | ret = s->lcr; | |
562 | break; | |
563 | case 4: | |
564 | ret = s->mcr; | |
565 | break; | |
566 | case 5: | |
567 | ret = s->lsr; | |
71e605f8 JG |
568 | /* Clear break and overrun interrupts */ |
569 | if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { | |
570 | s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); | |
81174dae AL |
571 | serial_update_irq(s); |
572 | } | |
80cabfad FB |
573 | break; |
574 | case 6: | |
575 | if (s->mcr & UART_MCR_LOOP) { | |
576 | /* in loopback, the modem output pins are connected to the | |
577 | inputs */ | |
578 | ret = (s->mcr & 0x0c) << 4; | |
579 | ret |= (s->mcr & 0x02) << 3; | |
580 | ret |= (s->mcr & 0x01) << 5; | |
581 | } else { | |
81174dae AL |
582 | if (s->poll_msl >= 0) |
583 | serial_update_msl(s); | |
80cabfad | 584 | ret = s->msr; |
81174dae AL |
585 | /* Clear delta bits & msr int after read, if they were set */ |
586 | if (s->msr & UART_MSR_ANY_DELTA) { | |
587 | s->msr &= 0xF0; | |
588 | serial_update_irq(s); | |
589 | } | |
80cabfad FB |
590 | } |
591 | break; | |
592 | case 7: | |
593 | ret = s->scr; | |
594 | break; | |
595 | } | |
b6601141 | 596 | DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret); |
80cabfad FB |
597 | return ret; |
598 | } | |
599 | ||
82c643ff | 600 | static int serial_can_receive(SerialState *s) |
80cabfad | 601 | { |
81174dae AL |
602 | if(s->fcr & UART_FCR_FE) { |
603 | if(s->recv_fifo.count < UART_FIFO_LENGTH) | |
604 | /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is | |
605 | advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond, | |
606 | effectively overriding the ITL that the guest has set. */ | |
607 | return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1; | |
608 | else | |
609 | return 0; | |
610 | } else { | |
80cabfad | 611 | return !(s->lsr & UART_LSR_DR); |
81174dae | 612 | } |
80cabfad FB |
613 | } |
614 | ||
82c643ff | 615 | static void serial_receive_break(SerialState *s) |
80cabfad | 616 | { |
80cabfad | 617 | s->rbr = 0; |
40ff1624 JW |
618 | /* When the LSR_DR is set a null byte is pushed into the fifo */ |
619 | fifo_put(s, RECV_FIFO, '\0'); | |
80cabfad | 620 | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
b41a2cd1 | 621 | serial_update_irq(s); |
80cabfad FB |
622 | } |
623 | ||
81174dae AL |
624 | /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ |
625 | static void fifo_timeout_int (void *opaque) { | |
626 | SerialState *s = opaque; | |
627 | if (s->recv_fifo.count) { | |
628 | s->timeout_ipending = 1; | |
629 | serial_update_irq(s); | |
630 | } | |
631 | } | |
632 | ||
b41a2cd1 | 633 | static int serial_can_receive1(void *opaque) |
80cabfad | 634 | { |
b41a2cd1 FB |
635 | SerialState *s = opaque; |
636 | return serial_can_receive(s); | |
637 | } | |
638 | ||
639 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) | |
640 | { | |
641 | SerialState *s = opaque; | |
9826fd59 GH |
642 | |
643 | if (s->wakeup) { | |
644 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER); | |
645 | } | |
81174dae AL |
646 | if(s->fcr & UART_FCR_FE) { |
647 | int i; | |
648 | for (i = 0; i < size; i++) { | |
649 | fifo_put(s, RECV_FIFO, buf[i]); | |
650 | } | |
651 | s->lsr |= UART_LSR_DR; | |
652 | /* call the timeout receive callback in 4 char transmit time */ | |
74475455 | 653 | qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); |
81174dae | 654 | } else { |
71e605f8 JG |
655 | if (s->lsr & UART_LSR_DR) |
656 | s->lsr |= UART_LSR_OE; | |
81174dae AL |
657 | s->rbr = buf[0]; |
658 | s->lsr |= UART_LSR_DR; | |
659 | } | |
660 | serial_update_irq(s); | |
b41a2cd1 | 661 | } |
80cabfad | 662 | |
82c643ff FB |
663 | static void serial_event(void *opaque, int event) |
664 | { | |
665 | SerialState *s = opaque; | |
b6601141 | 666 | DPRINTF("event %x\n", event); |
82c643ff FB |
667 | if (event == CHR_EVENT_BREAK) |
668 | serial_receive_break(s); | |
669 | } | |
670 | ||
d4bfa4d7 | 671 | static void serial_pre_save(void *opaque) |
8738a8d0 | 672 | { |
d4bfa4d7 | 673 | SerialState *s = opaque; |
747791f1 | 674 | s->fcr_vmstate = s->fcr; |
8738a8d0 FB |
675 | } |
676 | ||
e59fb374 | 677 | static int serial_post_load(void *opaque, int version_id) |
747791f1 JQ |
678 | { |
679 | SerialState *s = opaque; | |
81174dae | 680 | |
4c18ce94 JQ |
681 | if (version_id < 3) { |
682 | s->fcr_vmstate = 0; | |
683 | } | |
81174dae | 684 | /* Initialize fcr via setter to perform essential side-effects */ |
747791f1 | 685 | serial_ioport_write(s, 0x02, s->fcr_vmstate); |
9a7c4878 | 686 | serial_update_parameters(s); |
8738a8d0 FB |
687 | return 0; |
688 | } | |
689 | ||
747791f1 JQ |
690 | static const VMStateDescription vmstate_serial = { |
691 | .name = "serial", | |
692 | .version_id = 3, | |
693 | .minimum_version_id = 2, | |
694 | .pre_save = serial_pre_save, | |
747791f1 JQ |
695 | .post_load = serial_post_load, |
696 | .fields = (VMStateField []) { | |
697 | VMSTATE_UINT16_V(divider, SerialState, 2), | |
698 | VMSTATE_UINT8(rbr, SerialState), | |
699 | VMSTATE_UINT8(ier, SerialState), | |
700 | VMSTATE_UINT8(iir, SerialState), | |
701 | VMSTATE_UINT8(lcr, SerialState), | |
702 | VMSTATE_UINT8(mcr, SerialState), | |
703 | VMSTATE_UINT8(lsr, SerialState), | |
704 | VMSTATE_UINT8(msr, SerialState), | |
705 | VMSTATE_UINT8(scr, SerialState), | |
706 | VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3), | |
707 | VMSTATE_END_OF_LIST() | |
708 | } | |
709 | }; | |
710 | ||
b2a5160c AZ |
711 | static void serial_reset(void *opaque) |
712 | { | |
713 | SerialState *s = opaque; | |
714 | ||
b2a5160c AZ |
715 | s->rbr = 0; |
716 | s->ier = 0; | |
717 | s->iir = UART_IIR_NO_INT; | |
718 | s->lcr = 0; | |
b2a5160c AZ |
719 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
720 | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; | |
718b8aec | 721 | /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */ |
81174dae AL |
722 | s->divider = 0x0C; |
723 | s->mcr = UART_MCR_OUT2; | |
b2a5160c | 724 | s->scr = 0; |
81174dae | 725 | s->tsr_retry = 0; |
718b8aec | 726 | s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10; |
81174dae AL |
727 | s->poll_msl = 0; |
728 | ||
729 | fifo_clear(s,RECV_FIFO); | |
730 | fifo_clear(s,XMIT_FIFO); | |
731 | ||
74475455 | 732 | s->last_xmit_ts = qemu_get_clock_ns(vm_clock); |
b2a5160c AZ |
733 | |
734 | s->thr_ipending = 0; | |
735 | s->last_break_enable = 0; | |
736 | qemu_irq_lower(s->irq); | |
737 | } | |
738 | ||
ac0be998 | 739 | static void serial_init_core(SerialState *s) |
81174dae | 740 | { |
ac0be998 | 741 | if (!s->chr) { |
387f4a5a AJ |
742 | fprintf(stderr, "Can't create serial device, empty char device\n"); |
743 | exit(1); | |
744 | } | |
745 | ||
74475455 | 746 | s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s); |
81174dae | 747 | |
74475455 PB |
748 | s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); |
749 | s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s); | |
81174dae | 750 | |
a08d4367 | 751 | qemu_register_reset(serial_reset, s); |
81174dae | 752 | |
b47543c4 AJ |
753 | qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, |
754 | serial_event, s); | |
81174dae AL |
755 | } |
756 | ||
038eaf82 SW |
757 | /* Change the main reference oscillator frequency. */ |
758 | void serial_set_frequency(SerialState *s, uint32_t frequency) | |
759 | { | |
760 | s->baudbase = frequency; | |
761 | serial_update_parameters(s); | |
762 | } | |
763 | ||
e8ee28fb GH |
764 | static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
765 | static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
766 | ||
a941ae45 RH |
767 | static const MemoryRegionPortio serial_portio[] = { |
768 | { 0, 8, 1, .read = serial_ioport_read, .write = serial_ioport_write }, | |
769 | PORTIO_END_OF_LIST() | |
770 | }; | |
771 | ||
772 | static const MemoryRegionOps serial_io_ops = { | |
773 | .old_portio = serial_portio | |
774 | }; | |
775 | ||
ac0be998 GH |
776 | static int serial_isa_initfn(ISADevice *dev) |
777 | { | |
e8ee28fb | 778 | static int index; |
ac0be998 GH |
779 | ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev); |
780 | SerialState *s = &isa->state; | |
781 | ||
e8ee28fb GH |
782 | if (isa->index == -1) |
783 | isa->index = index; | |
784 | if (isa->index >= MAX_SERIAL_PORTS) | |
785 | return -1; | |
786 | if (isa->iobase == -1) | |
787 | isa->iobase = isa_serial_io[isa->index]; | |
788 | if (isa->isairq == -1) | |
789 | isa->isairq = isa_serial_irq[isa->index]; | |
790 | index++; | |
791 | ||
ac0be998 GH |
792 | s->baudbase = 115200; |
793 | isa_init_irq(dev, &s->irq, isa->isairq); | |
794 | serial_init_core(s); | |
1cc9f514 | 795 | qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3); |
ac0be998 | 796 | |
8e8ffc44 RH |
797 | memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8); |
798 | isa_register_ioport(dev, &s->io, isa->iobase); | |
ac0be998 GH |
799 | return 0; |
800 | } | |
801 | ||
1cc9f514 JK |
802 | static const VMStateDescription vmstate_isa_serial = { |
803 | .name = "serial", | |
804 | .version_id = 3, | |
805 | .minimum_version_id = 2, | |
806 | .fields = (VMStateField []) { | |
807 | VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState), | |
808 | VMSTATE_END_OF_LIST() | |
809 | } | |
810 | }; | |
811 | ||
b6cd0ea1 AJ |
812 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
813 | CharDriverState *chr) | |
b41a2cd1 FB |
814 | { |
815 | SerialState *s; | |
816 | ||
7267c094 | 817 | s = g_malloc0(sizeof(SerialState)); |
6936bfe5 | 818 | |
ac0be998 GH |
819 | s->irq = irq; |
820 | s->baudbase = baudbase; | |
821 | s->chr = chr; | |
822 | serial_init_core(s); | |
b41a2cd1 | 823 | |
0be71e32 | 824 | vmstate_register(NULL, base, &vmstate_serial, s); |
8738a8d0 | 825 | |
b41a2cd1 FB |
826 | register_ioport_write(base, 8, 1, serial_ioport_write, s); |
827 | register_ioport_read(base, 8, 1, serial_ioport_read, s); | |
b41a2cd1 | 828 | return s; |
80cabfad | 829 | } |
e5d13e2f FB |
830 | |
831 | /* Memory mapped interface */ | |
8e8ffc44 RH |
832 | static uint64_t serial_mm_read(void *opaque, target_phys_addr_t addr, |
833 | unsigned size) | |
e5d13e2f FB |
834 | { |
835 | SerialState *s = opaque; | |
8e8ffc44 | 836 | return serial_ioport_read(s, addr >> s->it_shift); |
e5d13e2f FB |
837 | } |
838 | ||
8e8ffc44 RH |
839 | static void serial_mm_write(void *opaque, target_phys_addr_t addr, |
840 | uint64_t value, unsigned size) | |
2d48377a BS |
841 | { |
842 | SerialState *s = opaque; | |
8e8ffc44 | 843 | value &= ~0u >> (32 - (size * 8)); |
2d48377a BS |
844 | serial_ioport_write(s, addr >> s->it_shift, value); |
845 | } | |
846 | ||
8e8ffc44 RH |
847 | static const MemoryRegionOps serial_mm_ops[3] = { |
848 | [DEVICE_NATIVE_ENDIAN] = { | |
849 | .read = serial_mm_read, | |
850 | .write = serial_mm_write, | |
851 | .endianness = DEVICE_NATIVE_ENDIAN, | |
852 | }, | |
853 | [DEVICE_LITTLE_ENDIAN] = { | |
854 | .read = serial_mm_read, | |
855 | .write = serial_mm_write, | |
856 | .endianness = DEVICE_LITTLE_ENDIAN, | |
857 | }, | |
858 | [DEVICE_BIG_ENDIAN] = { | |
859 | .read = serial_mm_read, | |
860 | .write = serial_mm_write, | |
861 | .endianness = DEVICE_BIG_ENDIAN, | |
862 | }, | |
e5d13e2f FB |
863 | }; |
864 | ||
39186d8a RH |
865 | SerialState *serial_mm_init(MemoryRegion *address_space, |
866 | target_phys_addr_t base, int it_shift, | |
867 | qemu_irq irq, int baudbase, | |
868 | CharDriverState *chr, enum device_endian end) | |
e5d13e2f FB |
869 | { |
870 | SerialState *s; | |
e5d13e2f | 871 | |
7267c094 | 872 | s = g_malloc0(sizeof(SerialState)); |
81174dae | 873 | |
e5d13e2f | 874 | s->it_shift = it_shift; |
ac0be998 GH |
875 | s->irq = irq; |
876 | s->baudbase = baudbase; | |
877 | s->chr = chr; | |
e5d13e2f | 878 | |
ac0be998 | 879 | serial_init_core(s); |
0be71e32 | 880 | vmstate_register(NULL, base, &vmstate_serial, s); |
e5d13e2f | 881 | |
8e8ffc44 RH |
882 | memory_region_init_io(&s->io, &serial_mm_ops[end], s, |
883 | "serial", 8 << it_shift); | |
39186d8a | 884 | memory_region_add_subregion(address_space, base, &s->io); |
2ff0c7c3 | 885 | |
81174dae | 886 | serial_update_msl(s); |
e5d13e2f FB |
887 | return s; |
888 | } | |
ac0be998 | 889 | |
39bffca2 AL |
890 | static Property serial_isa_properties[] = { |
891 | DEFINE_PROP_UINT32("index", ISASerialState, index, -1), | |
892 | DEFINE_PROP_HEX32("iobase", ISASerialState, iobase, -1), | |
893 | DEFINE_PROP_UINT32("irq", ISASerialState, isairq, -1), | |
894 | DEFINE_PROP_CHR("chardev", ISASerialState, state.chr), | |
9826fd59 | 895 | DEFINE_PROP_UINT32("wakeup", ISASerialState, state.wakeup, 0), |
39bffca2 AL |
896 | DEFINE_PROP_END_OF_LIST(), |
897 | }; | |
898 | ||
8f04ee08 AL |
899 | static void serial_isa_class_initfn(ObjectClass *klass, void *data) |
900 | { | |
39bffca2 | 901 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 AL |
902 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
903 | ic->init = serial_isa_initfn; | |
39bffca2 AL |
904 | dc->vmsd = &vmstate_isa_serial; |
905 | dc->props = serial_isa_properties; | |
8f04ee08 AL |
906 | } |
907 | ||
39bffca2 AL |
908 | static TypeInfo serial_isa_info = { |
909 | .name = "isa-serial", | |
910 | .parent = TYPE_ISA_DEVICE, | |
911 | .instance_size = sizeof(ISASerialState), | |
912 | .class_init = serial_isa_class_initfn, | |
ac0be998 GH |
913 | }; |
914 | ||
83f7d43a | 915 | static void serial_register_types(void) |
ac0be998 | 916 | { |
39bffca2 | 917 | type_register_static(&serial_isa_info); |
ac0be998 GH |
918 | } |
919 | ||
83f7d43a | 920 | type_init(serial_register_types) |