[qemu.git] / hw / serial.c

/*
 * QEMU 16450 UART emulation
 * 
 * Copyright (c) 2003-2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_SERIAL

#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */

#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
#define UART_MCR_OUT2	0x08	/* Out2 complement */
#define UART_MCR_OUT1	0x04	/* Out1 complement */
#define UART_MCR_RTS	0x02	/* RTS complement */
#define UART_MCR_DTR	0x01	/* DTR complement */

/*
 * These are the definitions for the Modem Status Register
 */
#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
#define UART_MSR_RI	0x40	/* Ring Indicator */
#define UART_MSR_DSR	0x20	/* Data Set Ready */
#define UART_MSR_CTS	0x10	/* Clear to Send */
#define UART_MSR_DDCD	0x08	/* Delta DCD */
#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02	/* Delta DSR */
#define UART_MSR_DCTS	0x01	/* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */

#define UART_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_LSR_FE	0x08	/* Frame error indicator */
#define UART_LSR_PE	0x04	/* Parity error indicator */
#define UART_LSR_OE	0x02	/* Overrun error indicator */
#define UART_LSR_DR	0x01	/* Receiver data ready */

struct SerialState {
    uint8_t divider;
    uint8_t rbr; /* receive register */
    uint8_t ier;
    uint8_t iir; /* read only */
    uint8_t lcr;
    uint8_t mcr;
    uint8_t lsr; /* read only */
    uint8_t msr;
    uint8_t scr;
    /* NOTE: this hidden state is necessary for tx irq generation as
       it can be reset while reading iir */
    int thr_ipending;
    int irq;
    int out_fd;
};

static void serial_update_irq(SerialState *s)
{
    if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
        s->iir = UART_IIR_RDI;
    } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
        s->iir = UART_IIR_THRI;
    } else {
        s->iir = UART_IIR_NO_INT;
    }
    if (s->iir != UART_IIR_NO_INT) {
        pic_set_irq(s->irq, 1);
    } else {
        pic_set_irq(s->irq, 0);
    }
}

static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    SerialState *s = opaque;
    unsigned char ch;
    int ret;
    
    addr &= 7;
#ifdef DEBUG_SERIAL
    printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0xff00) | val;
        } else {
            s->thr_ipending = 0;
            s->lsr &= ~UART_LSR_THRE;
            serial_update_irq(s);

            ch = val;
            do {
                ret = write(s->out_fd, &ch, 1);
            } while (ret != 1);
            s->thr_ipending = 1;
            s->lsr |= UART_LSR_THRE;
            s->lsr |= UART_LSR_TEMT;
            serial_update_irq(s);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0x00ff) | (val << 8);
        } else {
            s->ier = val;
            serial_update_irq(s);
        }
        break;
    case 2:
        break;
    case 3:
        s->lcr = val;
        break;
    case 4:
        s->mcr = val;
        break;
    case 5:
        break;
    case 6:
        s->msr = val;
        break;
    case 7:
        s->scr = val;
        break;
    }
}

static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
{
    SerialState *s = opaque;
    uint32_t ret;

    addr &= 7;
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            ret = s->divider & 0xff; 
        } else {
            ret = s->rbr;
            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
            serial_update_irq(s);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            ret = (s->divider >> 8) & 0xff;
        } else {
            ret = s->ier;
        }
        break;
    case 2:
        ret = s->iir;
        /* reset THR pending bit */
        if ((ret & 0x7) == UART_IIR_THRI)
            s->thr_ipending = 0;
        serial_update_irq(s);
        break;
    case 3:
        ret = s->lcr;
        break;
    case 4:
        ret = s->mcr;
        break;
    case 5:
        ret = s->lsr;
        break;
    case 6:
        if (s->mcr & UART_MCR_LOOP) {
            /* in loopback, the modem output pins are connected to the
               inputs */
            ret = (s->mcr & 0x0c) << 4;
            ret |= (s->mcr & 0x02) << 3;
            ret |= (s->mcr & 0x01) << 5;
        } else {
            ret = s->msr;
        }
        break;
    case 7:
        ret = s->scr;
        break;
    }
#ifdef DEBUG_SERIAL
    printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

int serial_can_receive(SerialState *s)
{
    return !(s->lsr & UART_LSR_DR);
}

void serial_receive_byte(SerialState *s, int ch)
{
    s->rbr = ch;
    s->lsr |= UART_LSR_DR;
    serial_update_irq(s);
}

void serial_receive_break(SerialState *s)
{
    s->rbr = 0;
    s->lsr |= UART_LSR_BI | UART_LSR_DR;
    serial_update_irq(s);
}

static int serial_can_receive1(void *opaque)
{
    SerialState *s = opaque;
    return serial_can_receive(s);
}

static void serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    SerialState *s = opaque;
    serial_receive_byte(s, buf[0]);
}

/* If fd is zero, it means that the serial device uses the console */
SerialState *serial_init(int base, int irq, int fd)
{
    SerialState *s;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->irq = irq;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->iir = UART_IIR_NO_INT;

    register_ioport_write(base, 8, 1, serial_ioport_write, s);
    register_ioport_read(base, 8, 1, serial_ioport_read, s);

    if (fd != 0) {
        qemu_add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s);
        s->out_fd = fd;
    } else {
        serial_console = s;
        s->out_fd = 1;
    }
    return s;
}
Commit	Line	Data
80cabfad FB	1	/*
	2	* QEMU 16450 UART emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80cabfad FB	24	#include "vl.h"
	25
	26	//#define DEBUG_SERIAL
	27
	28	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	29
	30	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
	31	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
	32	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
	33	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
	34
	35	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
	36	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
	37
	38	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
	39	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
	40	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
	41	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
	42
	43	/*
	44	* These are the definitions for the Modem Control Register
	45	*/
	46	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
	47	#define UART_MCR_OUT2 0x08 /* Out2 complement */
	48	#define UART_MCR_OUT1 0x04 /* Out1 complement */
	49	#define UART_MCR_RTS 0x02 /* RTS complement */
	50	#define UART_MCR_DTR 0x01 /* DTR complement */
	51
	52	/*
	53	* These are the definitions for the Modem Status Register
	54	*/
	55	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
	56	#define UART_MSR_RI 0x40 /* Ring Indicator */
	57	#define UART_MSR_DSR 0x20 /* Data Set Ready */
	58	#define UART_MSR_CTS 0x10 /* Clear to Send */
	59	#define UART_MSR_DDCD 0x08 /* Delta DCD */
	60	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
	61	#define UART_MSR_DDSR 0x02 /* Delta DSR */
	62	#define UART_MSR_DCTS 0x01 /* Delta CTS */
	63	#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
	64
	65	#define UART_LSR_TEMT 0x40 /* Transmitter empty */
	66	#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
	67	#define UART_LSR_BI 0x10 /* Break interrupt indicator */
	68	#define UART_LSR_FE 0x08 /* Frame error indicator */
	69	#define UART_LSR_PE 0x04 /* Parity error indicator */
	70	#define UART_LSR_OE 0x02 /* Overrun error indicator */
	71	#define UART_LSR_DR 0x01 /* Receiver data ready */
	72
b41a2cd1	73	struct SerialState {
80cabfad FB	74	uint8_t divider;
	75	uint8_t rbr; /* receive register */
	76	uint8_t ier;
	77	uint8_t iir; /* read only */
	78	uint8_t lcr;
	79	uint8_t mcr;
	80	uint8_t lsr; /* read only */
	81	uint8_t msr;
	82	uint8_t scr;
	83	/* NOTE: this hidden state is necessary for tx irq generation as
	84	it can be reset while reading iir */
	85	int thr_ipending;
	86	int irq;
b41a2cd1 FB	87	int out_fd;
b41a2cd1 FB	88	};
80cabfad	89
b41a2cd1	90	static void serial_update_irq(SerialState *s)
80cabfad	91	{
80cabfad FB	92	if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
	93	s->iir = UART_IIR_RDI;
	94	} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
	95	s->iir = UART_IIR_THRI;
	96	} else {
	97	s->iir = UART_IIR_NO_INT;
	98	}
	99	if (s->iir != UART_IIR_NO_INT) {
	100	pic_set_irq(s->irq, 1);
	101	} else {
	102	pic_set_irq(s->irq, 0);
	103	}
	104	}
	105
b41a2cd1	106	static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	107	{
b41a2cd1	108	SerialState *s = opaque;
80cabfad FB	109	unsigned char ch;
	110	int ret;
	111
	112	addr &= 7;
	113	#ifdef DEBUG_SERIAL
	114	printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
	115	#endif
	116	switch(addr) {
	117	default:
	118	case 0:
	119	if (s->lcr & UART_LCR_DLAB) {
	120	s->divider = (s->divider & 0xff00) \| val;
	121	} else {
	122	s->thr_ipending = 0;
	123	s->lsr &= ~UART_LSR_THRE;
b41a2cd1	124	serial_update_irq(s);
80cabfad FB	125
	126	ch = val;
	127	do {
b41a2cd1	128	ret = write(s->out_fd, &ch, 1);
80cabfad FB	129	} while (ret != 1);
	130	s->thr_ipending = 1;
	131	s->lsr \|= UART_LSR_THRE;
	132	s->lsr \|= UART_LSR_TEMT;
b41a2cd1	133	serial_update_irq(s);
80cabfad FB	134	}
	135	break;
	136	case 1:
	137	if (s->lcr & UART_LCR_DLAB) {
	138	s->divider = (s->divider & 0x00ff) \| (val << 8);
	139	} else {
	140	s->ier = val;
b41a2cd1	141	serial_update_irq(s);
80cabfad FB	142	}
	143	break;
	144	case 2:
	145	break;
	146	case 3:
	147	s->lcr = val;
	148	break;
	149	case 4:
	150	s->mcr = val;
	151	break;
	152	case 5:
	153	break;
	154	case 6:
	155	s->msr = val;
	156	break;
	157	case 7:
	158	s->scr = val;
	159	break;
	160	}
	161	}
	162
b41a2cd1	163	static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
80cabfad	164	{
b41a2cd1	165	SerialState *s = opaque;
80cabfad FB	166	uint32_t ret;
	167
	168	addr &= 7;
	169	switch(addr) {
	170	default:
	171	case 0:
	172	if (s->lcr & UART_LCR_DLAB) {
	173	ret = s->divider & 0xff;
	174	} else {
	175	ret = s->rbr;
	176	s->lsr &= ~(UART_LSR_DR \| UART_LSR_BI);
b41a2cd1	177	serial_update_irq(s);
80cabfad FB	178	}
	179	break;
	180	case 1:
	181	if (s->lcr & UART_LCR_DLAB) {
	182	ret = (s->divider >> 8) & 0xff;
	183	} else {
	184	ret = s->ier;
	185	}
	186	break;
	187	case 2:
	188	ret = s->iir;
	189	/* reset THR pending bit */
	190	if ((ret & 0x7) == UART_IIR_THRI)
	191	s->thr_ipending = 0;
b41a2cd1	192	serial_update_irq(s);
80cabfad FB	193	break;
	194	case 3:
	195	ret = s->lcr;
	196	break;
	197	case 4:
	198	ret = s->mcr;
	199	break;
	200	case 5:
	201	ret = s->lsr;
	202	break;
	203	case 6:
	204	if (s->mcr & UART_MCR_LOOP) {
	205	/* in loopback, the modem output pins are connected to the
	206	inputs */
	207	ret = (s->mcr & 0x0c) << 4;
	208	ret \|= (s->mcr & 0x02) << 3;
	209	ret \|= (s->mcr & 0x01) << 5;
	210	} else {
	211	ret = s->msr;
	212	}
	213	break;
	214	case 7:
	215	ret = s->scr;
	216	break;
	217	}
	218	#ifdef DEBUG_SERIAL
	219	printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
	220	#endif
	221	return ret;
	222	}
	223
b41a2cd1	224	int serial_can_receive(SerialState *s)
80cabfad	225	{
80cabfad FB	226	return !(s->lsr & UART_LSR_DR);
	227	}
	228
b41a2cd1	229	void serial_receive_byte(SerialState *s, int ch)
80cabfad	230	{
80cabfad FB	231	s->rbr = ch;
80cabfad FB	232	s->lsr \|= UART_LSR_DR;
b41a2cd1	233	serial_update_irq(s);
80cabfad FB	234	}
80cabfad FB	235
b41a2cd1	236	void serial_receive_break(SerialState *s)
80cabfad	237	{
80cabfad FB	238	s->rbr = 0;
80cabfad FB	239	s->lsr \|= UART_LSR_BI \| UART_LSR_DR;
b41a2cd1	240	serial_update_irq(s);
80cabfad FB	241	}
80cabfad FB	242
b41a2cd1	243	static int serial_can_receive1(void *opaque)
80cabfad	244	{
b41a2cd1 FB	245	SerialState *s = opaque;
	246	return serial_can_receive(s);
	247	}
	248
	249	static void serial_receive1(void opaque, const uint8_t buf, int size)
	250	{
	251	SerialState *s = opaque;
	252	serial_receive_byte(s, buf[0]);
	253	}
80cabfad	254
b41a2cd1 FB	255	/* If fd is zero, it means that the serial device uses the console */
	256	SerialState *serial_init(int base, int irq, int fd)
	257	{
	258	SerialState *s;
	259
	260	s = qemu_mallocz(sizeof(SerialState));
	261	if (!s)
	262	return NULL;
80cabfad FB	263	s->irq = irq;
	264	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
	265	s->iir = UART_IIR_NO_INT;
b41a2cd1 FB	266
	267	register_ioport_write(base, 8, 1, serial_ioport_write, s);
	268	register_ioport_read(base, 8, 1, serial_ioport_read, s);
	269
	270	if (fd != 0) {
b0a21b53	271	qemu_add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s);
b41a2cd1 FB	272	s->out_fd = fd;
	273	} else {
	274	serial_console = s;
	275	s->out_fd = 1;
	276	}
	277	return s;
80cabfad	278	}