[qemu.git] / hw / serial.c

/*
 * QEMU 16450 UART emulation
 * 
 * Copyright (c) 2003-2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <getopt.h>
#include <inttypes.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <malloc.h>
#include <termios.h>
#include <sys/poll.h>
#include <errno.h>
#include <sys/wait.h>
#include <netinet/in.h>

#include "cpu.h"
#include "vl.h"

//#define DEBUG_SERIAL

#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */

#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
#define UART_MCR_OUT2	0x08	/* Out2 complement */
#define UART_MCR_OUT1	0x04	/* Out1 complement */
#define UART_MCR_RTS	0x02	/* RTS complement */
#define UART_MCR_DTR	0x01	/* DTR complement */

/*
 * These are the definitions for the Modem Status Register
 */
#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
#define UART_MSR_RI	0x40	/* Ring Indicator */
#define UART_MSR_DSR	0x20	/* Data Set Ready */
#define UART_MSR_CTS	0x10	/* Clear to Send */
#define UART_MSR_DDCD	0x08	/* Delta DCD */
#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02	/* Delta DSR */
#define UART_MSR_DCTS	0x01	/* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */

#define UART_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_LSR_FE	0x08	/* Frame error indicator */
#define UART_LSR_PE	0x04	/* Parity error indicator */
#define UART_LSR_OE	0x02	/* Overrun error indicator */
#define UART_LSR_DR	0x01	/* Receiver data ready */

typedef struct SerialState {
    uint8_t divider;
    uint8_t rbr; /* receive register */
    uint8_t ier;
    uint8_t iir; /* read only */
    uint8_t lcr;
    uint8_t mcr;
    uint8_t lsr; /* read only */
    uint8_t msr;
    uint8_t scr;
    /* NOTE: this hidden state is necessary for tx irq generation as
       it can be reset while reading iir */
    int thr_ipending;
    int irq;
} SerialState;

SerialState serial_ports[1];

void serial_update_irq(void)
{
    SerialState *s = &serial_ports[0];

    if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
        s->iir = UART_IIR_RDI;
    } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
        s->iir = UART_IIR_THRI;
    } else {
        s->iir = UART_IIR_NO_INT;
    }
    if (s->iir != UART_IIR_NO_INT) {
        pic_set_irq(s->irq, 1);
    } else {
        pic_set_irq(s->irq, 0);
    }
}

void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
{
    SerialState *s = &serial_ports[0];
    unsigned char ch;
    int ret;
    
    addr &= 7;
#ifdef DEBUG_SERIAL
    printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0xff00) | val;
        } else {
            s->thr_ipending = 0;
            s->lsr &= ~UART_LSR_THRE;
            serial_update_irq();

            ch = val;
            do {
                ret = write(1, &ch, 1);
            } while (ret != 1);
            s->thr_ipending = 1;
            s->lsr |= UART_LSR_THRE;
            s->lsr |= UART_LSR_TEMT;
            serial_update_irq();
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0x00ff) | (val << 8);
        } else {
            s->ier = val;
            serial_update_irq();
        }
        break;
    case 2:
        break;
    case 3:
        s->lcr = val;
        break;
    case 4:
        s->mcr = val;
        break;
    case 5:
        break;
    case 6:
        s->msr = val;
        break;
    case 7:
        s->scr = val;
        break;
    }
}

uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
{
    SerialState *s = &serial_ports[0];
    uint32_t ret;

    addr &= 7;
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            ret = s->divider & 0xff; 
        } else {
            ret = s->rbr;
            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
            serial_update_irq();
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            ret = (s->divider >> 8) & 0xff;
        } else {
            ret = s->ier;
        }
        break;
    case 2:
        ret = s->iir;
        /* reset THR pending bit */
        if ((ret & 0x7) == UART_IIR_THRI)
            s->thr_ipending = 0;
        serial_update_irq();
        break;
    case 3:
        ret = s->lcr;
        break;
    case 4:
        ret = s->mcr;
        break;
    case 5:
        ret = s->lsr;
        break;
    case 6:
        if (s->mcr & UART_MCR_LOOP) {
            /* in loopback, the modem output pins are connected to the
               inputs */
            ret = (s->mcr & 0x0c) << 4;
            ret |= (s->mcr & 0x02) << 3;
            ret |= (s->mcr & 0x01) << 5;
        } else {
            ret = s->msr;
        }
        break;
    case 7:
        ret = s->scr;
        break;
    }
#ifdef DEBUG_SERIAL
    printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

int serial_can_receive(void)
{
    SerialState *s = &serial_ports[0];
    return !(s->lsr & UART_LSR_DR);
}

void serial_receive_byte(int ch)
{
    SerialState *s = &serial_ports[0];

    s->rbr = ch;
    s->lsr |= UART_LSR_DR;
    serial_update_irq();
}

void serial_receive_break(void)
{
    SerialState *s = &serial_ports[0];

    s->rbr = 0;
    s->lsr |= UART_LSR_BI | UART_LSR_DR;
    serial_update_irq();
}

void serial_init(int base, int irq)
{
    SerialState *s = &serial_ports[0];

    s->irq = irq;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->iir = UART_IIR_NO_INT;
    
    register_ioport_write(base, 8, serial_ioport_write, 1);
    register_ioport_read(base, 8, serial_ioport_read, 1);
}
Commit	Line	Data
80cabfad FB	1	/*
	2	* QEMU 16450 UART emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include <stdlib.h>
	25	#include <stdio.h>
	26	#include <stdarg.h>
	27	#include <string.h>
	28	#include <getopt.h>
	29	#include <inttypes.h>
	30	#include <unistd.h>
	31	#include <sys/mman.h>
	32	#include <fcntl.h>
	33	#include <signal.h>
	34	#include <time.h>
	35	#include <sys/time.h>
	36	#include <malloc.h>
	37	#include <termios.h>
	38	#include <sys/poll.h>
	39	#include <errno.h>
	40	#include <sys/wait.h>
	41	#include <netinet/in.h>
	42
	43	#include "cpu.h"
	44	#include "vl.h"
	45
	46	//#define DEBUG_SERIAL
	47
	48	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	49
	50	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
	51	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
	52	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
	53	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
	54
	55	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
	56	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
	57
	58	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
	59	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
	60	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
	61	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
	62
	63	/*
	64	* These are the definitions for the Modem Control Register
65	*/
66	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
67	#define UART_MCR_OUT2 0x08 /* Out2 complement */
68	#define UART_MCR_OUT1 0x04 /* Out1 complement */
69	#define UART_MCR_RTS 0x02 /* RTS complement */
70	#define UART_MCR_DTR 0x01 /* DTR complement */
71
72	/*
73	* These are the definitions for the Modem Status Register
74	*/
75	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
76	#define UART_MSR_RI 0x40 /* Ring Indicator */
77	#define UART_MSR_DSR 0x20 /* Data Set Ready */
78	#define UART_MSR_CTS 0x10 /* Clear to Send */
79	#define UART_MSR_DDCD 0x08 /* Delta DCD */
80	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
81	#define UART_MSR_DDSR 0x02 /* Delta DSR */
82	#define UART_MSR_DCTS 0x01 /* Delta CTS */
83	#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
84
85	#define UART_LSR_TEMT 0x40 /* Transmitter empty */
86	#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
87	#define UART_LSR_BI 0x10 /* Break interrupt indicator */
88	#define UART_LSR_FE 0x08 /* Frame error indicator */
89	#define UART_LSR_PE 0x04 /* Parity error indicator */
90	#define UART_LSR_OE 0x02 /* Overrun error indicator */
91	#define UART_LSR_DR 0x01 /* Receiver data ready */
92
93	typedef struct SerialState {
94	uint8_t divider;
95	uint8_t rbr; /* receive register */
96	uint8_t ier;
97	uint8_t iir; /* read only */
98	uint8_t lcr;
99	uint8_t mcr;
100	uint8_t lsr; /* read only */
101	uint8_t msr;
102	uint8_t scr;
103	/* NOTE: this hidden state is necessary for tx irq generation as
104	it can be reset while reading iir */
105	int thr_ipending;
106	int irq;
107	} SerialState;
108
109	SerialState serial_ports[1];
110
111	void serial_update_irq(void)
112	{
113	SerialState *s = &serial_ports[0];
114
115	if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
116	s->iir = UART_IIR_RDI;
117	} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
118	s->iir = UART_IIR_THRI;
119	} else {
120	s->iir = UART_IIR_NO_INT;
121	}
122	if (s->iir != UART_IIR_NO_INT) {
123	pic_set_irq(s->irq, 1);
124	} else {
125	pic_set_irq(s->irq, 0);
126	}
127	}
128
129	void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
130	{
131	SerialState *s = &serial_ports[0];
132	unsigned char ch;
133	int ret;
134
135	addr &= 7;
136	#ifdef DEBUG_SERIAL
137	printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
138	#endif
139	switch(addr) {
140	default:
141	case 0:
142	if (s->lcr & UART_LCR_DLAB) {
143	s->divider = (s->divider & 0xff00) \| val;
144	} else {
145	s->thr_ipending = 0;
146	s->lsr &= ~UART_LSR_THRE;
147	serial_update_irq();
148
149	ch = val;
150	do {
151	ret = write(1, &ch, 1);
152	} while (ret != 1);
153	s->thr_ipending = 1;
154	s->lsr \|= UART_LSR_THRE;
155	s->lsr \|= UART_LSR_TEMT;
156	serial_update_irq();
157	}
158	break;
159	case 1:
160	if (s->lcr & UART_LCR_DLAB) {
161	s->divider = (s->divider & 0x00ff) \| (val << 8);
162	} else {
163	s->ier = val;
164	serial_update_irq();
165	}
166	break;
167	case 2:
168	break;
169	case 3:
170	s->lcr = val;
171	break;
172	case 4:
173	s->mcr = val;
174	break;
175	case 5:
176	break;
177	case 6:
178	s->msr = val;
179	break;
180	case 7:
181	s->scr = val;
182	break;
183	}
184	}
185
186	uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
187	{
188	SerialState *s = &serial_ports[0];
189	uint32_t ret;
190
191	addr &= 7;
192	switch(addr) {
193	default:
194	case 0:
195	if (s->lcr & UART_LCR_DLAB) {
196	ret = s->divider & 0xff;
197	} else {
198	ret = s->rbr;
199	s->lsr &= ~(UART_LSR_DR \| UART_LSR_BI);
200	serial_update_irq();
201	}
202	break;
203	case 1:
204	if (s->lcr & UART_LCR_DLAB) {
205	ret = (s->divider >> 8) & 0xff;
206	} else {
207	ret = s->ier;
208	}
209	break;
210	case 2:
211	ret = s->iir;
212	/* reset THR pending bit */
213	if ((ret & 0x7) == UART_IIR_THRI)
214	s->thr_ipending = 0;
215	serial_update_irq();
216	break;
217	case 3:
218	ret = s->lcr;
219	break;
220	case 4:
221	ret = s->mcr;
222	break;
223	case 5:
224	ret = s->lsr;
225	break;
226	case 6:
227	if (s->mcr & UART_MCR_LOOP) {
228	/* in loopback, the modem output pins are connected to the
229	inputs */
230	ret = (s->mcr & 0x0c) << 4;
231	ret \|= (s->mcr & 0x02) << 3;
232	ret \|= (s->mcr & 0x01) << 5;
233	} else {
234	ret = s->msr;
235	}
236	break;
237	case 7:
238	ret = s->scr;
239	break;
240	}
241	#ifdef DEBUG_SERIAL
242	printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
243	#endif
244	return ret;
245	}
246
247	int serial_can_receive(void)
248	{
249	SerialState *s = &serial_ports[0];
250	return !(s->lsr & UART_LSR_DR);
251	}
252
253	void serial_receive_byte(int ch)
254	{
255	SerialState *s = &serial_ports[0];
256
257	s->rbr = ch;
258	s->lsr \|= UART_LSR_DR;
259	serial_update_irq();
260	}
261
262	void serial_receive_break(void)
263	{
264	SerialState *s = &serial_ports[0];
265
266	s->rbr = 0;
267	s->lsr \|= UART_LSR_BI \| UART_LSR_DR;
268	serial_update_irq();
269	}
270
271	void serial_init(int base, int irq)
272	{
273	SerialState *s = &serial_ports[0];
274
275	s->irq = irq;
276	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
277	s->iir = UART_IIR_NO_INT;
278
279	register_ioport_write(base, 8, serial_ioport_write, 1);
280	register_ioport_read(base, 8, serial_ioport_read, 1);
281	}