[qemu.git] / hw / serial.c

/*
 * QEMU 16450 UART emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "qemu-char.h"
#include "isa.h"
#include "pc.h"

//#define DEBUG_SERIAL

#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */

#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
#define UART_MCR_OUT2	0x08	/* Out2 complement */
#define UART_MCR_OUT1	0x04	/* Out1 complement */
#define UART_MCR_RTS	0x02	/* RTS complement */
#define UART_MCR_DTR	0x01	/* DTR complement */

/*
 * These are the definitions for the Modem Status Register
 */
#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
#define UART_MSR_RI	0x40	/* Ring Indicator */
#define UART_MSR_DSR	0x20	/* Data Set Ready */
#define UART_MSR_CTS	0x10	/* Clear to Send */
#define UART_MSR_DDCD	0x08	/* Delta DCD */
#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02	/* Delta DSR */
#define UART_MSR_DCTS	0x01	/* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */

#define UART_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_LSR_FE	0x08	/* Frame error indicator */
#define UART_LSR_PE	0x04	/* Parity error indicator */
#define UART_LSR_OE	0x02	/* Overrun error indicator */
#define UART_LSR_DR	0x01	/* Receiver data ready */

struct SerialState {
    uint16_t divider;
    uint8_t rbr; /* receive register */
    uint8_t ier;
    uint8_t iir; /* read only */
    uint8_t lcr;
    uint8_t mcr;
    uint8_t lsr; /* read only */
    uint8_t msr; /* read only */
    uint8_t scr;
    /* NOTE: this hidden state is necessary for tx irq generation as
       it can be reset while reading iir */
    int thr_ipending;
    qemu_irq irq;
    CharDriverState *chr;
    int last_break_enable;
    target_phys_addr_t base;
    int it_shift;
};

static void serial_update_irq(SerialState *s)
{
    if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
        s->iir = UART_IIR_RDI;
    } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
        s->iir = UART_IIR_THRI;
    } else {
        s->iir = UART_IIR_NO_INT;
    }
    if (s->iir != UART_IIR_NO_INT) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static void serial_update_parameters(SerialState *s)
{
    int speed, parity, data_bits, stop_bits;
    QEMUSerialSetParams ssp;

    if (s->lcr & 0x08) {
        if (s->lcr & 0x10)
            parity = 'E';
        else
            parity = 'O';
    } else {
            parity = 'N';
    }
    if (s->lcr & 0x04)
        stop_bits = 2;
    else
        stop_bits = 1;
    data_bits = (s->lcr & 0x03) + 5;
    if (s->divider == 0)
        return;
    speed = 115200 / s->divider;
    ssp.speed = speed;
    ssp.parity = parity;
    ssp.data_bits = data_bits;
    ssp.stop_bits = stop_bits;
    qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
#if 0
    printf("speed=%d parity=%c data=%d stop=%d\n",
           speed, parity, data_bits, stop_bits);
#endif
}

static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    SerialState *s = opaque;
    unsigned char ch;

    addr &= 7;
#ifdef DEBUG_SERIAL
    printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0xff00) | val;
            serial_update_parameters(s);
        } else {
            s->thr_ipending = 0;
            s->lsr &= ~UART_LSR_THRE;
            serial_update_irq(s);
            ch = val;
            qemu_chr_write(s->chr, &ch, 1);
            s->thr_ipending = 1;
            s->lsr |= UART_LSR_THRE;
            s->lsr |= UART_LSR_TEMT;
            serial_update_irq(s);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0x00ff) | (val << 8);
            serial_update_parameters(s);
        } else {
            s->ier = val & 0x0f;
            if (s->lsr & UART_LSR_THRE) {
                s->thr_ipending = 1;
            }
            serial_update_irq(s);
        }
        break;
    case 2:
        break;
    case 3:
        {
            int break_enable;
            s->lcr = val;
            serial_update_parameters(s);
            break_enable = (val >> 6) & 1;
            if (break_enable != s->last_break_enable) {
                s->last_break_enable = break_enable;
                qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
                               &break_enable);
            }
        }
        break;
    case 4:
        s->mcr = val & 0x1f;
        break;
    case 5:
        break;
    case 6:
        break;
    case 7:
        s->scr = val;
        break;
    }
}

static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
{
    SerialState *s = opaque;
    uint32_t ret;

    addr &= 7;
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            ret = s->divider & 0xff;
        } else {
            ret = s->rbr;
            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
            serial_update_irq(s);
            qemu_chr_accept_input(s->chr);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            ret = (s->divider >> 8) & 0xff;
        } else {
            ret = s->ier;
        }
        break;
    case 2:
        ret = s->iir;
        /* reset THR pending bit */
        if ((ret & 0x7) == UART_IIR_THRI)
            s->thr_ipending = 0;
        serial_update_irq(s);
        break;
    case 3:
        ret = s->lcr;
        break;
    case 4:
        ret = s->mcr;
        break;
    case 5:
        ret = s->lsr;
        break;
    case 6:
        if (s->mcr & UART_MCR_LOOP) {
            /* in loopback, the modem output pins are connected to the
               inputs */
            ret = (s->mcr & 0x0c) << 4;
            ret |= (s->mcr & 0x02) << 3;
            ret |= (s->mcr & 0x01) << 5;
        } else {
            ret = s->msr;
        }
        break;
    case 7:
        ret = s->scr;
        break;
    }
#ifdef DEBUG_SERIAL
    printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static int serial_can_receive(SerialState *s)
{
    return !(s->lsr & UART_LSR_DR);
}

static void serial_receive_byte(SerialState *s, int ch)
{
    s->rbr = ch;
    s->lsr |= UART_LSR_DR;
    serial_update_irq(s);
}

static void serial_receive_break(SerialState *s)
{
    s->rbr = 0;
    s->lsr |= UART_LSR_BI | UART_LSR_DR;
    serial_update_irq(s);
}

static int serial_can_receive1(void *opaque)
{
    SerialState *s = opaque;
    return serial_can_receive(s);
}

static void serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    SerialState *s = opaque;
    serial_receive_byte(s, buf[0]);
}

static void serial_event(void *opaque, int event)
{
    SerialState *s = opaque;
    if (event == CHR_EVENT_BREAK)
        serial_receive_break(s);
}

static void serial_save(QEMUFile *f, void *opaque)
{
    SerialState *s = opaque;

    qemu_put_be16s(f,&s->divider);
    qemu_put_8s(f,&s->rbr);
    qemu_put_8s(f,&s->ier);
    qemu_put_8s(f,&s->iir);
    qemu_put_8s(f,&s->lcr);
    qemu_put_8s(f,&s->mcr);
    qemu_put_8s(f,&s->lsr);
    qemu_put_8s(f,&s->msr);
    qemu_put_8s(f,&s->scr);
}

static int serial_load(QEMUFile *f, void *opaque, int version_id)
{
    SerialState *s = opaque;

    if(version_id > 2)
        return -EINVAL;

    if (version_id >= 2)
        qemu_get_be16s(f, &s->divider);
    else
        s->divider = qemu_get_byte(f);
    qemu_get_8s(f,&s->rbr);
    qemu_get_8s(f,&s->ier);
    qemu_get_8s(f,&s->iir);
    qemu_get_8s(f,&s->lcr);
    qemu_get_8s(f,&s->mcr);
    qemu_get_8s(f,&s->lsr);
    qemu_get_8s(f,&s->msr);
    qemu_get_8s(f,&s->scr);

    return 0;
}

/* If fd is zero, it means that the serial device uses the console */
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
{
    SerialState *s;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->irq = irq;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->iir = UART_IIR_NO_INT;
    s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;

    register_savevm("serial", base, 2, serial_save, serial_load, s);

    register_ioport_write(base, 8, 1, serial_ioport_write, s);
    register_ioport_read(base, 8, 1, serial_ioport_read, s);
    s->chr = chr;
    qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
                          serial_event, s);
    return s;
}

/* Memory mapped interface */
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;

    return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
}

void serial_mm_writeb (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;

    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}

uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;
    uint32_t val;

    val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    return val;
}

void serial_mm_writew (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap16(value);
#endif
    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}

uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;
    uint32_t val;

    val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    return val;
}

void serial_mm_writel (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif
    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
}

static CPUReadMemoryFunc *serial_mm_read[] = {
    &serial_mm_readb,
    &serial_mm_readw,
    &serial_mm_readl,
};

static CPUWriteMemoryFunc *serial_mm_write[] = {
    &serial_mm_writeb,
    &serial_mm_writew,
    &serial_mm_writel,
};

SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
                             qemu_irq irq, CharDriverState *chr,
                             int ioregister)
{
    SerialState *s;
    int s_io_memory;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->irq = irq;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->iir = UART_IIR_NO_INT;
    s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
    s->base = base;
    s->it_shift = it_shift;

    register_savevm("serial", base, 2, serial_save, serial_load, s);

    if (ioregister) {
        s_io_memory = cpu_register_io_memory(0, serial_mm_read,
                                             serial_mm_write, s);
        cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
    }
    s->chr = chr;
    qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
                          serial_event, s);
    return s;
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU 16450 UART emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "qemu-char.h"
	26	#include "isa.h"
	27	#include "pc.h"
80cabfad FB	28
	29	//#define DEBUG_SERIAL
	30
	31	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	32
	33	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
	34	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
	35	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
	36	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
	37
	38	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
	39	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
	40
	41	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
	42	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
	43	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
	44	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
	45
	46	/*
	47	* These are the definitions for the Modem Control Register
	48	*/
	49	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
	50	#define UART_MCR_OUT2 0x08 /* Out2 complement */
	51	#define UART_MCR_OUT1 0x04 /* Out1 complement */
	52	#define UART_MCR_RTS 0x02 /* RTS complement */
	53	#define UART_MCR_DTR 0x01 /* DTR complement */
	54
	55	/*
	56	* These are the definitions for the Modem Status Register
	57	*/
	58	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
	59	#define UART_MSR_RI 0x40 /* Ring Indicator */
	60	#define UART_MSR_DSR 0x20 /* Data Set Ready */
	61	#define UART_MSR_CTS 0x10 /* Clear to Send */
	62	#define UART_MSR_DDCD 0x08 /* Delta DCD */
	63	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
	64	#define UART_MSR_DDSR 0x02 /* Delta DSR */
	65	#define UART_MSR_DCTS 0x01 /* Delta CTS */
	66	#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
	67
	68	#define UART_LSR_TEMT 0x40 /* Transmitter empty */
	69	#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
	70	#define UART_LSR_BI 0x10 /* Break interrupt indicator */
	71	#define UART_LSR_FE 0x08 /* Frame error indicator */
	72	#define UART_LSR_PE 0x04 /* Parity error indicator */
	73	#define UART_LSR_OE 0x02 /* Overrun error indicator */
	74	#define UART_LSR_DR 0x01 /* Receiver data ready */
	75
b41a2cd1	76	struct SerialState {
508d92d0	77	uint16_t divider;
80cabfad FB	78	uint8_t rbr; /* receive register */
	79	uint8_t ier;
	80	uint8_t iir; /* read only */
	81	uint8_t lcr;
	82	uint8_t mcr;
	83	uint8_t lsr; /* read only */
3e749fe1	84	uint8_t msr; /* read only */
80cabfad FB	85	uint8_t scr;
	86	/* NOTE: this hidden state is necessary for tx irq generation as
	87	it can be reset while reading iir */
	88	int thr_ipending;
d537cf6c	89	qemu_irq irq;
82c643ff	90	CharDriverState *chr;
f8d179e3	91	int last_break_enable;
71db710f	92	target_phys_addr_t base;
e5d13e2f	93	int it_shift;
b41a2cd1	94	};
80cabfad	95
b41a2cd1	96	static void serial_update_irq(SerialState *s)
80cabfad	97	{
80cabfad FB	98	if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
	99	s->iir = UART_IIR_RDI;
	100	} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
	101	s->iir = UART_IIR_THRI;
	102	} else {
	103	s->iir = UART_IIR_NO_INT;
	104	}
	105	if (s->iir != UART_IIR_NO_INT) {
d537cf6c	106	qemu_irq_raise(s->irq);
80cabfad	107	} else {
d537cf6c	108	qemu_irq_lower(s->irq);
80cabfad FB	109	}
	110	}
	111
f8d179e3 FB	112	static void serial_update_parameters(SerialState *s)
	113	{
	114	int speed, parity, data_bits, stop_bits;
2122c51a	115	QEMUSerialSetParams ssp;
f8d179e3 FB	116
	117	if (s->lcr & 0x08) {
	118	if (s->lcr & 0x10)
	119	parity = 'E';
	120	else
	121	parity = 'O';
	122	} else {
	123	parity = 'N';
	124	}
5fafdf24	125	if (s->lcr & 0x04)
f8d179e3 FB	126	stop_bits = 2;
	127	else
	128	stop_bits = 1;
	129	data_bits = (s->lcr & 0x03) + 5;
	130	if (s->divider == 0)
	131	return;
	132	speed = 115200 / s->divider;
2122c51a FB	133	ssp.speed = speed;
	134	ssp.parity = parity;
	135	ssp.data_bits = data_bits;
	136	ssp.stop_bits = stop_bits;
	137	qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
	138	#if 0
5fafdf24	139	printf("speed=%d parity=%c data=%d stop=%d\n",
f8d179e3 FB	140	speed, parity, data_bits, stop_bits);
	141	#endif
	142	}
	143
b41a2cd1	144	static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	145	{
b41a2cd1	146	SerialState *s = opaque;
80cabfad	147	unsigned char ch;
3b46e624	148
80cabfad FB	149	addr &= 7;
	150	#ifdef DEBUG_SERIAL
	151	printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
	152	#endif
	153	switch(addr) {
	154	default:
	155	case 0:
	156	if (s->lcr & UART_LCR_DLAB) {
	157	s->divider = (s->divider & 0xff00) \| val;
f8d179e3	158	serial_update_parameters(s);
80cabfad FB	159	} else {
	160	s->thr_ipending = 0;
	161	s->lsr &= ~UART_LSR_THRE;
b41a2cd1	162	serial_update_irq(s);
82c643ff FB	163	ch = val;
82c643ff FB	164	qemu_chr_write(s->chr, &ch, 1);
80cabfad FB	165	s->thr_ipending = 1;
	166	s->lsr \|= UART_LSR_THRE;
	167	s->lsr \|= UART_LSR_TEMT;
b41a2cd1	168	serial_update_irq(s);
80cabfad FB	169	}
	170	break;
	171	case 1:
	172	if (s->lcr & UART_LCR_DLAB) {
	173	s->divider = (s->divider & 0x00ff) \| (val << 8);
f8d179e3	174	serial_update_parameters(s);
80cabfad	175	} else {
60e336db FB	176	s->ier = val & 0x0f;
	177	if (s->lsr & UART_LSR_THRE) {
	178	s->thr_ipending = 1;
	179	}
b41a2cd1	180	serial_update_irq(s);
80cabfad FB	181	}
	182	break;
	183	case 2:
	184	break;
	185	case 3:
f8d179e3 FB	186	{
	187	int break_enable;
	188	s->lcr = val;
	189	serial_update_parameters(s);
	190	break_enable = (val >> 6) & 1;
	191	if (break_enable != s->last_break_enable) {
	192	s->last_break_enable = break_enable;
5fafdf24	193	qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
2122c51a	194	&break_enable);
f8d179e3 FB	195	}
f8d179e3 FB	196	}
80cabfad FB	197	break;
80cabfad FB	198	case 4:
60e336db	199	s->mcr = val & 0x1f;
80cabfad FB	200	break;
	201	case 5:
	202	break;
	203	case 6:
80cabfad FB	204	break;
	205	case 7:
	206	s->scr = val;
	207	break;
	208	}
	209	}
	210
b41a2cd1	211	static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
80cabfad	212	{
b41a2cd1	213	SerialState *s = opaque;
80cabfad FB	214	uint32_t ret;
	215
	216	addr &= 7;
	217	switch(addr) {
	218	default:
	219	case 0:
	220	if (s->lcr & UART_LCR_DLAB) {
5fafdf24	221	ret = s->divider & 0xff;
80cabfad FB	222	} else {
	223	ret = s->rbr;
	224	s->lsr &= ~(UART_LSR_DR \| UART_LSR_BI);
b41a2cd1	225	serial_update_irq(s);
bd9bdce6	226	qemu_chr_accept_input(s->chr);
80cabfad FB	227	}
	228	break;
	229	case 1:
	230	if (s->lcr & UART_LCR_DLAB) {
	231	ret = (s->divider >> 8) & 0xff;
	232	} else {
	233	ret = s->ier;
	234	}
	235	break;
	236	case 2:
	237	ret = s->iir;
	238	/* reset THR pending bit */
	239	if ((ret & 0x7) == UART_IIR_THRI)
	240	s->thr_ipending = 0;
b41a2cd1	241	serial_update_irq(s);
80cabfad FB	242	break;
	243	case 3:
	244	ret = s->lcr;
	245	break;
	246	case 4:
	247	ret = s->mcr;
	248	break;
	249	case 5:
	250	ret = s->lsr;
	251	break;
	252	case 6:
	253	if (s->mcr & UART_MCR_LOOP) {
	254	/* in loopback, the modem output pins are connected to the
	255	inputs */
	256	ret = (s->mcr & 0x0c) << 4;
	257	ret \|= (s->mcr & 0x02) << 3;
	258	ret \|= (s->mcr & 0x01) << 5;
	259	} else {
	260	ret = s->msr;
	261	}
	262	break;
	263	case 7:
	264	ret = s->scr;
	265	break;
	266	}
	267	#ifdef DEBUG_SERIAL
	268	printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
	269	#endif
	270	return ret;
	271	}
	272
82c643ff	273	static int serial_can_receive(SerialState *s)
80cabfad	274	{
80cabfad FB	275	return !(s->lsr & UART_LSR_DR);
	276	}
	277
82c643ff	278	static void serial_receive_byte(SerialState *s, int ch)
80cabfad	279	{
80cabfad FB	280	s->rbr = ch;
80cabfad FB	281	s->lsr \|= UART_LSR_DR;
b41a2cd1	282	serial_update_irq(s);
80cabfad FB	283	}
80cabfad FB	284
82c643ff	285	static void serial_receive_break(SerialState *s)
80cabfad	286	{
80cabfad FB	287	s->rbr = 0;
80cabfad FB	288	s->lsr \|= UART_LSR_BI \| UART_LSR_DR;
b41a2cd1	289	serial_update_irq(s);
80cabfad FB	290	}
80cabfad FB	291
b41a2cd1	292	static int serial_can_receive1(void *opaque)
80cabfad	293	{
b41a2cd1 FB	294	SerialState *s = opaque;
	295	return serial_can_receive(s);
	296	}
	297
	298	static void serial_receive1(void opaque, const uint8_t buf, int size)
	299	{
	300	SerialState *s = opaque;
	301	serial_receive_byte(s, buf[0]);
	302	}
80cabfad	303
82c643ff FB	304	static void serial_event(void *opaque, int event)
	305	{
	306	SerialState *s = opaque;
	307	if (event == CHR_EVENT_BREAK)
	308	serial_receive_break(s);
	309	}
	310
8738a8d0 FB	311	static void serial_save(QEMUFile f, void opaque)
	312	{
	313	SerialState *s = opaque;
	314
508d92d0	315	qemu_put_be16s(f,&s->divider);
8738a8d0 FB	316	qemu_put_8s(f,&s->rbr);
	317	qemu_put_8s(f,&s->ier);
	318	qemu_put_8s(f,&s->iir);
	319	qemu_put_8s(f,&s->lcr);
	320	qemu_put_8s(f,&s->mcr);
	321	qemu_put_8s(f,&s->lsr);
	322	qemu_put_8s(f,&s->msr);
	323	qemu_put_8s(f,&s->scr);
	324	}
	325
	326	static int serial_load(QEMUFile f, void opaque, int version_id)
	327	{
	328	SerialState *s = opaque;
	329
508d92d0	330	if(version_id > 2)
8738a8d0 FB	331	return -EINVAL;
8738a8d0 FB	332
508d92d0 FB	333	if (version_id >= 2)
	334	qemu_get_be16s(f, &s->divider);
	335	else
	336	s->divider = qemu_get_byte(f);
8738a8d0 FB	337	qemu_get_8s(f,&s->rbr);
	338	qemu_get_8s(f,&s->ier);
	339	qemu_get_8s(f,&s->iir);
	340	qemu_get_8s(f,&s->lcr);
	341	qemu_get_8s(f,&s->mcr);
	342	qemu_get_8s(f,&s->lsr);
	343	qemu_get_8s(f,&s->msr);
	344	qemu_get_8s(f,&s->scr);
	345
	346	return 0;
	347	}
	348
b41a2cd1	349	/* If fd is zero, it means that the serial device uses the console */
d537cf6c	350	SerialState serial_init(int base, qemu_irq irq, CharDriverState chr)
b41a2cd1 FB	351	{
	352	SerialState *s;
	353
	354	s = qemu_mallocz(sizeof(SerialState));
	355	if (!s)
	356	return NULL;
80cabfad FB	357	s->irq = irq;
	358	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
	359	s->iir = UART_IIR_NO_INT;
3e749fe1	360	s->msr = UART_MSR_DCD \| UART_MSR_DSR \| UART_MSR_CTS;
b41a2cd1	361
508d92d0	362	register_savevm("serial", base, 2, serial_save, serial_load, s);
8738a8d0	363
b41a2cd1 FB	364	register_ioport_write(base, 8, 1, serial_ioport_write, s);
b41a2cd1 FB	365	register_ioport_read(base, 8, 1, serial_ioport_read, s);
82c643ff	366	s->chr = chr;
e5b0bc44 PB	367	qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
e5b0bc44 PB	368	serial_event, s);
b41a2cd1	369	return s;
80cabfad	370	}
e5d13e2f FB	371
e5d13e2f FB	372	/* Memory mapped interface */
a4bc3afc	373	uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
e5d13e2f FB	374	{
	375	SerialState *s = opaque;
	376
	377	return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
	378	}
	379
a4bc3afc TS	380	void serial_mm_writeb (void *opaque,
a4bc3afc TS	381	target_phys_addr_t addr, uint32_t value)
e5d13e2f FB	382	{
	383	SerialState *s = opaque;
	384
	385	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
	386	}
	387
a4bc3afc	388	uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
e5d13e2f FB	389	{
e5d13e2f FB	390	SerialState *s = opaque;
e918ee04	391	uint32_t val;
e5d13e2f	392
e918ee04 TS	393	val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
	394	#ifdef TARGET_WORDS_BIGENDIAN
	395	val = bswap16(val);
	396	#endif
	397	return val;
e5d13e2f FB	398	}
e5d13e2f FB	399
a4bc3afc TS	400	void serial_mm_writew (void *opaque,
a4bc3afc TS	401	target_phys_addr_t addr, uint32_t value)
e5d13e2f FB	402	{
e5d13e2f FB	403	SerialState *s = opaque;
e918ee04 TS	404	#ifdef TARGET_WORDS_BIGENDIAN
	405	value = bswap16(value);
	406	#endif
e5d13e2f FB	407	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
	408	}
	409
a4bc3afc	410	uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
e5d13e2f FB	411	{
e5d13e2f FB	412	SerialState *s = opaque;
e918ee04	413	uint32_t val;
e5d13e2f	414
e918ee04 TS	415	val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
	416	#ifdef TARGET_WORDS_BIGENDIAN
	417	val = bswap32(val);
	418	#endif
	419	return val;
e5d13e2f FB	420	}
e5d13e2f FB	421
a4bc3afc TS	422	void serial_mm_writel (void *opaque,
a4bc3afc TS	423	target_phys_addr_t addr, uint32_t value)
e5d13e2f FB	424	{
e5d13e2f FB	425	SerialState *s = opaque;
e918ee04 TS	426	#ifdef TARGET_WORDS_BIGENDIAN
	427	value = bswap32(value);
	428	#endif
e5d13e2f FB	429	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
	430	}
	431
	432	static CPUReadMemoryFunc *serial_mm_read[] = {
	433	&serial_mm_readb,
	434	&serial_mm_readw,
	435	&serial_mm_readl,
	436	};
	437
	438	static CPUWriteMemoryFunc *serial_mm_write[] = {
	439	&serial_mm_writeb,
	440	&serial_mm_writew,
	441	&serial_mm_writel,
	442	};
	443
71db710f	444	SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
d537cf6c	445	qemu_irq irq, CharDriverState *chr,
a4bc3afc	446	int ioregister)
e5d13e2f FB	447	{
	448	SerialState *s;
	449	int s_io_memory;
	450
	451	s = qemu_mallocz(sizeof(SerialState));
	452	if (!s)
	453	return NULL;
e5d13e2f FB	454	s->irq = irq;
	455	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
	456	s->iir = UART_IIR_NO_INT;
3e749fe1	457	s->msr = UART_MSR_DCD \| UART_MSR_DSR \| UART_MSR_CTS;
e5d13e2f FB	458	s->base = base;
	459	s->it_shift = it_shift;
	460
508d92d0	461	register_savevm("serial", base, 2, serial_save, serial_load, s);
e5d13e2f	462
a4bc3afc TS	463	if (ioregister) {
	464	s_io_memory = cpu_register_io_memory(0, serial_mm_read,
	465	serial_mm_write, s);
	466	cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
	467	}
e5d13e2f	468	s->chr = chr;
e5b0bc44 PB	469	qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
e5b0bc44 PB	470	serial_event, s);
e5d13e2f FB	471	return s;
e5d13e2f FB	472	}