[qemu.git] / hw / serial.c

/*
 * QEMU 16450 UART emulation
 * 
 * Copyright (c) 2003-2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_SERIAL

#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */

#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
#define UART_MCR_OUT2	0x08	/* Out2 complement */
#define UART_MCR_OUT1	0x04	/* Out1 complement */
#define UART_MCR_RTS	0x02	/* RTS complement */
#define UART_MCR_DTR	0x01	/* DTR complement */

/*
 * These are the definitions for the Modem Status Register
 */
#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
#define UART_MSR_RI	0x40	/* Ring Indicator */
#define UART_MSR_DSR	0x20	/* Data Set Ready */
#define UART_MSR_CTS	0x10	/* Clear to Send */
#define UART_MSR_DDCD	0x08	/* Delta DCD */
#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02	/* Delta DSR */
#define UART_MSR_DCTS	0x01	/* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */

#define UART_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_LSR_FE	0x08	/* Frame error indicator */
#define UART_LSR_PE	0x04	/* Parity error indicator */
#define UART_LSR_OE	0x02	/* Overrun error indicator */
#define UART_LSR_DR	0x01	/* Receiver data ready */

struct SerialState {
    uint16_t divider;
    uint8_t rbr; /* receive register */
    uint8_t ier;
    uint8_t iir; /* read only */
    uint8_t lcr;
    uint8_t mcr;
    uint8_t lsr; /* read only */
    uint8_t msr; /* read only */
    uint8_t scr;
    /* NOTE: this hidden state is necessary for tx irq generation as
       it can be reset while reading iir */
    int thr_ipending;
    SetIRQFunc *set_irq;
    void *irq_opaque;
    int irq;
    CharDriverState *chr;
    int last_break_enable;
    target_ulong base;
    int it_shift;
};

static void serial_update_irq(SerialState *s)
{
    if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
        s->iir = UART_IIR_RDI;
    } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
        s->iir = UART_IIR_THRI;
    } else {
        s->iir = UART_IIR_NO_INT;
    }
    if (s->iir != UART_IIR_NO_INT) {
        s->set_irq(s->irq_opaque, s->irq, 1);
    } else {
        s->set_irq(s->irq_opaque, s->irq, 0);
    }
}

static void serial_update_parameters(SerialState *s)
{
    int speed, parity, data_bits, stop_bits;
    QEMUSerialSetParams ssp;

    if (s->lcr & 0x08) {
        if (s->lcr & 0x10)
            parity = 'E';
        else
            parity = 'O';
    } else {
            parity = 'N';
    }
    if (s->lcr & 0x04) 
        stop_bits = 2;
    else
        stop_bits = 1;
    data_bits = (s->lcr & 0x03) + 5;
    if (s->divider == 0)
        return;
    speed = 115200 / s->divider;
    ssp.speed = speed;
    ssp.parity = parity;
    ssp.data_bits = data_bits;
    ssp.stop_bits = stop_bits;
    qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
#if 0
    printf("speed=%d parity=%c data=%d stop=%d\n", 
           speed, parity, data_bits, stop_bits);
#endif
}

static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    SerialState *s = opaque;
    unsigned char ch;
    
    addr &= 7;
#ifdef DEBUG_SERIAL
    printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0xff00) | val;
            serial_update_parameters(s);
        } else {
            s->thr_ipending = 0;
            s->lsr &= ~UART_LSR_THRE;
            serial_update_irq(s);
            ch = val;
            qemu_chr_write(s->chr, &ch, 1);
            s->thr_ipending = 1;
            s->lsr |= UART_LSR_THRE;
            s->lsr |= UART_LSR_TEMT;
            serial_update_irq(s);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0x00ff) | (val << 8);
            serial_update_parameters(s);
        } else {
            s->ier = val & 0x0f;
            if (s->lsr & UART_LSR_THRE) {
                s->thr_ipending = 1;
            }
            serial_update_irq(s);
        }
        break;
    case 2:
        break;
    case 3:
        {
            int break_enable;
            s->lcr = val;
            serial_update_parameters(s);
            break_enable = (val >> 6) & 1;
            if (break_enable != s->last_break_enable) {
                s->last_break_enable = break_enable;
                qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 
                               &break_enable);
            }
        }
        break;
    case 4:
        s->mcr = val & 0x1f;
        break;
    case 5:
        break;
    case 6:
        break;
    case 7:
        s->scr = val;
        break;
    }
}

static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
{
    SerialState *s = opaque;
    uint32_t ret;

    addr &= 7;
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            ret = s->divider & 0xff; 
        } else {
            ret = s->rbr;
            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
            serial_update_irq(s);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            ret = (s->divider >> 8) & 0xff;
        } else {
            ret = s->ier;
        }
        break;
    case 2:
        ret = s->iir;
        /* reset THR pending bit */
        if ((ret & 0x7) == UART_IIR_THRI)
            s->thr_ipending = 0;
        serial_update_irq(s);
        break;
    case 3:
        ret = s->lcr;
        break;
    case 4:
        ret = s->mcr;
        break;
    case 5:
        ret = s->lsr;
        break;
    case 6:
        if (s->mcr & UART_MCR_LOOP) {
            /* in loopback, the modem output pins are connected to the
               inputs */
            ret = (s->mcr & 0x0c) << 4;
            ret |= (s->mcr & 0x02) << 3;
            ret |= (s->mcr & 0x01) << 5;
        } else {
            ret = s->msr;
        }
        break;
    case 7:
        ret = s->scr;
        break;
    }
#ifdef DEBUG_SERIAL
    printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static int serial_can_receive(SerialState *s)
{
    return !(s->lsr & UART_LSR_DR);
}

static void serial_receive_byte(SerialState *s, int ch)
{
    s->rbr = ch;
    s->lsr |= UART_LSR_DR;
    serial_update_irq(s);
}

static void serial_receive_break(SerialState *s)
{
    s->rbr = 0;
    s->lsr |= UART_LSR_BI | UART_LSR_DR;
    serial_update_irq(s);
}

static int serial_can_receive1(void *opaque)
{
    SerialState *s = opaque;
    return serial_can_receive(s);
}

static void serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    SerialState *s = opaque;
    serial_receive_byte(s, buf[0]);
}

static void serial_event(void *opaque, int event)
{
    SerialState *s = opaque;
    if (event == CHR_EVENT_BREAK)
        serial_receive_break(s);
}

static void serial_save(QEMUFile *f, void *opaque)
{
    SerialState *s = opaque;

    qemu_put_be16s(f,&s->divider);
    qemu_put_8s(f,&s->rbr);
    qemu_put_8s(f,&s->ier);
    qemu_put_8s(f,&s->iir);
    qemu_put_8s(f,&s->lcr);
    qemu_put_8s(f,&s->mcr);
    qemu_put_8s(f,&s->lsr);
    qemu_put_8s(f,&s->msr);
    qemu_put_8s(f,&s->scr);
}

static int serial_load(QEMUFile *f, void *opaque, int version_id)
{
    SerialState *s = opaque;

    if(version_id > 2)
        return -EINVAL;

    if (version_id >= 2)
        qemu_get_be16s(f, &s->divider);
    else
        s->divider = qemu_get_byte(f);
    qemu_get_8s(f,&s->rbr);
    qemu_get_8s(f,&s->ier);
    qemu_get_8s(f,&s->iir);
    qemu_get_8s(f,&s->lcr);
    qemu_get_8s(f,&s->mcr);
    qemu_get_8s(f,&s->lsr);
    qemu_get_8s(f,&s->msr);
    qemu_get_8s(f,&s->scr);

    return 0;
}

/* If fd is zero, it means that the serial device uses the console */
SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
                         int base, int irq, CharDriverState *chr)
{
    SerialState *s;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->set_irq = set_irq;
    s->irq_opaque = opaque;
    s->irq = irq;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->iir = UART_IIR_NO_INT;
    s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;

    register_savevm("serial", base, 2, serial_save, serial_load, s);

    register_ioport_write(base, 8, 1, serial_ioport_write, s);
    register_ioport_read(base, 8, 1, serial_ioport_read, s);
    s->chr = chr;
    qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
                          serial_event, s);
    return s;
}

/* Memory mapped interface */
static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;

    return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
}

static void serial_mm_writeb (void *opaque,
                              target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;

    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}

static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;

    return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
}

static void serial_mm_writew (void *opaque,
                              target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;

    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}

static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;

    return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
}

static void serial_mm_writel (void *opaque,
                              target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;

    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
}

static CPUReadMemoryFunc *serial_mm_read[] = {
    &serial_mm_readb,
    &serial_mm_readw,
    &serial_mm_readl,
};

static CPUWriteMemoryFunc *serial_mm_write[] = {
    &serial_mm_writeb,
    &serial_mm_writew,
    &serial_mm_writel,
};

SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
                             target_ulong base, int it_shift,
                             int irq, CharDriverState *chr)
{
    SerialState *s;
    int s_io_memory;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->set_irq = set_irq;
    s->irq_opaque = opaque;
    s->irq = irq;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->iir = UART_IIR_NO_INT;
    s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
    s->base = base;
    s->it_shift = it_shift;

    register_savevm("serial", base, 2, serial_save, serial_load, s);

    s_io_memory = cpu_register_io_memory(0, serial_mm_read,
                                         serial_mm_write, s);
    cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
    s->chr = chr;
    qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
                          serial_event, s);
    return s;
}
Commit	Line	Data
80cabfad FB	1	/*
	2	* QEMU 16450 UART emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80cabfad FB	24	#include "vl.h"
	25
	26	//#define DEBUG_SERIAL
	27
	28	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	29
	30	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
	31	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
	32	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
	33	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
	34
	35	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
	36	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
	37
	38	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
	39	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
	40	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
	41	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
	42
	43	/*
	44	* These are the definitions for the Modem Control Register
	45	*/
	46	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
	47	#define UART_MCR_OUT2 0x08 /* Out2 complement */
	48	#define UART_MCR_OUT1 0x04 /* Out1 complement */
	49	#define UART_MCR_RTS 0x02 /* RTS complement */
	50	#define UART_MCR_DTR 0x01 /* DTR complement */
	51
	52	/*
	53	* These are the definitions for the Modem Status Register
	54	*/
	55	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
	56	#define UART_MSR_RI 0x40 /* Ring Indicator */
	57	#define UART_MSR_DSR 0x20 /* Data Set Ready */
	58	#define UART_MSR_CTS 0x10 /* Clear to Send */
	59	#define UART_MSR_DDCD 0x08 /* Delta DCD */
	60	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
	61	#define UART_MSR_DDSR 0x02 /* Delta DSR */
	62	#define UART_MSR_DCTS 0x01 /* Delta CTS */
	63	#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
	64
	65	#define UART_LSR_TEMT 0x40 /* Transmitter empty */
	66	#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
	67	#define UART_LSR_BI 0x10 /* Break interrupt indicator */
	68	#define UART_LSR_FE 0x08 /* Frame error indicator */
	69	#define UART_LSR_PE 0x04 /* Parity error indicator */
	70	#define UART_LSR_OE 0x02 /* Overrun error indicator */
	71	#define UART_LSR_DR 0x01 /* Receiver data ready */
	72
b41a2cd1	73	struct SerialState {
508d92d0	74	uint16_t divider;
80cabfad FB	75	uint8_t rbr; /* receive register */
	76	uint8_t ier;
	77	uint8_t iir; /* read only */
	78	uint8_t lcr;
	79	uint8_t mcr;
	80	uint8_t lsr; /* read only */
3e749fe1	81	uint8_t msr; /* read only */
80cabfad FB	82	uint8_t scr;
	83	/* NOTE: this hidden state is necessary for tx irq generation as
	84	it can be reset while reading iir */
	85	int thr_ipending;
e5d13e2f FB	86	SetIRQFunc *set_irq;
e5d13e2f FB	87	void *irq_opaque;
80cabfad	88	int irq;
82c643ff	89	CharDriverState *chr;
f8d179e3	90	int last_break_enable;
e5d13e2f FB	91	target_ulong base;
e5d13e2f FB	92	int it_shift;
b41a2cd1	93	};
80cabfad	94
b41a2cd1	95	static void serial_update_irq(SerialState *s)
80cabfad	96	{
80cabfad FB	97	if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
	98	s->iir = UART_IIR_RDI;
	99	} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
	100	s->iir = UART_IIR_THRI;
	101	} else {
	102	s->iir = UART_IIR_NO_INT;
	103	}
	104	if (s->iir != UART_IIR_NO_INT) {
e5d13e2f	105	s->set_irq(s->irq_opaque, s->irq, 1);
80cabfad	106	} else {
e5d13e2f	107	s->set_irq(s->irq_opaque, s->irq, 0);
80cabfad FB	108	}
	109	}
	110
f8d179e3 FB	111	static void serial_update_parameters(SerialState *s)
	112	{
	113	int speed, parity, data_bits, stop_bits;
2122c51a	114	QEMUSerialSetParams ssp;
f8d179e3 FB	115
	116	if (s->lcr & 0x08) {
	117	if (s->lcr & 0x10)
	118	parity = 'E';
	119	else
	120	parity = 'O';
	121	} else {
	122	parity = 'N';
	123	}
	124	if (s->lcr & 0x04)
	125	stop_bits = 2;
	126	else
	127	stop_bits = 1;
	128	data_bits = (s->lcr & 0x03) + 5;
	129	if (s->divider == 0)
	130	return;
	131	speed = 115200 / s->divider;
2122c51a FB	132	ssp.speed = speed;
	133	ssp.parity = parity;
	134	ssp.data_bits = data_bits;
	135	ssp.stop_bits = stop_bits;
	136	qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
	137	#if 0
f8d179e3 FB	138	printf("speed=%d parity=%c data=%d stop=%d\n",
	139	speed, parity, data_bits, stop_bits);
	140	#endif
	141	}
	142
b41a2cd1	143	static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	144	{
b41a2cd1	145	SerialState *s = opaque;
80cabfad	146	unsigned char ch;
80cabfad FB	147
	148	addr &= 7;
	149	#ifdef DEBUG_SERIAL
	150	printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
	151	#endif
	152	switch(addr) {
	153	default:
	154	case 0:
	155	if (s->lcr & UART_LCR_DLAB) {
	156	s->divider = (s->divider & 0xff00) \| val;
f8d179e3	157	serial_update_parameters(s);
80cabfad FB	158	} else {
	159	s->thr_ipending = 0;
	160	s->lsr &= ~UART_LSR_THRE;
b41a2cd1	161	serial_update_irq(s);
82c643ff FB	162	ch = val;
82c643ff FB	163	qemu_chr_write(s->chr, &ch, 1);
80cabfad FB	164	s->thr_ipending = 1;
	165	s->lsr \|= UART_LSR_THRE;
	166	s->lsr \|= UART_LSR_TEMT;
b41a2cd1	167	serial_update_irq(s);
80cabfad FB	168	}
	169	break;
	170	case 1:
	171	if (s->lcr & UART_LCR_DLAB) {
	172	s->divider = (s->divider & 0x00ff) \| (val << 8);
f8d179e3	173	serial_update_parameters(s);
80cabfad	174	} else {
60e336db FB	175	s->ier = val & 0x0f;
	176	if (s->lsr & UART_LSR_THRE) {
	177	s->thr_ipending = 1;
	178	}
b41a2cd1	179	serial_update_irq(s);
80cabfad FB	180	}
	181	break;
	182	case 2:
	183	break;
	184	case 3:
f8d179e3 FB	185	{
	186	int break_enable;
	187	s->lcr = val;
	188	serial_update_parameters(s);
	189	break_enable = (val >> 6) & 1;
	190	if (break_enable != s->last_break_enable) {
	191	s->last_break_enable = break_enable;
2122c51a FB	192	qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
2122c51a FB	193	&break_enable);
f8d179e3 FB	194	}
f8d179e3 FB	195	}
80cabfad FB	196	break;
80cabfad FB	197	case 4:
60e336db	198	s->mcr = val & 0x1f;
80cabfad FB	199	break;
	200	case 5:
	201	break;
	202	case 6:
80cabfad FB	203	break;
	204	case 7:
	205	s->scr = val;
	206	break;
	207	}
	208	}
	209
b41a2cd1	210	static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
80cabfad	211	{
b41a2cd1	212	SerialState *s = opaque;
80cabfad FB	213	uint32_t ret;
	214
	215	addr &= 7;
	216	switch(addr) {
	217	default:
	218	case 0:
	219	if (s->lcr & UART_LCR_DLAB) {
	220	ret = s->divider & 0xff;
	221	} else {
	222	ret = s->rbr;
	223	s->lsr &= ~(UART_LSR_DR \| UART_LSR_BI);
b41a2cd1	224	serial_update_irq(s);
80cabfad FB	225	}
	226	break;
	227	case 1:
	228	if (s->lcr & UART_LCR_DLAB) {
	229	ret = (s->divider >> 8) & 0xff;
	230	} else {
	231	ret = s->ier;
	232	}
	233	break;
	234	case 2:
	235	ret = s->iir;
	236	/* reset THR pending bit */
	237	if ((ret & 0x7) == UART_IIR_THRI)
	238	s->thr_ipending = 0;
b41a2cd1	239	serial_update_irq(s);
80cabfad FB	240	break;
	241	case 3:
	242	ret = s->lcr;
	243	break;
	244	case 4:
	245	ret = s->mcr;
	246	break;
	247	case 5:
	248	ret = s->lsr;
	249	break;
	250	case 6:
	251	if (s->mcr & UART_MCR_LOOP) {
	252	/* in loopback, the modem output pins are connected to the
	253	inputs */
	254	ret = (s->mcr & 0x0c) << 4;
	255	ret \|= (s->mcr & 0x02) << 3;
	256	ret \|= (s->mcr & 0x01) << 5;
	257	} else {
	258	ret = s->msr;
	259	}
	260	break;
	261	case 7:
	262	ret = s->scr;
	263	break;
	264	}
	265	#ifdef DEBUG_SERIAL
	266	printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
	267	#endif
	268	return ret;
	269	}
	270
82c643ff	271	static int serial_can_receive(SerialState *s)
80cabfad	272	{
80cabfad FB	273	return !(s->lsr & UART_LSR_DR);
	274	}
	275
82c643ff	276	static void serial_receive_byte(SerialState *s, int ch)
80cabfad	277	{
80cabfad FB	278	s->rbr = ch;
80cabfad FB	279	s->lsr \|= UART_LSR_DR;
b41a2cd1	280	serial_update_irq(s);
80cabfad FB	281	}
80cabfad FB	282
82c643ff	283	static void serial_receive_break(SerialState *s)
80cabfad	284	{
80cabfad FB	285	s->rbr = 0;
80cabfad FB	286	s->lsr \|= UART_LSR_BI \| UART_LSR_DR;
b41a2cd1	287	serial_update_irq(s);
80cabfad FB	288	}
80cabfad FB	289
b41a2cd1	290	static int serial_can_receive1(void *opaque)
80cabfad	291	{
b41a2cd1 FB	292	SerialState *s = opaque;
	293	return serial_can_receive(s);
	294	}
	295
	296	static void serial_receive1(void opaque, const uint8_t buf, int size)
	297	{
	298	SerialState *s = opaque;
	299	serial_receive_byte(s, buf[0]);
	300	}
80cabfad	301
82c643ff FB	302	static void serial_event(void *opaque, int event)
	303	{
	304	SerialState *s = opaque;
	305	if (event == CHR_EVENT_BREAK)
	306	serial_receive_break(s);
	307	}
	308
8738a8d0 FB	309	static void serial_save(QEMUFile f, void opaque)
	310	{
	311	SerialState *s = opaque;
	312
508d92d0	313	qemu_put_be16s(f,&s->divider);
8738a8d0 FB	314	qemu_put_8s(f,&s->rbr);
	315	qemu_put_8s(f,&s->ier);
	316	qemu_put_8s(f,&s->iir);
	317	qemu_put_8s(f,&s->lcr);
	318	qemu_put_8s(f,&s->mcr);
	319	qemu_put_8s(f,&s->lsr);
	320	qemu_put_8s(f,&s->msr);
	321	qemu_put_8s(f,&s->scr);
	322	}
	323
	324	static int serial_load(QEMUFile f, void opaque, int version_id)
	325	{
	326	SerialState *s = opaque;
	327
508d92d0	328	if(version_id > 2)
8738a8d0 FB	329	return -EINVAL;
8738a8d0 FB	330
508d92d0 FB	331	if (version_id >= 2)
	332	qemu_get_be16s(f, &s->divider);
	333	else
	334	s->divider = qemu_get_byte(f);
8738a8d0 FB	335	qemu_get_8s(f,&s->rbr);
	336	qemu_get_8s(f,&s->ier);
	337	qemu_get_8s(f,&s->iir);
	338	qemu_get_8s(f,&s->lcr);
	339	qemu_get_8s(f,&s->mcr);
	340	qemu_get_8s(f,&s->lsr);
	341	qemu_get_8s(f,&s->msr);
	342	qemu_get_8s(f,&s->scr);
	343
	344	return 0;
	345	}
	346
b41a2cd1	347	/* If fd is zero, it means that the serial device uses the console */
e5d13e2f FB	348	SerialState serial_init(SetIRQFunc set_irq, void *opaque,
e5d13e2f FB	349	int base, int irq, CharDriverState *chr)
b41a2cd1 FB	350	{
	351	SerialState *s;
	352
	353	s = qemu_mallocz(sizeof(SerialState));
	354	if (!s)
	355	return NULL;
e5d13e2f FB	356	s->set_irq = set_irq;
e5d13e2f FB	357	s->irq_opaque = opaque;
80cabfad FB	358	s->irq = irq;
	359	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
	360	s->iir = UART_IIR_NO_INT;
3e749fe1	361	s->msr = UART_MSR_DCD \| UART_MSR_DSR \| UART_MSR_CTS;
b41a2cd1	362
508d92d0	363	register_savevm("serial", base, 2, serial_save, serial_load, s);
8738a8d0	364
b41a2cd1 FB	365	register_ioport_write(base, 8, 1, serial_ioport_write, s);
b41a2cd1 FB	366	register_ioport_read(base, 8, 1, serial_ioport_read, s);
82c643ff	367	s->chr = chr;
e5b0bc44 PB	368	qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
e5b0bc44 PB	369	serial_event, s);
b41a2cd1	370	return s;
80cabfad	371	}
e5d13e2f FB	372
	373	/* Memory mapped interface */
	374	static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
	375	{
	376	SerialState *s = opaque;
	377
	378	return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
	379	}
	380
	381	static void serial_mm_writeb (void *opaque,
	382	target_phys_addr_t addr, uint32_t value)
	383	{
	384	SerialState *s = opaque;
	385
	386	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
	387	}
	388
	389	static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
	390	{
	391	SerialState *s = opaque;
	392
	393	return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
	394	}
	395
	396	static void serial_mm_writew (void *opaque,
	397	target_phys_addr_t addr, uint32_t value)
	398	{
	399	SerialState *s = opaque;
	400
	401	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
	402	}
	403
	404	static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
	405	{
	406	SerialState *s = opaque;
	407
	408	return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
	409	}
	410
	411	static void serial_mm_writel (void *opaque,
	412	target_phys_addr_t addr, uint32_t value)
	413	{
	414	SerialState *s = opaque;
	415
	416	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
	417	}
	418
	419	static CPUReadMemoryFunc *serial_mm_read[] = {
	420	&serial_mm_readb,
	421	&serial_mm_readw,
	422	&serial_mm_readl,
	423	};
	424
	425	static CPUWriteMemoryFunc *serial_mm_write[] = {
	426	&serial_mm_writeb,
	427	&serial_mm_writew,
	428	&serial_mm_writel,
	429	};
	430
	431	SerialState serial_mm_init (SetIRQFunc set_irq, void *opaque,
	432	target_ulong base, int it_shift,
	433	int irq, CharDriverState *chr)
	434	{
	435	SerialState *s;
436	int s_io_memory;
437
438	s = qemu_mallocz(sizeof(SerialState));
439	if (!s)
440	return NULL;
441	s->set_irq = set_irq;
442	s->irq_opaque = opaque;
443	s->irq = irq;
444	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
445	s->iir = UART_IIR_NO_INT;
3e749fe1	446	s->msr = UART_MSR_DCD \| UART_MSR_DSR \| UART_MSR_CTS;
e5d13e2f FB	447	s->base = base;
	448	s->it_shift = it_shift;
	449
508d92d0	450	register_savevm("serial", base, 2, serial_save, serial_load, s);
e5d13e2f FB	451
	452	s_io_memory = cpu_register_io_memory(0, serial_mm_read,
	453	serial_mm_write, s);
	454	cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
	455	s->chr = chr;
e5b0bc44 PB	456	qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
e5b0bc44 PB	457	serial_event, s);
e5d13e2f FB	458	return s;
e5d13e2f FB	459	}