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1e5459a3 AZ |
1 | /* |
2 | * SuperH on-chip PCIC emulation. | |
3 | * | |
4 | * Copyright (c) 2008 Takashi YOSHII | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/sysbus.h" |
0d09e41a | 25 | #include "hw/sh4/sh.h" |
83c9f4ca PB |
26 | #include "hw/pci/pci.h" |
27 | #include "hw/pci/pci_host.h" | |
1de7afc9 | 28 | #include "qemu/bswap.h" |
022c62cb | 29 | #include "exec/address-spaces.h" |
1e5459a3 | 30 | |
b23ea25f PB |
31 | #define TYPE_SH_PCI_HOST_BRIDGE "sh_pci" |
32 | ||
33 | #define SH_PCI_HOST_BRIDGE(obj) \ | |
34 | OBJECT_CHECK(SHPCIState, (obj), TYPE_SH_PCI_HOST_BRIDGE) | |
35 | ||
cf154394 | 36 | typedef struct SHPCIState { |
b23ea25f PB |
37 | PCIHostState parent_obj; |
38 | ||
1e5459a3 | 39 | PCIDevice *dev; |
cf154394 | 40 | qemu_irq irq[4]; |
fb57117a AK |
41 | MemoryRegion memconfig_p4; |
42 | MemoryRegion memconfig_a7; | |
43 | MemoryRegion isa; | |
1e5459a3 AZ |
44 | uint32_t par; |
45 | uint32_t mbr; | |
46 | uint32_t iobr; | |
cf154394 | 47 | } SHPCIState; |
1e5459a3 | 48 | |
a8170e5e | 49 | static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val, |
fb57117a | 50 | unsigned size) |
1e5459a3 | 51 | { |
cf154394 | 52 | SHPCIState *pcic = p; |
b23ea25f PB |
53 | PCIHostState *phb = PCI_HOST_BRIDGE(pcic); |
54 | ||
1e5459a3 AZ |
55 | switch(addr) { |
56 | case 0 ... 0xfc: | |
57 | cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); | |
58 | break; | |
59 | case 0x1c0: | |
60 | pcic->par = val; | |
61 | break; | |
62 | case 0x1c4: | |
5ba9e952 | 63 | pcic->mbr = val & 0xff000001; |
1e5459a3 AZ |
64 | break; |
65 | case 0x1c8: | |
5ba9e952 | 66 | if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { |
fb57117a | 67 | memory_region_del_subregion(get_system_memory(), &pcic->isa); |
5ba9e952 | 68 | pcic->iobr = val & 0xfffc0001; |
fb57117a AK |
69 | memory_region_add_subregion(get_system_memory(), |
70 | pcic->iobr & 0xfffc0000, &pcic->isa); | |
5ba9e952 | 71 | } |
1e5459a3 AZ |
72 | break; |
73 | case 0x220: | |
b23ea25f | 74 | pci_data_write(phb->bus, pcic->par, val, 4); |
1e5459a3 AZ |
75 | break; |
76 | } | |
77 | } | |
78 | ||
a8170e5e | 79 | static uint64_t sh_pci_reg_read (void *p, hwaddr addr, |
fb57117a | 80 | unsigned size) |
1e5459a3 | 81 | { |
cf154394 | 82 | SHPCIState *pcic = p; |
b23ea25f PB |
83 | PCIHostState *phb = PCI_HOST_BRIDGE(pcic); |
84 | ||
1e5459a3 AZ |
85 | switch(addr) { |
86 | case 0 ... 0xfc: | |
87 | return le32_to_cpup((uint32_t*)(pcic->dev->config + addr)); | |
88 | case 0x1c0: | |
89 | return pcic->par; | |
5ba9e952 AJ |
90 | case 0x1c4: |
91 | return pcic->mbr; | |
92 | case 0x1c8: | |
93 | return pcic->iobr; | |
1e5459a3 | 94 | case 0x220: |
b23ea25f | 95 | return pci_data_read(phb->bus, pcic->par, 4); |
1e5459a3 AZ |
96 | } |
97 | return 0; | |
98 | } | |
99 | ||
fb57117a AK |
100 | static const MemoryRegionOps sh_pci_reg_ops = { |
101 | .read = sh_pci_reg_read, | |
102 | .write = sh_pci_reg_write, | |
103 | .endianness = DEVICE_NATIVE_ENDIAN, | |
104 | .valid = { | |
105 | .min_access_size = 4, | |
106 | .max_access_size = 4, | |
107 | }, | |
1e5459a3 AZ |
108 | }; |
109 | ||
cf154394 AJ |
110 | static int sh_pci_map_irq(PCIDevice *d, int irq_num) |
111 | { | |
112 | return (d->devfn >> 3); | |
113 | } | |
114 | ||
115 | static void sh_pci_set_irq(void *opaque, int irq_num, int level) | |
116 | { | |
117 | qemu_irq *pic = opaque; | |
118 | ||
119 | qemu_set_irq(pic[irq_num], level); | |
120 | } | |
121 | ||
999e12bb | 122 | static int sh_pci_device_init(SysBusDevice *dev) |
cf154394 | 123 | { |
b23ea25f | 124 | PCIHostState *phb; |
cf154394 AJ |
125 | SHPCIState *s; |
126 | int i; | |
127 | ||
b23ea25f PB |
128 | s = SH_PCI_HOST_BRIDGE(dev); |
129 | phb = PCI_HOST_BRIDGE(s); | |
cf154394 AJ |
130 | for (i = 0; i < 4; i++) { |
131 | sysbus_init_irq(dev, &s->irq[i]); | |
132 | } | |
b23ea25f PB |
133 | phb->bus = pci_register_bus(DEVICE(dev), "pci", |
134 | sh_pci_set_irq, sh_pci_map_irq, | |
135 | s->irq, | |
136 | get_system_memory(), | |
137 | get_system_io(), | |
138 | PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS); | |
29776739 | 139 | memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s, |
fb57117a | 140 | "sh_pci", 0x224); |
29776739 PB |
141 | memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2", |
142 | &s->memconfig_p4, 0, 0x224); | |
4759ab6b PB |
143 | memory_region_init_alias(&s->isa, OBJECT(s), "sh_pci.isa", |
144 | get_system_io(), 0, 0x40000); | |
8c106233 | 145 | sysbus_init_mmio(dev, &s->memconfig_p4); |
750ecd44 | 146 | sysbus_init_mmio(dev, &s->memconfig_a7); |
8c106233 BC |
147 | s->iobr = 0xfe240000; |
148 | memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa); | |
149 | ||
b23ea25f | 150 | s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host"); |
cf154394 AJ |
151 | return 0; |
152 | } | |
153 | ||
154 | static int sh_pci_host_init(PCIDevice *d) | |
155 | { | |
cf154394 AJ |
156 | pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT); |
157 | pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST | | |
158 | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); | |
159 | return 0; | |
160 | } | |
161 | ||
40021f08 AL |
162 | static void sh_pci_host_class_init(ObjectClass *klass, void *data) |
163 | { | |
164 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
165 | ||
166 | k->init = sh_pci_host_init; | |
167 | k->vendor_id = PCI_VENDOR_ID_HITACHI; | |
168 | k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R; | |
169 | } | |
170 | ||
8c43a6f0 | 171 | static const TypeInfo sh_pci_host_info = { |
39bffca2 AL |
172 | .name = "sh_pci_host", |
173 | .parent = TYPE_PCI_DEVICE, | |
174 | .instance_size = sizeof(PCIDevice), | |
175 | .class_init = sh_pci_host_class_init, | |
cf154394 AJ |
176 | }; |
177 | ||
999e12bb AL |
178 | static void sh_pci_device_class_init(ObjectClass *klass, void *data) |
179 | { | |
180 | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); | |
181 | ||
182 | sdc->init = sh_pci_device_init; | |
183 | } | |
184 | ||
8c43a6f0 | 185 | static const TypeInfo sh_pci_device_info = { |
b23ea25f PB |
186 | .name = TYPE_SH_PCI_HOST_BRIDGE, |
187 | .parent = TYPE_PCI_HOST_BRIDGE, | |
39bffca2 AL |
188 | .instance_size = sizeof(SHPCIState), |
189 | .class_init = sh_pci_device_class_init, | |
999e12bb AL |
190 | }; |
191 | ||
83f7d43a | 192 | static void sh_pci_register_types(void) |
1e5459a3 | 193 | { |
39bffca2 AL |
194 | type_register_static(&sh_pci_device_info); |
195 | type_register_static(&sh_pci_host_info); | |
1e5459a3 | 196 | } |
cf154394 | 197 | |
83f7d43a | 198 | type_init(sh_pci_register_types) |