[qemu.git] / hw / sh7750.c

/*
 * SH7750 device
 *
 * Copyright (c) 2007 Magnus Damm
 * Copyright (c) 2005 Samuel Tardieu
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <stdio.h>
#include <assert.h>
#include "hw.h"
#include "sh.h"
#include "sysemu.h"
#include "sh7750_regs.h"
#include "sh7750_regnames.h"
#include "sh_intc.h"

#define NB_DEVICES 4

typedef struct SH7750State {
    /* CPU */
    CPUSH4State *cpu;
    /* Peripheral frequency in Hz */
    uint32_t periph_freq;
    /* SDRAM controller */
    uint16_t rfcr;
    /* IO ports */
    uint16_t gpioic;
    uint32_t pctra;
    uint32_t pctrb;
    uint16_t portdira;		/* Cached */
    uint16_t portpullupa;	/* Cached */
    uint16_t portdirb;		/* Cached */
    uint16_t portpullupb;	/* Cached */
    uint16_t pdtra;
    uint16_t pdtrb;
    uint16_t periph_pdtra;	/* Imposed by the peripherals */
    uint16_t periph_portdira;	/* Direction seen from the peripherals */
    uint16_t periph_pdtrb;	/* Imposed by the peripherals */
    uint16_t periph_portdirb;	/* Direction seen from the peripherals */
    sh7750_io_device *devices[NB_DEVICES];	/* External peripherals */

    uint16_t icr;
    /* Cache */
    uint32_t ccr;

    struct intc_desc intc;
} SH7750State;


/**********************************************************************
 I/O ports
**********************************************************************/

int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
{
    int i;

    for (i = 0; i < NB_DEVICES; i++) {
	if (s->devices[i] == NULL) {
	    s->devices[i] = device;
	    return 0;
	}
    }
    return -1;
}

static uint16_t portdir(uint32_t v)
{
#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
    return
	EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
	EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
	EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
	EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
	EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
	EVENPORTMASK(0);
}

static uint16_t portpullup(uint32_t v)
{
#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
    return
	ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
	ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
	ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
	ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
	ODDPORTMASK(1) | ODDPORTMASK(0);
}

static uint16_t porta_lines(SH7750State * s)
{
    return (s->portdira & s->pdtra) |	/* CPU */
	(s->periph_portdira & s->periph_pdtra) |	/* Peripherals */
	(~(s->portdira | s->periph_portdira) & s->portpullupa);	/* Pullups */
}

static uint16_t portb_lines(SH7750State * s)
{
    return (s->portdirb & s->pdtrb) |	/* CPU */
	(s->periph_portdirb & s->periph_pdtrb) |	/* Peripherals */
	(~(s->portdirb | s->periph_portdirb) & s->portpullupb);	/* Pullups */
}

static void gen_port_interrupts(SH7750State * s)
{
    /* XXXXX interrupts not generated */
}

static void porta_changed(SH7750State * s, uint16_t prev)
{
    uint16_t currenta, changes;
    int i, r = 0;

#if 0
    fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
	    prev, porta_lines(s));
    fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
#endif
    currenta = porta_lines(s);
    if (currenta == prev)
	return;
    changes = currenta ^ prev;

    for (i = 0; i < NB_DEVICES; i++) {
	if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
	    r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
					       &s->periph_pdtra,
					       &s->periph_portdira,
					       &s->periph_pdtrb,
					       &s->periph_portdirb);
	}
    }

    if (r)
	gen_port_interrupts(s);
}

static void portb_changed(SH7750State * s, uint16_t prev)
{
    uint16_t currentb, changes;
    int i, r = 0;

    currentb = portb_lines(s);
    if (currentb == prev)
	return;
    changes = currentb ^ prev;

    for (i = 0; i < NB_DEVICES; i++) {
	if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
	    r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
					       &s->periph_pdtra,
					       &s->periph_portdira,
					       &s->periph_pdtrb,
					       &s->periph_portdirb);
	}
    }

    if (r)
	gen_port_interrupts(s);
}

/**********************************************************************
 Memory
**********************************************************************/

static void error_access(const char *kind, target_phys_addr_t addr)
{
    fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
	    kind, regname(addr), addr);
}

static void ignore_access(const char *kind, target_phys_addr_t addr)
{
    fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
	    kind, regname(addr), addr);
}

static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
{
    switch (addr) {
    default:
	error_access("byte read", addr);
	assert(0);
    }
}

static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
{
    SH7750State *s = opaque;

    switch (addr) {
    case SH7750_FRQCR_A7:
	return 0;
    case SH7750_RFCR_A7:
	fprintf(stderr,
		"Read access to refresh count register, incrementing\n");
	return s->rfcr++;
    case SH7750_PDTRA_A7:
	return porta_lines(s);
    case SH7750_PDTRB_A7:
	return portb_lines(s);
    case 0x1fd00000:
        return s->icr;
    default:
	error_access("word read", addr);
	assert(0);
    }
}

static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SH7750State *s = opaque;

    switch (addr) {
    case SH7750_MMUCR_A7:
	return s->cpu->mmucr;
    case SH7750_PTEH_A7:
	return s->cpu->pteh;
    case SH7750_PTEL_A7:
	return s->cpu->ptel;
    case SH7750_TTB_A7:
	return s->cpu->ttb;
    case SH7750_TEA_A7:
	return s->cpu->tea;
    case SH7750_TRA_A7:
	return s->cpu->tra;
    case SH7750_EXPEVT_A7:
	return s->cpu->expevt;
    case SH7750_INTEVT_A7:
	return s->cpu->intevt;
    case SH7750_CCR_A7:
	return s->ccr;
    case 0x1f000030:		/* Processor version PVR */
	return 0x00050000;	/* SH7750R */
    case 0x1f000040:		/* Processor version CVR */
	return 0x00110000;	/* Minimum caches */
    case 0x1f000044:		/* Processor version PRR */
	return 0x00000100;	/* SH7750R */
    default:
	error_access("long read", addr);
	assert(0);
    }
}

static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{
    switch (addr) {
	/* PRECHARGE ? XXXXX */
    case SH7750_PRECHARGE0_A7:
    case SH7750_PRECHARGE1_A7:
	ignore_access("byte write", addr);
	return;
    default:
	error_access("byte write", addr);
	assert(0);
    }
}

static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{
    SH7750State *s = opaque;
    uint16_t temp;

    switch (addr) {
	/* SDRAM controller */
    case SH7750_BCR2_A7:
    case SH7750_BCR3_A7:
    case SH7750_RTCOR_A7:
    case SH7750_RTCNT_A7:
    case SH7750_RTCSR_A7:
	ignore_access("word write", addr);
	return;
	/* IO ports */
    case SH7750_PDTRA_A7:
	temp = porta_lines(s);
	s->pdtra = mem_value;
	porta_changed(s, temp);
	return;
    case SH7750_PDTRB_A7:
	temp = portb_lines(s);
	s->pdtrb = mem_value;
	portb_changed(s, temp);
	return;
    case SH7750_RFCR_A7:
	fprintf(stderr, "Write access to refresh count register\n");
	s->rfcr = mem_value;
	return;
    case SH7750_GPIOIC_A7:
	s->gpioic = mem_value;
	if (mem_value != 0) {
	    fprintf(stderr, "I/O interrupts not implemented\n");
	    assert(0);
	}
	return;
    case 0x1fd00000:
        s->icr = mem_value;
	return;
    default:
	error_access("word write", addr);
	assert(0);
    }
}

static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{
    SH7750State *s = opaque;
    uint16_t temp;

    switch (addr) {
	/* SDRAM controller */
    case SH7750_BCR1_A7:
    case SH7750_BCR4_A7:
    case SH7750_WCR1_A7:
    case SH7750_WCR2_A7:
    case SH7750_WCR3_A7:
    case SH7750_MCR_A7:
	ignore_access("long write", addr);
	return;
	/* IO ports */
    case SH7750_PCTRA_A7:
	temp = porta_lines(s);
	s->pctra = mem_value;
	s->portdira = portdir(mem_value);
	s->portpullupa = portpullup(mem_value);
	porta_changed(s, temp);
	return;
    case SH7750_PCTRB_A7:
	temp = portb_lines(s);
	s->pctrb = mem_value;
	s->portdirb = portdir(mem_value);
	s->portpullupb = portpullup(mem_value);
	portb_changed(s, temp);
	return;
    case SH7750_MMUCR_A7:
	s->cpu->mmucr = mem_value;
	return;
    case SH7750_PTEH_A7:
	s->cpu->pteh = mem_value;
	return;
    case SH7750_PTEL_A7:
	s->cpu->ptel = mem_value;
	return;
    case SH7750_PTEA_A7:
	s->cpu->ptea = mem_value & 0x0000000f;
	return;
    case SH7750_TTB_A7:
	s->cpu->ttb = mem_value;
	return;
    case SH7750_TEA_A7:
	s->cpu->tea = mem_value;
	return;
    case SH7750_TRA_A7:
	s->cpu->tra = mem_value & 0x000007ff;
	return;
    case SH7750_EXPEVT_A7:
	s->cpu->expevt = mem_value & 0x000007ff;
	return;
    case SH7750_INTEVT_A7:
	s->cpu->intevt = mem_value & 0x000007ff;
	return;
    case SH7750_CCR_A7:
	s->ccr = mem_value;
	return;
    default:
	error_access("long write", addr);
	assert(0);
    }
}

static CPUReadMemoryFunc *sh7750_mem_read[] = {
    sh7750_mem_readb,
    sh7750_mem_readw,
    sh7750_mem_readl
};

static CPUWriteMemoryFunc *sh7750_mem_write[] = {
    sh7750_mem_writeb,
    sh7750_mem_writew,
    sh7750_mem_writel
};

/* sh775x interrupt controller tables for sh_intc.c
 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
 */

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
	HUDI, GPIOI,
	DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
	DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
	DMAC_DMAE,
	PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
	TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
	RTC_ATI, RTC_PRI, RTC_CUI,
	SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
	SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
	WDT,
	REF_RCMI, REF_ROVI,

	/* interrupt groups */
	DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,

	NR_SOURCES,
};

static struct intc_vect vectors[] = {
	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
	INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
	INTC_VECT(RTC_CUI, 0x4c0),
	INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
	INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
	INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
	INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
	INTC_VECT(WDT, 0x560),
	INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
};

static struct intc_group groups[] = {
	INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
	INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
	INTC_GROUP(REF, REF_RCMI, REF_ROVI),
};

static struct intc_prio_reg prio_registers[] = {
	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
						 TMU4, TMU3,
						 PCIC1, PCIC0_PCISERR } },
};

/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */

static struct intc_vect vectors_dma4[] = {
	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
	INTC_VECT(DMAC_DMAE, 0x6c0),
};

static struct intc_group groups_dma4[] = {
	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
		   DMAC_DMTE3, DMAC_DMAE),
};

/* SH7750R and SH7751R both have 8-channel DMA controllers */

static struct intc_vect vectors_dma8[] = {
	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
	INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
	INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
	INTC_VECT(DMAC_DMAE, 0x6c0),
};

static struct intc_group groups_dma8[] = {
	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
		   DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
		   DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
};

/* SH7750R, SH7751 and SH7751R all have two extra timer channels */

static struct intc_vect vectors_tmu34[] = {
	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
};

static struct intc_mask_reg mask_registers[] = {
	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	    0, 0, 0, 0, 0, 0, TMU4, TMU3,
	    PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
	    PCIC1_PCIDMA3, PCIC0_PCISERR } },
};

/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */

static struct intc_vect vectors_irlm[] = {
	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
};

/* SH7751 and SH7751R both have PCI */

static struct intc_vect vectors_pci[] = {
	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
};

static struct intc_group groups_pci[] = {
	INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
		   PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
};

#define SH_CPU_SH7750  (1 << 0)
#define SH_CPU_SH7750S (1 << 1)
#define SH_CPU_SH7750R (1 << 2)
#define SH_CPU_SH7751  (1 << 3)
#define SH_CPU_SH7751R (1 << 4)
#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)

SH7750State *sh7750_init(CPUSH4State * cpu)
{
    SH7750State *s;
    int sh7750_io_memory;
    int cpu_model = SH_CPU_SH7751R; /* for now */

    s = qemu_mallocz(sizeof(SH7750State));
    s->cpu = cpu;
    s->periph_freq = 60000000;	/* 60MHz */
    sh7750_io_memory = cpu_register_io_memory(0,
					      sh7750_mem_read,
					      sh7750_mem_write, s);
    cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);

    sh_intc_init(&s->intc, NR_SOURCES,
		 _INTC_ARRAY(mask_registers),
		 _INTC_ARRAY(prio_registers));

    sh_intc_register_sources(&s->intc, 
			     _INTC_ARRAY(vectors),
			     _INTC_ARRAY(groups));

    cpu->intc_handle = &s->intc;

    sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
		   sh_intc_source(&s->intc, SCI1_ERI),
		   sh_intc_source(&s->intc, SCI1_RXI),
		   sh_intc_source(&s->intc, SCI1_TXI),
		   sh_intc_source(&s->intc, SCI1_TEI),
		   NULL);
    sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
		   s->periph_freq, serial_hds[1],
		   sh_intc_source(&s->intc, SCIF_ERI),
		   sh_intc_source(&s->intc, SCIF_RXI),
		   sh_intc_source(&s->intc, SCIF_TXI),
		   NULL,
		   sh_intc_source(&s->intc, SCIF_BRI));

    tmu012_init(0x1fd80000,
		TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
		s->periph_freq,
		sh_intc_source(&s->intc, TMU0),
		sh_intc_source(&s->intc, TMU1),
		sh_intc_source(&s->intc, TMU2_TUNI),
		sh_intc_source(&s->intc, TMU2_TICPI));

    if (cpu_model & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_dma4),
				 _INTC_ARRAY(groups_dma4));
    }

    if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_dma8),
				 _INTC_ARRAY(groups_dma8));
    }

    if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_tmu34),
				 NULL, 0);
        tmu012_init(0x1e100000, 0, s->periph_freq,
		    sh_intc_source(&s->intc, TMU3),
		    sh_intc_source(&s->intc, TMU4),
		    NULL, NULL);
    }

    if (cpu_model & (SH_CPU_SH7751_ALL)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_pci),
				 _INTC_ARRAY(groups_pci));
    }

    if (cpu_model & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_irlm),
				 NULL, 0);
    }

    return s;
}
Commit	Line	Data
27c7ca7e FB	1	/*
27c7ca7e FB	2	* SH7750 device
5fafdf24	3	*
80f515e6	4	* Copyright (c) 2007 Magnus Damm
27c7ca7e	5	* Copyright (c) 2005 Samuel Tardieu
5fafdf24	6	*
27c7ca7e FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include <stdio.h>
	26	#include <assert.h>
87ecb68b PB	27	#include "hw.h"
	28	#include "sh.h"
	29	#include "sysemu.h"
27c7ca7e FB	30	#include "sh7750_regs.h"
27c7ca7e FB	31	#include "sh7750_regnames.h"
80f515e6	32	#include "sh_intc.h"
27c7ca7e	33
27c7ca7e FB	34	#define NB_DEVICES 4
	35
	36	typedef struct SH7750State {
	37	/* CPU */
	38	CPUSH4State *cpu;
	39	/* Peripheral frequency in Hz */
	40	uint32_t periph_freq;
	41	/* SDRAM controller */
	42	uint16_t rfcr;
27c7ca7e FB	43	/* IO ports */
	44	uint16_t gpioic;
	45	uint32_t pctra;
	46	uint32_t pctrb;
	47	uint16_t portdira; /* Cached */
	48	uint16_t portpullupa; /* Cached */
	49	uint16_t portdirb; /* Cached */
	50	uint16_t portpullupb; /* Cached */
	51	uint16_t pdtra;
	52	uint16_t pdtrb;
	53	uint16_t periph_pdtra; /* Imposed by the peripherals */
	54	uint16_t periph_portdira; /* Direction seen from the peripherals */
	55	uint16_t periph_pdtrb; /* Imposed by the peripherals */
	56	uint16_t periph_portdirb; /* Direction seen from the peripherals */
	57	sh7750_io_device devices[NB_DEVICES]; / External peripherals */
3464c589 TS	58
3464c589 TS	59	uint16_t icr;
27c7ca7e FB	60	/* Cache */
27c7ca7e FB	61	uint32_t ccr;
27c7ca7e	62
80f515e6	63	struct intc_desc intc;
cd1a3f68	64	} SH7750State;
27c7ca7e	65
27c7ca7e FB	66
	67	/**********************************************************************
	68	I/O ports
	69	**********************************************************************/
	70
	71	int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
	72	{
	73	int i;
	74
	75	for (i = 0; i < NB_DEVICES; i++) {
	76	if (s->devices[i] == NULL) {
	77	s->devices[i] = device;
	78	return 0;
	79	}
	80	}
	81	return -1;
	82	}
	83
	84	static uint16_t portdir(uint32_t v)
	85	{
	86	#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
	87	return
	88	EVENPORTMASK(15) \| EVENPORTMASK(14) \| EVENPORTMASK(13) \|
	89	EVENPORTMASK(12) \| EVENPORTMASK(11) \| EVENPORTMASK(10) \|
	90	EVENPORTMASK(9) \| EVENPORTMASK(8) \| EVENPORTMASK(7) \|
	91	EVENPORTMASK(6) \| EVENPORTMASK(5) \| EVENPORTMASK(4) \|
	92	EVENPORTMASK(3) \| EVENPORTMASK(2) \| EVENPORTMASK(1) \|
	93	EVENPORTMASK(0);
	94	}
	95
	96	static uint16_t portpullup(uint32_t v)
	97	{
	98	#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
	99	return
	100	ODDPORTMASK(15) \| ODDPORTMASK(14) \| ODDPORTMASK(13) \|
	101	ODDPORTMASK(12) \| ODDPORTMASK(11) \| ODDPORTMASK(10) \|
	102	ODDPORTMASK(9) \| ODDPORTMASK(8) \| ODDPORTMASK(7) \| ODDPORTMASK(6) \|
	103	ODDPORTMASK(5) \| ODDPORTMASK(4) \| ODDPORTMASK(3) \| ODDPORTMASK(2) \|
	104	ODDPORTMASK(1) \| ODDPORTMASK(0);
	105	}
	106
	107	static uint16_t porta_lines(SH7750State * s)
	108	{
	109	return (s->portdira & s->pdtra) \| /* CPU */
	110	(s->periph_portdira & s->periph_pdtra) \| /* Peripherals */
	111	(~(s->portdira \| s->periph_portdira) & s->portpullupa); /* Pullups */
	112	}
	113
	114	static uint16_t portb_lines(SH7750State * s)
	115	{
	116	return (s->portdirb & s->pdtrb) \| /* CPU */
	117	(s->periph_portdirb & s->periph_pdtrb) \| /* Peripherals */
	118	(~(s->portdirb \| s->periph_portdirb) & s->portpullupb); /* Pullups */
	119	}
	120
	121	static void gen_port_interrupts(SH7750State * s)
	122	{
	123	/* XXXXX interrupts not generated */
	124	}
	125
	126	static void porta_changed(SH7750State * s, uint16_t prev)
	127	{
	128	uint16_t currenta, changes;
	129	int i, r = 0;
130
131	#if 0
132	fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
133	prev, porta_lines(s));
134	fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
135	#endif
136	currenta = porta_lines(s);
137	if (currenta == prev)
138	return;
139	changes = currenta ^ prev;
140
141	for (i = 0; i < NB_DEVICES; i++) {
142	if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
143	r \|= s->devices[i]->port_change_cb(currenta, portb_lines(s),
144	&s->periph_pdtra,
145	&s->periph_portdira,
146	&s->periph_pdtrb,
147	&s->periph_portdirb);
148	}
149	}
150
151	if (r)
152	gen_port_interrupts(s);
153	}
154
155	static void portb_changed(SH7750State * s, uint16_t prev)
156	{
157	uint16_t currentb, changes;
158	int i, r = 0;
159
160	currentb = portb_lines(s);
161	if (currentb == prev)
162	return;
163	changes = currentb ^ prev;
164
165	for (i = 0; i < NB_DEVICES; i++) {
166	if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
167	r \|= s->devices[i]->port_change_cb(portb_lines(s), currentb,
168	&s->periph_pdtra,
169	&s->periph_portdira,
170	&s->periph_pdtrb,
171	&s->periph_portdirb);
172	}
173	}
174
175	if (r)
176	gen_port_interrupts(s);
177	}
178
179	/**********************************************************************
180	Memory
181	**********************************************************************/
182
183	static void error_access(const char *kind, target_phys_addr_t addr)
184	{
526ccb7a	185	fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
27c7ca7e FB	186	kind, regname(addr), addr);
	187	}
	188
	189	static void ignore_access(const char *kind, target_phys_addr_t addr)
	190	{
526ccb7a	191	fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
27c7ca7e FB	192	kind, regname(addr), addr);
	193	}
	194
	195	static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
	196	{
27c7ca7e	197	switch (addr) {
27c7ca7e FB	198	default:
	199	error_access("byte read", addr);
	200	assert(0);
	201	}
	202	}
	203
	204	static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
	205	{
	206	SH7750State *s = opaque;
27c7ca7e FB	207
27c7ca7e FB	208	switch (addr) {
ed8e0a4d TS	209	case SH7750_FRQCR_A7:
ed8e0a4d TS	210	return 0;
27c7ca7e FB	211	case SH7750_RFCR_A7:
	212	fprintf(stderr,
	213	"Read access to refresh count register, incrementing\n");
	214	return s->rfcr++;
27c7ca7e FB	215	case SH7750_PDTRA_A7:
	216	return porta_lines(s);
	217	case SH7750_PDTRB_A7:
	218	return portb_lines(s);
3464c589 TS	219	case 0x1fd00000:
3464c589 TS	220	return s->icr;
27c7ca7e FB	221	default:
	222	error_access("word read", addr);
	223	assert(0);
	224	}
	225	}
	226
	227	static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
	228	{
	229	SH7750State *s = opaque;
	230
	231	switch (addr) {
	232	case SH7750_MMUCR_A7:
	233	return s->cpu->mmucr;
	234	case SH7750_PTEH_A7:
	235	return s->cpu->pteh;
	236	case SH7750_PTEL_A7:
	237	return s->cpu->ptel;
	238	case SH7750_TTB_A7:
	239	return s->cpu->ttb;
	240	case SH7750_TEA_A7:
	241	return s->cpu->tea;
	242	case SH7750_TRA_A7:
	243	return s->cpu->tra;
	244	case SH7750_EXPEVT_A7:
	245	return s->cpu->expevt;
	246	case SH7750_INTEVT_A7:
	247	return s->cpu->intevt;
	248	case SH7750_CCR_A7:
	249	return s->ccr;
	250	case 0x1f000030: /* Processor version PVR */
	251	return 0x00050000; /* SH7750R */
	252	case 0x1f000040: /* Processor version CVR */
	253	return 0x00110000; /* Minimum caches */
	254	case 0x1f000044: /* Processor version PRR */
	255	return 0x00000100; /* SH7750R */
	256	default:
	257	error_access("long read", addr);
	258	assert(0);
	259	}
	260	}
	261
	262	static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
	263	uint32_t mem_value)
	264	{
27c7ca7e FB	265	switch (addr) {
	266	/* PRECHARGE ? XXXXX */
	267	case SH7750_PRECHARGE0_A7:
	268	case SH7750_PRECHARGE1_A7:
	269	ignore_access("byte write", addr);
	270	return;
27c7ca7e FB	271	default:
	272	error_access("byte write", addr);
	273	assert(0);
	274	}
	275	}
	276
	277	static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
	278	uint32_t mem_value)
	279	{
	280	SH7750State *s = opaque;
	281	uint16_t temp;
	282
	283	switch (addr) {
	284	/* SDRAM controller */
27c7ca7e FB	285	case SH7750_BCR2_A7:
	286	case SH7750_BCR3_A7:
	287	case SH7750_RTCOR_A7:
	288	case SH7750_RTCNT_A7:
	289	case SH7750_RTCSR_A7:
	290	ignore_access("word write", addr);
	291	return;
	292	/* IO ports */
	293	case SH7750_PDTRA_A7:
	294	temp = porta_lines(s);
	295	s->pdtra = mem_value;
	296	porta_changed(s, temp);
	297	return;
	298	case SH7750_PDTRB_A7:
	299	temp = portb_lines(s);
	300	s->pdtrb = mem_value;
	301	portb_changed(s, temp);
	302	return;
	303	case SH7750_RFCR_A7:
	304	fprintf(stderr, "Write access to refresh count register\n");
	305	s->rfcr = mem_value;
	306	return;
27c7ca7e FB	307	case SH7750_GPIOIC_A7:
	308	s->gpioic = mem_value;
	309	if (mem_value != 0) {
	310	fprintf(stderr, "I/O interrupts not implemented\n");
	311	assert(0);
	312	}
	313	return;
3464c589 TS	314	case 0x1fd00000:
	315	s->icr = mem_value;
	316	return;
27c7ca7e FB	317	default:
	318	error_access("word write", addr);
	319	assert(0);
	320	}
	321	}
	322
	323	static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
	324	uint32_t mem_value)
	325	{
	326	SH7750State *s = opaque;
	327	uint16_t temp;
	328
	329	switch (addr) {
	330	/* SDRAM controller */
	331	case SH7750_BCR1_A7:
	332	case SH7750_BCR4_A7:
	333	case SH7750_WCR1_A7:
	334	case SH7750_WCR2_A7:
	335	case SH7750_WCR3_A7:
	336	case SH7750_MCR_A7:
	337	ignore_access("long write", addr);
	338	return;
	339	/* IO ports */
	340	case SH7750_PCTRA_A7:
	341	temp = porta_lines(s);
	342	s->pctra = mem_value;
	343	s->portdira = portdir(mem_value);
	344	s->portpullupa = portpullup(mem_value);
	345	porta_changed(s, temp);
	346	return;
	347	case SH7750_PCTRB_A7:
	348	temp = portb_lines(s);
	349	s->pctrb = mem_value;
	350	s->portdirb = portdir(mem_value);
	351	s->portpullupb = portpullup(mem_value);
	352	portb_changed(s, temp);
	353	return;
27c7ca7e FB	354	case SH7750_MMUCR_A7:
	355	s->cpu->mmucr = mem_value;
	356	return;
	357	case SH7750_PTEH_A7:
	358	s->cpu->pteh = mem_value;
	359	return;
	360	case SH7750_PTEL_A7:
	361	s->cpu->ptel = mem_value;
	362	return;
ea2b542a AJ	363	case SH7750_PTEA_A7:
	364	s->cpu->ptea = mem_value & 0x0000000f;
	365	return;
27c7ca7e FB	366	case SH7750_TTB_A7:
	367	s->cpu->ttb = mem_value;
	368	return;
	369	case SH7750_TEA_A7:
	370	s->cpu->tea = mem_value;
	371	return;
	372	case SH7750_TRA_A7:
	373	s->cpu->tra = mem_value & 0x000007ff;
	374	return;
	375	case SH7750_EXPEVT_A7:
	376	s->cpu->expevt = mem_value & 0x000007ff;
	377	return;
	378	case SH7750_INTEVT_A7:
	379	s->cpu->intevt = mem_value & 0x000007ff;
	380	return;
	381	case SH7750_CCR_A7:
	382	s->ccr = mem_value;
	383	return;
	384	default:
	385	error_access("long write", addr);
	386	assert(0);
	387	}
	388	}
	389
	390	static CPUReadMemoryFunc *sh7750_mem_read[] = {
	391	sh7750_mem_readb,
	392	sh7750_mem_readw,
	393	sh7750_mem_readl
	394	};
	395
	396	static CPUWriteMemoryFunc *sh7750_mem_write[] = {
	397	sh7750_mem_writeb,
	398	sh7750_mem_writew,
	399	sh7750_mem_writel
	400	};
	401
80f515e6 AZ	402	/* sh775x interrupt controller tables for sh_intc.c
	403	* stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
	404	*/
	405
	406	enum {
	407	UNUSED = 0,
	408
	409	/* interrupt sources */
	410	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
	411	HUDI, GPIOI,
	412	DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
	413	DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
	414	DMAC_DMAE,
	415	PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	416	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
	417	TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
	418	RTC_ATI, RTC_PRI, RTC_CUI,
	419	SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
	420	SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
	421	WDT,
	422	REF_RCMI, REF_ROVI,
	423
	424	/* interrupt groups */
	425	DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
	426
	427	NR_SOURCES,
	428	};
	429
	430	static struct intc_vect vectors[] = {
	431	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
	432	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	433	INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
	434	INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
	435	INTC_VECT(RTC_CUI, 0x4c0),
	436	INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
	437	INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
	438	INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
	439	INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
	440	INTC_VECT(WDT, 0x560),
	441	INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
	442	};
	443
	444	static struct intc_group groups[] = {
	445	INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
	446	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	447	INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
	448	INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
	449	INTC_GROUP(REF, REF_RCMI, REF_ROVI),
	450	};
	451
	452	static struct intc_prio_reg prio_registers[] = {
	453	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
	454	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
	455	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
	456	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
	457	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
	458	TMU4, TMU3,
	459	PCIC1, PCIC0_PCISERR } },
	460	};
	461
	462	/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
	463
	464	static struct intc_vect vectors_dma4[] = {
	465	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
466	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
467	INTC_VECT(DMAC_DMAE, 0x6c0),
468	};
469
470	static struct intc_group groups_dma4[] = {
471	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
472	DMAC_DMTE3, DMAC_DMAE),
473	};
474
475	/* SH7750R and SH7751R both have 8-channel DMA controllers */
476
477	static struct intc_vect vectors_dma8[] = {
478	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
479	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
480	INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
481	INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
482	INTC_VECT(DMAC_DMAE, 0x6c0),
483	};
484
485	static struct intc_group groups_dma8[] = {
486	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
487	DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
488	DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
489	};
490
491	/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
492
493	static struct intc_vect vectors_tmu34[] = {
494	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
495	};
496
497	static struct intc_mask_reg mask_registers[] = {
498	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
499	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
500	0, 0, 0, 0, 0, 0, TMU4, TMU3,
501	PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
502	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
503	PCIC1_PCIDMA3, PCIC0_PCISERR } },
504	};
505
506	/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
507
508	static struct intc_vect vectors_irlm[] = {
509	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
510	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
511	};
512
513	/* SH7751 and SH7751R both have PCI */
514
515	static struct intc_vect vectors_pci[] = {
516	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
517	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
518	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
519	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
520	};
521
522	static struct intc_group groups_pci[] = {
523	INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
524	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
525	};
526
527	#define SH_CPU_SH7750 (1 << 0)
528	#define SH_CPU_SH7750S (1 << 1)
529	#define SH_CPU_SH7750R (1 << 2)
530	#define SH_CPU_SH7751 (1 << 3)
531	#define SH_CPU_SH7751R (1 << 4)
532	#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 \| SH_CPU_SH7750S \| SH_CPU_SH7750R)
533	#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 \| SH_CPU_SH7751R)
534
27c7ca7e FB	535	SH7750State sh7750_init(CPUSH4State cpu)
	536	{
	537	SH7750State *s;
	538	int sh7750_io_memory;
80f515e6	539	int cpu_model = SH_CPU_SH7751R; /* for now */
27c7ca7e FB	540
	541	s = qemu_mallocz(sizeof(SH7750State));
	542	s->cpu = cpu;
	543	s->periph_freq = 60000000; /* 60MHz */
	544	sh7750_io_memory = cpu_register_io_memory(0,
	545	sh7750_mem_read,
	546	sh7750_mem_write, s);
	547	cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
2f062c72	548
80f515e6 AZ	549	sh_intc_init(&s->intc, NR_SOURCES,
	550	_INTC_ARRAY(mask_registers),
	551	_INTC_ARRAY(prio_registers));
	552
	553	sh_intc_register_sources(&s->intc,
	554	_INTC_ARRAY(vectors),
	555	_INTC_ARRAY(groups));
	556
e96e2044 TS	557	cpu->intc_handle = &s->intc;
e96e2044 TS	558
bf5b7423 AJ	559	sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
	560	sh_intc_source(&s->intc, SCI1_ERI),
	561	sh_intc_source(&s->intc, SCI1_RXI),
	562	sh_intc_source(&s->intc, SCI1_TXI),
	563	sh_intc_source(&s->intc, SCI1_TEI),
	564	NULL);
2f062c72	565	sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
bf5b7423 AJ	566	s->periph_freq, serial_hds[1],
	567	sh_intc_source(&s->intc, SCIF_ERI),
	568	sh_intc_source(&s->intc, SCIF_RXI),
	569	sh_intc_source(&s->intc, SCIF_TXI),
	570	NULL,
	571	sh_intc_source(&s->intc, SCIF_BRI));
cd1a3f68 TS	572
	573	tmu012_init(0x1fd80000,
	574	TMU012_FEAT_TOCR \| TMU012_FEAT_3CHAN \| TMU012_FEAT_EXTCLK,
703243a0 AZ	575	s->periph_freq,
	576	sh_intc_source(&s->intc, TMU0),
	577	sh_intc_source(&s->intc, TMU1),
	578	sh_intc_source(&s->intc, TMU2_TUNI),
	579	sh_intc_source(&s->intc, TMU2_TICPI));
80f515e6 AZ	580
	581	if (cpu_model & (SH_CPU_SH7750 \| SH_CPU_SH7750S \| SH_CPU_SH7751)) {
	582	sh_intc_register_sources(&s->intc,
	583	_INTC_ARRAY(vectors_dma4),
	584	_INTC_ARRAY(groups_dma4));
	585	}
	586
	587	if (cpu_model & (SH_CPU_SH7750R \| SH_CPU_SH7751R)) {
	588	sh_intc_register_sources(&s->intc,
	589	_INTC_ARRAY(vectors_dma8),
	590	_INTC_ARRAY(groups_dma8));
	591	}
	592
	593	if (cpu_model & (SH_CPU_SH7750R \| SH_CPU_SH7751 \| SH_CPU_SH7751R)) {
	594	sh_intc_register_sources(&s->intc,
	595	_INTC_ARRAY(vectors_tmu34),
f26ae302	596	NULL, 0);
703243a0 AZ	597	tmu012_init(0x1e100000, 0, s->periph_freq,
	598	sh_intc_source(&s->intc, TMU3),
	599	sh_intc_source(&s->intc, TMU4),
	600	NULL, NULL);
80f515e6 AZ	601	}
	602
	603	if (cpu_model & (SH_CPU_SH7751_ALL)) {
	604	sh_intc_register_sources(&s->intc,
	605	_INTC_ARRAY(vectors_pci),
	606	_INTC_ARRAY(groups_pci));
	607	}
	608
	609	if (cpu_model & (SH_CPU_SH7750S \| SH_CPU_SH7750R \| SH_CPU_SH7751_ALL)) {
	610	sh_intc_register_sources(&s->intc,
	611	_INTC_ARRAY(vectors_irlm),
f26ae302	612	NULL, 0);
80f515e6 AZ	613	}
80f515e6 AZ	614
27c7ca7e FB	615	return s;
27c7ca7e FB	616	}