[qemu.git] / hw / sh7750.c

/*
 * SH7750 device
 *
 * Copyright (c) 2007 Magnus Damm
 * Copyright (c) 2005 Samuel Tardieu
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <stdio.h>
#include <assert.h>
#include "vl.h"
#include "sh7750_regs.h"
#include "sh7750_regnames.h"
#include "sh_intc.h"

#define NB_DEVICES 4

typedef struct SH7750State {
    /* CPU */
    CPUSH4State *cpu;
    /* Peripheral frequency in Hz */
    uint32_t periph_freq;
    /* SDRAM controller */
    uint16_t rfcr;
    /* IO ports */
    uint16_t gpioic;
    uint32_t pctra;
    uint32_t pctrb;
    uint16_t portdira;		/* Cached */
    uint16_t portpullupa;	/* Cached */
    uint16_t portdirb;		/* Cached */
    uint16_t portpullupb;	/* Cached */
    uint16_t pdtra;
    uint16_t pdtrb;
    uint16_t periph_pdtra;	/* Imposed by the peripherals */
    uint16_t periph_portdira;	/* Direction seen from the peripherals */
    uint16_t periph_pdtrb;	/* Imposed by the peripherals */
    uint16_t periph_portdirb;	/* Direction seen from the peripherals */
    sh7750_io_device *devices[NB_DEVICES];	/* External peripherals */

    uint16_t icr;
    /* Cache */
    uint32_t ccr;

    struct intc_desc intc;
} SH7750State;


/**********************************************************************
 I/O ports
**********************************************************************/

int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
{
    int i;

    for (i = 0; i < NB_DEVICES; i++) {
	if (s->devices[i] == NULL) {
	    s->devices[i] = device;
	    return 0;
	}
    }
    return -1;
}

static uint16_t portdir(uint32_t v)
{
#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
    return
	EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
	EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
	EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
	EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
	EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
	EVENPORTMASK(0);
}

static uint16_t portpullup(uint32_t v)
{
#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
    return
	ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
	ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
	ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
	ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
	ODDPORTMASK(1) | ODDPORTMASK(0);
}

static uint16_t porta_lines(SH7750State * s)
{
    return (s->portdira & s->pdtra) |	/* CPU */
	(s->periph_portdira & s->periph_pdtra) |	/* Peripherals */
	(~(s->portdira | s->periph_portdira) & s->portpullupa);	/* Pullups */
}

static uint16_t portb_lines(SH7750State * s)
{
    return (s->portdirb & s->pdtrb) |	/* CPU */
	(s->periph_portdirb & s->periph_pdtrb) |	/* Peripherals */
	(~(s->portdirb | s->periph_portdirb) & s->portpullupb);	/* Pullups */
}

static void gen_port_interrupts(SH7750State * s)
{
    /* XXXXX interrupts not generated */
}

static void porta_changed(SH7750State * s, uint16_t prev)
{
    uint16_t currenta, changes;
    int i, r = 0;

#if 0
    fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
	    prev, porta_lines(s));
    fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
#endif
    currenta = porta_lines(s);
    if (currenta == prev)
	return;
    changes = currenta ^ prev;

    for (i = 0; i < NB_DEVICES; i++) {
	if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
	    r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
					       &s->periph_pdtra,
					       &s->periph_portdira,
					       &s->periph_pdtrb,
					       &s->periph_portdirb);
	}
    }

    if (r)
	gen_port_interrupts(s);
}

static void portb_changed(SH7750State * s, uint16_t prev)
{
    uint16_t currentb, changes;
    int i, r = 0;

    currentb = portb_lines(s);
    if (currentb == prev)
	return;
    changes = currentb ^ prev;

    for (i = 0; i < NB_DEVICES; i++) {
	if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
	    r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
					       &s->periph_pdtra,
					       &s->periph_portdira,
					       &s->periph_pdtrb,
					       &s->periph_portdirb);
	}
    }

    if (r)
	gen_port_interrupts(s);
}

/**********************************************************************
 Memory
**********************************************************************/

static void error_access(const char *kind, target_phys_addr_t addr)
{
    fprintf(stderr, "%s to %s (0x%08x) not supported\n",
	    kind, regname(addr), addr);
}

static void ignore_access(const char *kind, target_phys_addr_t addr)
{
    fprintf(stderr, "%s to %s (0x%08x) ignored\n",
	    kind, regname(addr), addr);
}

static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
{
    switch (addr) {
    default:
	error_access("byte read", addr);
	assert(0);
    }
}

static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
{
    SH7750State *s = opaque;

    switch (addr) {
    case SH7750_FRQCR_A7:
	return 0;
    case SH7750_RFCR_A7:
	fprintf(stderr,
		"Read access to refresh count register, incrementing\n");
	return s->rfcr++;
    case SH7750_PDTRA_A7:
	return porta_lines(s);
    case SH7750_PDTRB_A7:
	return portb_lines(s);
    case 0x1fd00000:
        return s->icr;
    default:
	error_access("word read", addr);
	assert(0);
    }
}

static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SH7750State *s = opaque;

    switch (addr) {
    case SH7750_MMUCR_A7:
	return s->cpu->mmucr;
    case SH7750_PTEH_A7:
	return s->cpu->pteh;
    case SH7750_PTEL_A7:
	return s->cpu->ptel;
    case SH7750_TTB_A7:
	return s->cpu->ttb;
    case SH7750_TEA_A7:
	return s->cpu->tea;
    case SH7750_TRA_A7:
	return s->cpu->tra;
    case SH7750_EXPEVT_A7:
	return s->cpu->expevt;
    case SH7750_INTEVT_A7:
	return s->cpu->intevt;
    case SH7750_CCR_A7:
	return s->ccr;
    case 0x1f000030:		/* Processor version PVR */
	return 0x00050000;	/* SH7750R */
    case 0x1f000040:		/* Processor version CVR */
	return 0x00110000;	/* Minimum caches */
    case 0x1f000044:		/* Processor version PRR */
	return 0x00000100;	/* SH7750R */
    default:
	error_access("long read", addr);
	assert(0);
    }
}

static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{
    switch (addr) {
	/* PRECHARGE ? XXXXX */
    case SH7750_PRECHARGE0_A7:
    case SH7750_PRECHARGE1_A7:
	ignore_access("byte write", addr);
	return;
    default:
	error_access("byte write", addr);
	assert(0);
    }
}

static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{
    SH7750State *s = opaque;
    uint16_t temp;

    switch (addr) {
	/* SDRAM controller */
    case SH7750_BCR2_A7:
    case SH7750_BCR3_A7:
    case SH7750_RTCOR_A7:
    case SH7750_RTCNT_A7:
    case SH7750_RTCSR_A7:
	ignore_access("word write", addr);
	return;
	/* IO ports */
    case SH7750_PDTRA_A7:
	temp = porta_lines(s);
	s->pdtra = mem_value;
	porta_changed(s, temp);
	return;
    case SH7750_PDTRB_A7:
	temp = portb_lines(s);
	s->pdtrb = mem_value;
	portb_changed(s, temp);
	return;
    case SH7750_RFCR_A7:
	fprintf(stderr, "Write access to refresh count register\n");
	s->rfcr = mem_value;
	return;
    case SH7750_GPIOIC_A7:
	s->gpioic = mem_value;
	if (mem_value != 0) {
	    fprintf(stderr, "I/O interrupts not implemented\n");
	    assert(0);
	}
	return;
    case 0x1fd00000:
        s->icr = mem_value;
	return;
    default:
	error_access("word write", addr);
	assert(0);
    }
}

static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{
    SH7750State *s = opaque;
    uint16_t temp;

    switch (addr) {
	/* SDRAM controller */
    case SH7750_BCR1_A7:
    case SH7750_BCR4_A7:
    case SH7750_WCR1_A7:
    case SH7750_WCR2_A7:
    case SH7750_WCR3_A7:
    case SH7750_MCR_A7:
	ignore_access("long write", addr);
	return;
	/* IO ports */
    case SH7750_PCTRA_A7:
	temp = porta_lines(s);
	s->pctra = mem_value;
	s->portdira = portdir(mem_value);
	s->portpullupa = portpullup(mem_value);
	porta_changed(s, temp);
	return;
    case SH7750_PCTRB_A7:
	temp = portb_lines(s);
	s->pctrb = mem_value;
	s->portdirb = portdir(mem_value);
	s->portpullupb = portpullup(mem_value);
	portb_changed(s, temp);
	return;
    case SH7750_MMUCR_A7:
	s->cpu->mmucr = mem_value;
	return;
    case SH7750_PTEH_A7:
	s->cpu->pteh = mem_value;
	return;
    case SH7750_PTEL_A7:
	s->cpu->ptel = mem_value;
	return;
    case SH7750_TTB_A7:
	s->cpu->ttb = mem_value;
	return;
    case SH7750_TEA_A7:
	s->cpu->tea = mem_value;
	return;
    case SH7750_TRA_A7:
	s->cpu->tra = mem_value & 0x000007ff;
	return;
    case SH7750_EXPEVT_A7:
	s->cpu->expevt = mem_value & 0x000007ff;
	return;
    case SH7750_INTEVT_A7:
	s->cpu->intevt = mem_value & 0x000007ff;
	return;
    case SH7750_CCR_A7:
	s->ccr = mem_value;
	return;
    default:
	error_access("long write", addr);
	assert(0);
    }
}

static CPUReadMemoryFunc *sh7750_mem_read[] = {
    sh7750_mem_readb,
    sh7750_mem_readw,
    sh7750_mem_readl
};

static CPUWriteMemoryFunc *sh7750_mem_write[] = {
    sh7750_mem_writeb,
    sh7750_mem_writew,
    sh7750_mem_writel
};

/* sh775x interrupt controller tables for sh_intc.c
 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
 */

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
	HUDI, GPIOI,
	DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
	DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
	DMAC_DMAE,
	PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
	TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
	RTC_ATI, RTC_PRI, RTC_CUI,
	SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
	SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
	WDT,
	REF_RCMI, REF_ROVI,

	/* interrupt groups */
	DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,

	NR_SOURCES,
};

static struct intc_vect vectors[] = {
	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
	INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
	INTC_VECT(RTC_CUI, 0x4c0),
	INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
	INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
	INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
	INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
	INTC_VECT(WDT, 0x560),
	INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
};

static struct intc_group groups[] = {
	INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
	INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
	INTC_GROUP(REF, REF_RCMI, REF_ROVI),
};

static struct intc_prio_reg prio_registers[] = {
	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
						 TMU4, TMU3,
						 PCIC1, PCIC0_PCISERR } },
};

/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */

static struct intc_vect vectors_dma4[] = {
	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
	INTC_VECT(DMAC_DMAE, 0x6c0),
};

static struct intc_group groups_dma4[] = {
	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
		   DMAC_DMTE3, DMAC_DMAE),
};

/* SH7750R and SH7751R both have 8-channel DMA controllers */

static struct intc_vect vectors_dma8[] = {
	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
	INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
	INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
	INTC_VECT(DMAC_DMAE, 0x6c0),
};

static struct intc_group groups_dma8[] = {
	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
		   DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
		   DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
};

/* SH7750R, SH7751 and SH7751R all have two extra timer channels */

static struct intc_vect vectors_tmu34[] = {
	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
};

static struct intc_mask_reg mask_registers[] = {
	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	    0, 0, 0, 0, 0, 0, TMU4, TMU3,
	    PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
	    PCIC1_PCIDMA3, PCIC0_PCISERR } },
};

/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */

static struct intc_vect vectors_irlm[] = {
	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
};

/* SH7751 and SH7751R both have PCI */

static struct intc_vect vectors_pci[] = {
	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
};

static struct intc_group groups_pci[] = {
	INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
		   PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
};

#define SH_CPU_SH7750  (1 << 0)
#define SH_CPU_SH7750S (1 << 1)
#define SH_CPU_SH7750R (1 << 2)
#define SH_CPU_SH7751  (1 << 3)
#define SH_CPU_SH7751R (1 << 4)
#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)

SH7750State *sh7750_init(CPUSH4State * cpu)
{
    SH7750State *s;
    int sh7750_io_memory;
    int cpu_model = SH_CPU_SH7751R; /* for now */

    s = qemu_mallocz(sizeof(SH7750State));
    s->cpu = cpu;
    s->periph_freq = 60000000;	/* 60MHz */
    sh7750_io_memory = cpu_register_io_memory(0,
					      sh7750_mem_read,
					      sh7750_mem_write, s);
    cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);

    sh_intc_init(&s->intc, NR_SOURCES,
		 _INTC_ARRAY(mask_registers),
		 _INTC_ARRAY(prio_registers));

    sh_intc_register_sources(&s->intc, 
			     _INTC_ARRAY(vectors),
			     _INTC_ARRAY(groups));

    sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]);
    sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
		   s->periph_freq, serial_hds[1]);

    tmu012_init(0x1fd80000,
		TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
		s->periph_freq);


    if (cpu_model & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_dma4),
				 _INTC_ARRAY(groups_dma4));
    }

    if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_dma8),
				 _INTC_ARRAY(groups_dma8));
    }

    if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_tmu34),
				 NULL, 0);
        tmu012_init(0x1e100000, 0, s->periph_freq);
    }

    if (cpu_model & (SH_CPU_SH7751_ALL)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_pci),
				 _INTC_ARRAY(groups_pci));
    }

    if (cpu_model & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
        sh_intc_register_sources(&s->intc, 
				 _INTC_ARRAY(vectors_irlm),
				 NULL, 0);
    }

    return s;
}
Commit	Line	Data
27c7ca7e FB	1	/*
27c7ca7e FB	2	* SH7750 device
5fafdf24	3	*
80f515e6	4	* Copyright (c) 2007 Magnus Damm
27c7ca7e	5	* Copyright (c) 2005 Samuel Tardieu
5fafdf24	6	*
27c7ca7e FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include <stdio.h>
	26	#include <assert.h>
	27	#include "vl.h"
	28	#include "sh7750_regs.h"
	29	#include "sh7750_regnames.h"
80f515e6	30	#include "sh_intc.h"
27c7ca7e	31
27c7ca7e FB	32	#define NB_DEVICES 4
	33
	34	typedef struct SH7750State {
	35	/* CPU */
	36	CPUSH4State *cpu;
	37	/* Peripheral frequency in Hz */
	38	uint32_t periph_freq;
	39	/* SDRAM controller */
	40	uint16_t rfcr;
27c7ca7e FB	41	/* IO ports */
	42	uint16_t gpioic;
	43	uint32_t pctra;
	44	uint32_t pctrb;
	45	uint16_t portdira; /* Cached */
	46	uint16_t portpullupa; /* Cached */
	47	uint16_t portdirb; /* Cached */
	48	uint16_t portpullupb; /* Cached */
	49	uint16_t pdtra;
	50	uint16_t pdtrb;
	51	uint16_t periph_pdtra; /* Imposed by the peripherals */
	52	uint16_t periph_portdira; /* Direction seen from the peripherals */
	53	uint16_t periph_pdtrb; /* Imposed by the peripherals */
	54	uint16_t periph_portdirb; /* Direction seen from the peripherals */
	55	sh7750_io_device devices[NB_DEVICES]; / External peripherals */
3464c589 TS	56
3464c589 TS	57	uint16_t icr;
27c7ca7e FB	58	/* Cache */
27c7ca7e FB	59	uint32_t ccr;
27c7ca7e	60
80f515e6	61	struct intc_desc intc;
cd1a3f68	62	} SH7750State;
27c7ca7e	63
27c7ca7e FB	64
	65	/**********************************************************************
	66	I/O ports
	67	**********************************************************************/
	68
	69	int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
	70	{
	71	int i;
	72
	73	for (i = 0; i < NB_DEVICES; i++) {
	74	if (s->devices[i] == NULL) {
	75	s->devices[i] = device;
	76	return 0;
	77	}
	78	}
	79	return -1;
	80	}
	81
	82	static uint16_t portdir(uint32_t v)
	83	{
	84	#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
	85	return
	86	EVENPORTMASK(15) \| EVENPORTMASK(14) \| EVENPORTMASK(13) \|
	87	EVENPORTMASK(12) \| EVENPORTMASK(11) \| EVENPORTMASK(10) \|
	88	EVENPORTMASK(9) \| EVENPORTMASK(8) \| EVENPORTMASK(7) \|
	89	EVENPORTMASK(6) \| EVENPORTMASK(5) \| EVENPORTMASK(4) \|
	90	EVENPORTMASK(3) \| EVENPORTMASK(2) \| EVENPORTMASK(1) \|
	91	EVENPORTMASK(0);
	92	}
	93
	94	static uint16_t portpullup(uint32_t v)
	95	{
	96	#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
	97	return
	98	ODDPORTMASK(15) \| ODDPORTMASK(14) \| ODDPORTMASK(13) \|
	99	ODDPORTMASK(12) \| ODDPORTMASK(11) \| ODDPORTMASK(10) \|
	100	ODDPORTMASK(9) \| ODDPORTMASK(8) \| ODDPORTMASK(7) \| ODDPORTMASK(6) \|
	101	ODDPORTMASK(5) \| ODDPORTMASK(4) \| ODDPORTMASK(3) \| ODDPORTMASK(2) \|
	102	ODDPORTMASK(1) \| ODDPORTMASK(0);
	103	}
	104
	105	static uint16_t porta_lines(SH7750State * s)
	106	{
	107	return (s->portdira & s->pdtra) \| /* CPU */
	108	(s->periph_portdira & s->periph_pdtra) \| /* Peripherals */
	109	(~(s->portdira \| s->periph_portdira) & s->portpullupa); /* Pullups */
	110	}
	111
	112	static uint16_t portb_lines(SH7750State * s)
	113	{
	114	return (s->portdirb & s->pdtrb) \| /* CPU */
	115	(s->periph_portdirb & s->periph_pdtrb) \| /* Peripherals */
	116	(~(s->portdirb \| s->periph_portdirb) & s->portpullupb); /* Pullups */
	117	}
	118
	119	static void gen_port_interrupts(SH7750State * s)
	120	{
	121	/* XXXXX interrupts not generated */
	122	}
	123
	124	static void porta_changed(SH7750State * s, uint16_t prev)
	125	{
	126	uint16_t currenta, changes;
	127	int i, r = 0;
128
129	#if 0
130	fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
131	prev, porta_lines(s));
132	fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
133	#endif
134	currenta = porta_lines(s);
135	if (currenta == prev)
136	return;
137	changes = currenta ^ prev;
138
139	for (i = 0; i < NB_DEVICES; i++) {
140	if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
141	r \|= s->devices[i]->port_change_cb(currenta, portb_lines(s),
142	&s->periph_pdtra,
143	&s->periph_portdira,
144	&s->periph_pdtrb,
145	&s->periph_portdirb);
146	}
147	}
148
149	if (r)
150	gen_port_interrupts(s);
151	}
152
153	static void portb_changed(SH7750State * s, uint16_t prev)
154	{
155	uint16_t currentb, changes;
156	int i, r = 0;
157
158	currentb = portb_lines(s);
159	if (currentb == prev)
160	return;
161	changes = currentb ^ prev;
162
163	for (i = 0; i < NB_DEVICES; i++) {
164	if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
165	r \|= s->devices[i]->port_change_cb(portb_lines(s), currentb,
166	&s->periph_pdtra,
167	&s->periph_portdira,
168	&s->periph_pdtrb,
169	&s->periph_portdirb);
170	}
171	}
172
173	if (r)
174	gen_port_interrupts(s);
175	}
176
177	/**********************************************************************
178	Memory
179	**********************************************************************/
180
181	static void error_access(const char *kind, target_phys_addr_t addr)
182	{
183	fprintf(stderr, "%s to %s (0x%08x) not supported\n",
184	kind, regname(addr), addr);
185	}
186
187	static void ignore_access(const char *kind, target_phys_addr_t addr)
188	{
189	fprintf(stderr, "%s to %s (0x%08x) ignored\n",
190	kind, regname(addr), addr);
191	}
192
193	static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
194	{
27c7ca7e	195	switch (addr) {
27c7ca7e FB	196	default:
	197	error_access("byte read", addr);
	198	assert(0);
	199	}
	200	}
	201
	202	static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
	203	{
	204	SH7750State *s = opaque;
27c7ca7e FB	205
27c7ca7e FB	206	switch (addr) {
ed8e0a4d TS	207	case SH7750_FRQCR_A7:
ed8e0a4d TS	208	return 0;
27c7ca7e FB	209	case SH7750_RFCR_A7:
	210	fprintf(stderr,
	211	"Read access to refresh count register, incrementing\n");
	212	return s->rfcr++;
27c7ca7e FB	213	case SH7750_PDTRA_A7:
	214	return porta_lines(s);
	215	case SH7750_PDTRB_A7:
	216	return portb_lines(s);
3464c589 TS	217	case 0x1fd00000:
3464c589 TS	218	return s->icr;
27c7ca7e FB	219	default:
	220	error_access("word read", addr);
	221	assert(0);
	222	}
	223	}
	224
	225	static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
	226	{
	227	SH7750State *s = opaque;
	228
	229	switch (addr) {
	230	case SH7750_MMUCR_A7:
	231	return s->cpu->mmucr;
	232	case SH7750_PTEH_A7:
	233	return s->cpu->pteh;
	234	case SH7750_PTEL_A7:
	235	return s->cpu->ptel;
	236	case SH7750_TTB_A7:
	237	return s->cpu->ttb;
	238	case SH7750_TEA_A7:
	239	return s->cpu->tea;
	240	case SH7750_TRA_A7:
	241	return s->cpu->tra;
	242	case SH7750_EXPEVT_A7:
	243	return s->cpu->expevt;
	244	case SH7750_INTEVT_A7:
	245	return s->cpu->intevt;
	246	case SH7750_CCR_A7:
	247	return s->ccr;
	248	case 0x1f000030: /* Processor version PVR */
	249	return 0x00050000; /* SH7750R */
	250	case 0x1f000040: /* Processor version CVR */
	251	return 0x00110000; /* Minimum caches */
	252	case 0x1f000044: /* Processor version PRR */
	253	return 0x00000100; /* SH7750R */
	254	default:
	255	error_access("long read", addr);
	256	assert(0);
	257	}
	258	}
	259
	260	static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
	261	uint32_t mem_value)
	262	{
27c7ca7e FB	263	switch (addr) {
	264	/* PRECHARGE ? XXXXX */
	265	case SH7750_PRECHARGE0_A7:
	266	case SH7750_PRECHARGE1_A7:
	267	ignore_access("byte write", addr);
	268	return;
27c7ca7e FB	269	default:
	270	error_access("byte write", addr);
	271	assert(0);
	272	}
	273	}
	274
	275	static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
	276	uint32_t mem_value)
	277	{
	278	SH7750State *s = opaque;
	279	uint16_t temp;
	280
	281	switch (addr) {
	282	/* SDRAM controller */
27c7ca7e FB	283	case SH7750_BCR2_A7:
	284	case SH7750_BCR3_A7:
	285	case SH7750_RTCOR_A7:
	286	case SH7750_RTCNT_A7:
	287	case SH7750_RTCSR_A7:
	288	ignore_access("word write", addr);
	289	return;
	290	/* IO ports */
	291	case SH7750_PDTRA_A7:
	292	temp = porta_lines(s);
	293	s->pdtra = mem_value;
	294	porta_changed(s, temp);
	295	return;
	296	case SH7750_PDTRB_A7:
	297	temp = portb_lines(s);
	298	s->pdtrb = mem_value;
	299	portb_changed(s, temp);
	300	return;
	301	case SH7750_RFCR_A7:
	302	fprintf(stderr, "Write access to refresh count register\n");
	303	s->rfcr = mem_value;
	304	return;
27c7ca7e FB	305	case SH7750_GPIOIC_A7:
	306	s->gpioic = mem_value;
	307	if (mem_value != 0) {
	308	fprintf(stderr, "I/O interrupts not implemented\n");
	309	assert(0);
	310	}
	311	return;
3464c589 TS	312	case 0x1fd00000:
	313	s->icr = mem_value;
	314	return;
27c7ca7e FB	315	default:
	316	error_access("word write", addr);
	317	assert(0);
	318	}
	319	}
	320
	321	static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
	322	uint32_t mem_value)
	323	{
	324	SH7750State *s = opaque;
	325	uint16_t temp;
	326
	327	switch (addr) {
	328	/* SDRAM controller */
	329	case SH7750_BCR1_A7:
	330	case SH7750_BCR4_A7:
	331	case SH7750_WCR1_A7:
	332	case SH7750_WCR2_A7:
	333	case SH7750_WCR3_A7:
	334	case SH7750_MCR_A7:
	335	ignore_access("long write", addr);
	336	return;
	337	/* IO ports */
	338	case SH7750_PCTRA_A7:
	339	temp = porta_lines(s);
	340	s->pctra = mem_value;
	341	s->portdira = portdir(mem_value);
	342	s->portpullupa = portpullup(mem_value);
	343	porta_changed(s, temp);
	344	return;
	345	case SH7750_PCTRB_A7:
	346	temp = portb_lines(s);
	347	s->pctrb = mem_value;
	348	s->portdirb = portdir(mem_value);
	349	s->portpullupb = portpullup(mem_value);
	350	portb_changed(s, temp);
	351	return;
27c7ca7e FB	352	case SH7750_MMUCR_A7:
	353	s->cpu->mmucr = mem_value;
	354	return;
	355	case SH7750_PTEH_A7:
	356	s->cpu->pteh = mem_value;
	357	return;
	358	case SH7750_PTEL_A7:
	359	s->cpu->ptel = mem_value;
	360	return;
	361	case SH7750_TTB_A7:
	362	s->cpu->ttb = mem_value;
	363	return;
	364	case SH7750_TEA_A7:
	365	s->cpu->tea = mem_value;
	366	return;
	367	case SH7750_TRA_A7:
	368	s->cpu->tra = mem_value & 0x000007ff;
	369	return;
	370	case SH7750_EXPEVT_A7:
	371	s->cpu->expevt = mem_value & 0x000007ff;
	372	return;
	373	case SH7750_INTEVT_A7:
	374	s->cpu->intevt = mem_value & 0x000007ff;
	375	return;
	376	case SH7750_CCR_A7:
	377	s->ccr = mem_value;
	378	return;
	379	default:
	380	error_access("long write", addr);
	381	assert(0);
	382	}
	383	}
	384
	385	static CPUReadMemoryFunc *sh7750_mem_read[] = {
	386	sh7750_mem_readb,
	387	sh7750_mem_readw,
	388	sh7750_mem_readl
	389	};
	390
	391	static CPUWriteMemoryFunc *sh7750_mem_write[] = {
	392	sh7750_mem_writeb,
	393	sh7750_mem_writew,
	394	sh7750_mem_writel
	395	};
	396
80f515e6 AZ	397	/* sh775x interrupt controller tables for sh_intc.c
	398	* stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
	399	*/
	400
	401	enum {
	402	UNUSED = 0,
	403
	404	/* interrupt sources */
	405	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
	406	HUDI, GPIOI,
	407	DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
	408	DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
	409	DMAC_DMAE,
	410	PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	411	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
	412	TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
	413	RTC_ATI, RTC_PRI, RTC_CUI,
	414	SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
	415	SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
	416	WDT,
	417	REF_RCMI, REF_ROVI,
	418
	419	/* interrupt groups */
	420	DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
	421
	422	NR_SOURCES,
	423	};
	424
	425	static struct intc_vect vectors[] = {
	426	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
	427	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	428	INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
	429	INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
	430	INTC_VECT(RTC_CUI, 0x4c0),
	431	INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
	432	INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
	433	INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
	434	INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
	435	INTC_VECT(WDT, 0x560),
	436	INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
	437	};
	438
	439	static struct intc_group groups[] = {
	440	INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
	441	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	442	INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
	443	INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
	444	INTC_GROUP(REF, REF_RCMI, REF_ROVI),
	445	};
	446
	447	static struct intc_prio_reg prio_registers[] = {
	448	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
	449	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
	450	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
	451	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
	452	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
	453	TMU4, TMU3,
	454	PCIC1, PCIC0_PCISERR } },
	455	};
	456
	457	/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
	458
	459	static struct intc_vect vectors_dma4[] = {
	460	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
461	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
462	INTC_VECT(DMAC_DMAE, 0x6c0),
463	};
464
465	static struct intc_group groups_dma4[] = {
466	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
467	DMAC_DMTE3, DMAC_DMAE),
468	};
469
470	/* SH7750R and SH7751R both have 8-channel DMA controllers */
471
472	static struct intc_vect vectors_dma8[] = {
473	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
474	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
475	INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
476	INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
477	INTC_VECT(DMAC_DMAE, 0x6c0),
478	};
479
480	static struct intc_group groups_dma8[] = {
481	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
482	DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
483	DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
484	};
485
486	/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
487
488	static struct intc_vect vectors_tmu34[] = {
489	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
490	};
491
492	static struct intc_mask_reg mask_registers[] = {
493	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
494	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
495	0, 0, 0, 0, 0, 0, TMU4, TMU3,
496	PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
497	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
498	PCIC1_PCIDMA3, PCIC0_PCISERR } },
499	};
500
501	/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
502
503	static struct intc_vect vectors_irlm[] = {
504	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
505	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
506	};
507
508	/* SH7751 and SH7751R both have PCI */
509
510	static struct intc_vect vectors_pci[] = {
511	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
512	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
513	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
514	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
515	};
516
517	static struct intc_group groups_pci[] = {
518	INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
519	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
520	};
521
522	#define SH_CPU_SH7750 (1 << 0)
523	#define SH_CPU_SH7750S (1 << 1)
524	#define SH_CPU_SH7750R (1 << 2)
525	#define SH_CPU_SH7751 (1 << 3)
526	#define SH_CPU_SH7751R (1 << 4)
527	#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 \| SH_CPU_SH7750S \| SH_CPU_SH7750R)
528	#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 \| SH_CPU_SH7751R)
529
27c7ca7e FB	530	SH7750State sh7750_init(CPUSH4State cpu)
	531	{
	532	SH7750State *s;
	533	int sh7750_io_memory;
80f515e6	534	int cpu_model = SH_CPU_SH7751R; /* for now */
27c7ca7e FB	535
	536	s = qemu_mallocz(sizeof(SH7750State));
	537	s->cpu = cpu;
	538	s->periph_freq = 60000000; /* 60MHz */
	539	sh7750_io_memory = cpu_register_io_memory(0,
	540	sh7750_mem_read,
	541	sh7750_mem_write, s);
	542	cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
2f062c72	543
80f515e6 AZ	544	sh_intc_init(&s->intc, NR_SOURCES,
	545	_INTC_ARRAY(mask_registers),
	546	_INTC_ARRAY(prio_registers));
	547
	548	sh_intc_register_sources(&s->intc,
	549	_INTC_ARRAY(vectors),
	550	_INTC_ARRAY(groups));
	551
2f062c72 TS	552	sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]);
	553	sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
	554	s->periph_freq, serial_hds[1]);
cd1a3f68 TS	555
	556	tmu012_init(0x1fd80000,
	557	TMU012_FEAT_TOCR \| TMU012_FEAT_3CHAN \| TMU012_FEAT_EXTCLK,
	558	s->periph_freq);
80f515e6 AZ	559
	560
	561	if (cpu_model & (SH_CPU_SH7750 \| SH_CPU_SH7750S \| SH_CPU_SH7751)) {
	562	sh_intc_register_sources(&s->intc,
	563	_INTC_ARRAY(vectors_dma4),
	564	_INTC_ARRAY(groups_dma4));
	565	}
	566
	567	if (cpu_model & (SH_CPU_SH7750R \| SH_CPU_SH7751R)) {
	568	sh_intc_register_sources(&s->intc,
	569	_INTC_ARRAY(vectors_dma8),
	570	_INTC_ARRAY(groups_dma8));
	571	}
	572
	573	if (cpu_model & (SH_CPU_SH7750R \| SH_CPU_SH7751 \| SH_CPU_SH7751R)) {
	574	sh_intc_register_sources(&s->intc,
	575	_INTC_ARRAY(vectors_tmu34),
f26ae302	576	NULL, 0);
80f515e6 AZ	577	tmu012_init(0x1e100000, 0, s->periph_freq);
	578	}
	579
	580	if (cpu_model & (SH_CPU_SH7751_ALL)) {
	581	sh_intc_register_sources(&s->intc,
	582	_INTC_ARRAY(vectors_pci),
	583	_INTC_ARRAY(groups_pci));
	584	}
	585
	586	if (cpu_model & (SH_CPU_SH7750S \| SH_CPU_SH7750R \| SH_CPU_SH7751_ALL)) {
	587	sh_intc_register_sources(&s->intc,
	588	_INTC_ARRAY(vectors_irlm),
f26ae302	589	NULL, 0);
80f515e6 AZ	590	}
80f515e6 AZ	591
27c7ca7e FB	592	return s;
27c7ca7e FB	593	}