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Fix some new warnings introduced after r5022
[qemu.git] / hw / sh7750.c
CommitLineData
27c7ca7e
FB		 1/*
2 * SH7750 device
5fafdf24 3 *
80f515e6 4 * Copyright (c) 2007 Magnus Damm
27c7ca7e 5 * Copyright (c) 2005 Samuel Tardieu
5fafdf24 6 *
27c7ca7e
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25#include <stdio.h>
26#include <assert.h>
87ecb68b
PB		 27#include "hw.h"
28#include "sh.h"
29#include "sysemu.h"
27c7ca7e
FB		 30#include "sh7750_regs.h"
31#include "sh7750_regnames.h"
80f515e6 32#include "sh_intc.h"
06afe2c8 33#include "exec-all.h"
29e179bc 34#include "cpu.h"
27c7ca7e 35
27c7ca7e
FB		 36#define NB_DEVICES 4
37
38typedef struct SH7750State {
39 /* CPU */
40 CPUSH4State *cpu;
41 /* Peripheral frequency in Hz */
42 uint32_t periph_freq;
43 /* SDRAM controller */
c2f01775
AZ		 44 uint32_t bcr1;
45 uint32_t bcr2;
27c7ca7e 46 uint16_t rfcr;
27c7ca7e
FB		 47 /* IO ports */
48 uint16_t gpioic;
49 uint32_t pctra;
50 uint32_t pctrb;
51 uint16_t portdira; /* Cached */
52 uint16_t portpullupa; /* Cached */
53 uint16_t portdirb; /* Cached */
54 uint16_t portpullupb; /* Cached */
55 uint16_t pdtra;
56 uint16_t pdtrb;
57 uint16_t periph_pdtra; /* Imposed by the peripherals */
58 uint16_t periph_portdira; /* Direction seen from the peripherals */
59 uint16_t periph_pdtrb; /* Imposed by the peripherals */
60 uint16_t periph_portdirb; /* Direction seen from the peripherals */
61 sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
3464c589
TS		 62
63 uint16_t icr;
27c7ca7e
FB		 64 /* Cache */
65 uint32_t ccr;
27c7ca7e 66
80f515e6 67 struct intc_desc intc;
cd1a3f68 68} SH7750State;
27c7ca7e 69
27c7ca7e
FB		 70
71/**********************************************************************
72 I/O ports
73**********************************************************************/
74
75int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
76{
77 int i;
78
79 for (i = 0; i < NB_DEVICES; i++) {
80 if (s->devices[i] == NULL) {
81 s->devices[i] = device;
82 return 0;
83 }
84 }
85 return -1;
86}
87
88static uint16_t portdir(uint32_t v)
89{
90#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
91 return
92 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
93 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
94 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
95 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
96 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
97 EVENPORTMASK(0);
98}
99
100static uint16_t portpullup(uint32_t v)
101{
102#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
103 return
104 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
105 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
106 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
107 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
108 ODDPORTMASK(1) | ODDPORTMASK(0);
109}
110
111static uint16_t porta_lines(SH7750State * s)
112{
113 return (s->portdira & s->pdtra) | /* CPU */
114 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */
115 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
116}
117
118static uint16_t portb_lines(SH7750State * s)
119{
120 return (s->portdirb & s->pdtrb) | /* CPU */
121 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
122 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
123}
124
125static void gen_port_interrupts(SH7750State * s)
126{
127 /* XXXXX interrupts not generated */
128}
129
130static void porta_changed(SH7750State * s, uint16_t prev)
131{
132 uint16_t currenta, changes;
133 int i, r = 0;
134
135#if 0
136 fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
137 prev, porta_lines(s));
138 fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
139#endif
140 currenta = porta_lines(s);
141 if (currenta == prev)
142 return;
143 changes = currenta ^ prev;
144
145 for (i = 0; i < NB_DEVICES; i++) {
146 if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
147 r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
148 &s->periph_pdtra,
149 &s->periph_portdira,
150 &s->periph_pdtrb,
151 &s->periph_portdirb);
152 }
153 }
154
155 if (r)
156 gen_port_interrupts(s);
157}
158
159static void portb_changed(SH7750State * s, uint16_t prev)
160{
161 uint16_t currentb, changes;
162 int i, r = 0;
163
164 currentb = portb_lines(s);
165 if (currentb == prev)
166 return;
167 changes = currentb ^ prev;
168
169 for (i = 0; i < NB_DEVICES; i++) {
170 if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
171 r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
172 &s->periph_pdtra,
173 &s->periph_portdira,
174 &s->periph_pdtrb,
175 &s->periph_portdirb);
176 }
177 }
178
179 if (r)
180 gen_port_interrupts(s);
181}
182
183/**********************************************************************
184 Memory
185**********************************************************************/
186
187static void error_access(const char *kind, target_phys_addr_t addr)
188{
526ccb7a 189 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
27c7ca7e
FB		 190 kind, regname(addr), addr);
191}
192
193static void ignore_access(const char *kind, target_phys_addr_t addr)
194{
526ccb7a 195 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
27c7ca7e
FB		 196 kind, regname(addr), addr);
197}
198
199static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
200{
27c7ca7e 201 switch (addr) {
27c7ca7e
FB		 202 default:
203 error_access("byte read", addr);
204 assert(0);
205 }
206}
207
208static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
209{
210 SH7750State *s = opaque;
27c7ca7e
FB		 211
212 switch (addr) {
c2f01775
AZ		 213 case SH7750_BCR2_A7:
214 return s->bcr2;
ed8e0a4d
TS		 215 case SH7750_FRQCR_A7:
216 return 0;
27c7ca7e
FB		 217 case SH7750_RFCR_A7:
218 fprintf(stderr,
219 "Read access to refresh count register, incrementing\n");
220 return s->rfcr++;
27c7ca7e
FB		 221 case SH7750_PDTRA_A7:
222 return porta_lines(s);
223 case SH7750_PDTRB_A7:
224 return portb_lines(s);
3464c589
TS		 225 case 0x1fd00000:
226 return s->icr;
27c7ca7e
FB		 227 default:
228 error_access("word read", addr);
229 assert(0);
230 }
231}
232
233static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
234{
235 SH7750State *s = opaque;
236
237 switch (addr) {
c2f01775
AZ		 238 case SH7750_BCR1_A7:
239 return s->bcr1;
240 case SH7750_BCR4_A7:
241 case SH7750_WCR1_A7:
242 case SH7750_WCR2_A7:
243 case SH7750_WCR3_A7:
244 case SH7750_MCR_A7:
245 ignore_access("long read", addr);
246 return 0;
27c7ca7e
FB		 247 case SH7750_MMUCR_A7:
248 return s->cpu->mmucr;
249 case SH7750_PTEH_A7:
250 return s->cpu->pteh;
251 case SH7750_PTEL_A7:
252 return s->cpu->ptel;
253 case SH7750_TTB_A7:
254 return s->cpu->ttb;
255 case SH7750_TEA_A7:
256 return s->cpu->tea;
257 case SH7750_TRA_A7:
258 return s->cpu->tra;
259 case SH7750_EXPEVT_A7:
260 return s->cpu->expevt;
261 case SH7750_INTEVT_A7:
262 return s->cpu->intevt;
263 case SH7750_CCR_A7:
264 return s->ccr;
0fd3ca30
AJ		 265 case 0x1f000030: /* Processor version */
266 return s->cpu->pvr;
267 case 0x1f000040: /* Cache version */
268 return s->cpu->cvr;
269 case 0x1f000044: /* Processor revision */
270 return s->cpu->prr;
27c7ca7e
FB		 271 default:
272 error_access("long read", addr);
273 assert(0);
274 }
275}
276
277static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
278 uint32_t mem_value)
279{
27c7ca7e
FB		 280 switch (addr) {
281 /* PRECHARGE ? XXXXX */
282 case SH7750_PRECHARGE0_A7:
283 case SH7750_PRECHARGE1_A7:
284 ignore_access("byte write", addr);
285 return;
27c7ca7e
FB		 286 default:
287 error_access("byte write", addr);
288 assert(0);
289 }
290}
291
292static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
293 uint32_t mem_value)
294{
295 SH7750State *s = opaque;
296 uint16_t temp;
297
298 switch (addr) {
299 /* SDRAM controller */
27c7ca7e 300 case SH7750_BCR2_A7:
c2f01775
AZ		 301 s->bcr2 = mem_value;
302 return;
27c7ca7e
FB		 303 case SH7750_BCR3_A7:
304 case SH7750_RTCOR_A7:
305 case SH7750_RTCNT_A7:
306 case SH7750_RTCSR_A7:
307 ignore_access("word write", addr);
308 return;
309 /* IO ports */
310 case SH7750_PDTRA_A7:
311 temp = porta_lines(s);
312 s->pdtra = mem_value;
313 porta_changed(s, temp);
314 return;
315 case SH7750_PDTRB_A7:
316 temp = portb_lines(s);
317 s->pdtrb = mem_value;
318 portb_changed(s, temp);
319 return;
320 case SH7750_RFCR_A7:
321 fprintf(stderr, "Write access to refresh count register\n");
322 s->rfcr = mem_value;
323 return;
27c7ca7e
FB		 324 case SH7750_GPIOIC_A7:
325 s->gpioic = mem_value;
326 if (mem_value != 0) {
327 fprintf(stderr, "I/O interrupts not implemented\n");
328 assert(0);
329 }
330 return;
3464c589
TS		 331 case 0x1fd00000:
332 s->icr = mem_value;
333 return;
27c7ca7e
FB		 334 default:
335 error_access("word write", addr);
336 assert(0);
337 }
338}
339
340static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
341 uint32_t mem_value)
342{
343 SH7750State *s = opaque;
344 uint16_t temp;
345
346 switch (addr) {
347 /* SDRAM controller */
348 case SH7750_BCR1_A7:
c2f01775
AZ		 349 s->bcr1 = mem_value;
350 return;
27c7ca7e
FB		 351 case SH7750_BCR4_A7:
352 case SH7750_WCR1_A7:
353 case SH7750_WCR2_A7:
354 case SH7750_WCR3_A7:
355 case SH7750_MCR_A7:
356 ignore_access("long write", addr);
357 return;
358 /* IO ports */
359 case SH7750_PCTRA_A7:
360 temp = porta_lines(s);
361 s->pctra = mem_value;
362 s->portdira = portdir(mem_value);
363 s->portpullupa = portpullup(mem_value);
364 porta_changed(s, temp);
365 return;
366 case SH7750_PCTRB_A7:
367 temp = portb_lines(s);
368 s->pctrb = mem_value;
369 s->portdirb = portdir(mem_value);
370 s->portpullupb = portpullup(mem_value);
371 portb_changed(s, temp);
372 return;
27c7ca7e
FB		 373 case SH7750_MMUCR_A7:
374 s->cpu->mmucr = mem_value;
375 return;
376 case SH7750_PTEH_A7:
06afe2c8
AJ		 377 /* If asid changes, clear all registered tlb entries. */
378 if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
379 tlb_flush(s->cpu, 1);
27c7ca7e
FB		 380 s->cpu->pteh = mem_value;
381 return;
382 case SH7750_PTEL_A7:
383 s->cpu->ptel = mem_value;
384 return;
ea2b542a
AJ		 385 case SH7750_PTEA_A7:
386 s->cpu->ptea = mem_value & 0x0000000f;
387 return;
27c7ca7e
FB		 388 case SH7750_TTB_A7:
389 s->cpu->ttb = mem_value;
390 return;
391 case SH7750_TEA_A7:
392 s->cpu->tea = mem_value;
393 return;
394 case SH7750_TRA_A7:
395 s->cpu->tra = mem_value & 0x000007ff;
396 return;
397 case SH7750_EXPEVT_A7:
398 s->cpu->expevt = mem_value & 0x000007ff;
399 return;
400 case SH7750_INTEVT_A7:
401 s->cpu->intevt = mem_value & 0x000007ff;
402 return;
403 case SH7750_CCR_A7:
404 s->ccr = mem_value;
405 return;
406 default:
407 error_access("long write", addr);
408 assert(0);
409 }
410}
411
412static CPUReadMemoryFunc *sh7750_mem_read[] = {
413 sh7750_mem_readb,
414 sh7750_mem_readw,
415 sh7750_mem_readl
416};
417
418static CPUWriteMemoryFunc *sh7750_mem_write[] = {
419 sh7750_mem_writeb,
420 sh7750_mem_writew,
421 sh7750_mem_writel
422};
423
80f515e6
AZ		 424/* sh775x interrupt controller tables for sh_intc.c
425 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
426 */
427
428enum {
429 UNUSED = 0,
430
431 /* interrupt sources */
c6d86a33
AZ		 432 IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
433 IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
434 IRL0, IRL1, IRL2, IRL3,
80f515e6
AZ		 435 HUDI, GPIOI,
436 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
437 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
438 DMAC_DMAE,
439 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
440 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
441 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
442 RTC_ATI, RTC_PRI, RTC_CUI,
443 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
444 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
445 WDT,
446 REF_RCMI, REF_ROVI,
447
448 /* interrupt groups */
449 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
c6d86a33
AZ		 450 /* irl bundle */
451 IRL,
80f515e6
AZ		 452
453 NR_SOURCES,
454};
455
456static struct intc_vect vectors[] = {
457 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
458 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
459 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
460 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
461 INTC_VECT(RTC_CUI, 0x4c0),
462 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
463 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
464 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
465 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
466 INTC_VECT(WDT, 0x560),
467 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
468};
469
470static struct intc_group groups[] = {
471 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
472 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
473 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
474 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
475 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
476};
477
478static struct intc_prio_reg prio_registers[] = {
479 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
480 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
481 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
482 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
483 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
484 TMU4, TMU3,
485 PCIC1, PCIC0_PCISERR } },
486};
487
488/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
489
490static struct intc_vect vectors_dma4[] = {
491 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
492 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
493 INTC_VECT(DMAC_DMAE, 0x6c0),
494};
495
496static struct intc_group groups_dma4[] = {
497 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
498 DMAC_DMTE3, DMAC_DMAE),
499};
500
501/* SH7750R and SH7751R both have 8-channel DMA controllers */
502
503static struct intc_vect vectors_dma8[] = {
504 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
505 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
506 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
507 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
508 INTC_VECT(DMAC_DMAE, 0x6c0),
509};
510
511static struct intc_group groups_dma8[] = {
512 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
513 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
514 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
515};
516
517/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
518
519static struct intc_vect vectors_tmu34[] = {
520 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
521};
522
523static struct intc_mask_reg mask_registers[] = {
524 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
525 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
526 0, 0, 0, 0, 0, 0, TMU4, TMU3,
527 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
528 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
529 PCIC1_PCIDMA3, PCIC0_PCISERR } },
530};
531
532/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
533
534static struct intc_vect vectors_irlm[] = {
535 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
536 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
537};
538
539/* SH7751 and SH7751R both have PCI */
540
541static struct intc_vect vectors_pci[] = {
542 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
543 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
544 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
545 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
546};
547
548static struct intc_group groups_pci[] = {
549 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
550 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
551};
552
c6d86a33
AZ		 553static struct intc_vect vectors_irl[] = {
554 INTC_VECT(IRL_0, 0x200),
555 INTC_VECT(IRL_1, 0x220),
556 INTC_VECT(IRL_2, 0x240),
557 INTC_VECT(IRL_3, 0x260),
558 INTC_VECT(IRL_4, 0x280),
559 INTC_VECT(IRL_5, 0x2a0),
560 INTC_VECT(IRL_6, 0x2c0),
561 INTC_VECT(IRL_7, 0x2e0),
562 INTC_VECT(IRL_8, 0x300),
563 INTC_VECT(IRL_9, 0x320),
564 INTC_VECT(IRL_A, 0x340),
565 INTC_VECT(IRL_B, 0x360),
566 INTC_VECT(IRL_C, 0x380),
567 INTC_VECT(IRL_D, 0x3a0),
568 INTC_VECT(IRL_E, 0x3c0),
569};
570
571static struct intc_group groups_irl[] = {
572 INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
573 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
574};
575
29e179bc
AJ		 576/**********************************************************************
577 Memory mapped cache and TLB
578**********************************************************************/
579
580#define MM_REGION_MASK 0x07000000
581#define MM_ICACHE_ADDR (0)
582#define MM_ICACHE_DATA (1)
583#define MM_ITLB_ADDR (2)
584#define MM_ITLB_DATA (3)
585#define MM_OCACHE_ADDR (4)
586#define MM_OCACHE_DATA (5)
587#define MM_UTLB_ADDR (6)
588#define MM_UTLB_DATA (7)
589#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
590
591static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
592{
593 assert(0);
594
595 return 0;
596}
597
598static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
599{
600 uint32_t ret = 0;
601
602 switch (MM_REGION_TYPE(addr)) {
603 case MM_ICACHE_ADDR:
604 case MM_ICACHE_DATA:
605 /* do nothing */
606 break;
607 case MM_ITLB_ADDR:
608 case MM_ITLB_DATA:
609 /* XXXXX */
610 assert(0);
611 break;
612 case MM_OCACHE_ADDR:
613 case MM_OCACHE_DATA:
614 /* do nothing */
615 break;
616 case MM_UTLB_ADDR:
617 case MM_UTLB_DATA:
618 /* XXXXX */
619 assert(0);
620 break;
621 default:
622 assert(0);
623 }
624
625 return ret;
626}
627
628static void invalid_write(void *opaque, target_phys_addr_t addr,
629 uint32_t mem_value)
630{
631 assert(0);
632}
633
634static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
635 uint32_t mem_value)
636{
637 SH7750State *s = opaque;
638
639 switch (MM_REGION_TYPE(addr)) {
640 case MM_ICACHE_ADDR:
641 case MM_ICACHE_DATA:
642 /* do nothing */
643 break;
644 case MM_ITLB_ADDR:
645 case MM_ITLB_DATA:
646 /* XXXXX */
647 assert(0);
648 break;
649 case MM_OCACHE_ADDR:
650 case MM_OCACHE_DATA:
651 /* do nothing */
652 break;
653 case MM_UTLB_ADDR:
654 cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
655 break;
656 case MM_UTLB_DATA:
657 /* XXXXX */
658 assert(0);
659 break;
660 default:
661 assert(0);
662 break;
663 }
664}
665
666static CPUReadMemoryFunc *sh7750_mmct_read[] = {
667 invalid_read,
668 invalid_read,
669 sh7750_mmct_readl
670};
671
672static CPUWriteMemoryFunc *sh7750_mmct_write[] = {
673 invalid_write,
674 invalid_write,
675 sh7750_mmct_writel
676};
677
27c7ca7e
FB		 678SH7750State *sh7750_init(CPUSH4State * cpu)
679{
680 SH7750State *s;
681 int sh7750_io_memory;
29e179bc 682 int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
27c7ca7e
FB		 683
684 s = qemu_mallocz(sizeof(SH7750State));
685 s->cpu = cpu;
686 s->periph_freq = 60000000; /* 60MHz */
687 sh7750_io_memory = cpu_register_io_memory(0,
688 sh7750_mem_read,
689 sh7750_mem_write, s);
8da3ff18
PB		 690 cpu_register_physical_memory_offset(0x1c000000, 0x04000000,
691 sh7750_io_memory, 0x1c000000);
2f062c72 692
29e179bc
AJ		 693 sh7750_mm_cache_and_tlb = cpu_register_io_memory(0,
694 sh7750_mmct_read,
695 sh7750_mmct_write, s);
696 cpu_register_physical_memory(0xf0000000, 0x08000000,
697 sh7750_mm_cache_and_tlb);
698
80f515e6
AZ		 699 sh_intc_init(&s->intc, NR_SOURCES,
700 _INTC_ARRAY(mask_registers),
701 _INTC_ARRAY(prio_registers));
702
0fd3ca30 703 sh_intc_register_sources(&s->intc,
80f515e6
AZ		 704 _INTC_ARRAY(vectors),
705 _INTC_ARRAY(groups));
706
e96e2044
TS		 707 cpu->intc_handle = &s->intc;
708
bf5b7423 709 sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
4e7ed2d1
AJ		 710 s->intc.irqs[SCI1_ERI],
711 s->intc.irqs[SCI1_RXI],
712 s->intc.irqs[SCI1_TXI],
713 s->intc.irqs[SCI1_TEI],
bf5b7423 714 NULL);
2f062c72 715 sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
bf5b7423 716 s->periph_freq, serial_hds[1],
4e7ed2d1
AJ		 717 s->intc.irqs[SCIF_ERI],
718 s->intc.irqs[SCIF_RXI],
719 s->intc.irqs[SCIF_TXI],
bf5b7423 720 NULL,
4e7ed2d1 721 s->intc.irqs[SCIF_BRI]);
cd1a3f68
TS		 722
723 tmu012_init(0x1fd80000,
724 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
703243a0 725 s->periph_freq,
96e2fc41
AJ		 726 s->intc.irqs[TMU0],
727 s->intc.irqs[TMU1],
728 s->intc.irqs[TMU2_TUNI],
729 s->intc.irqs[TMU2_TICPI]);
80f515e6 730
0fd3ca30
AJ		 731 if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
732 sh_intc_register_sources(&s->intc,
80f515e6
AZ		 733 _INTC_ARRAY(vectors_dma4),
734 _INTC_ARRAY(groups_dma4));
735 }
736
0fd3ca30
AJ		 737 if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
738 sh_intc_register_sources(&s->intc,
80f515e6
AZ		 739 _INTC_ARRAY(vectors_dma8),
740 _INTC_ARRAY(groups_dma8));
741 }
742
0fd3ca30
AJ		 743 if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
744 sh_intc_register_sources(&s->intc,
80f515e6 745 _INTC_ARRAY(vectors_tmu34),
f26ae302 746 NULL, 0);
703243a0 747 tmu012_init(0x1e100000, 0, s->periph_freq,
96e2fc41
AJ		 748 s->intc.irqs[TMU3],
749 s->intc.irqs[TMU4],
703243a0 750 NULL, NULL);
80f515e6
AZ		 751 }
752
0fd3ca30
AJ		 753 if (cpu->id & (SH_CPU_SH7751_ALL)) {
754 sh_intc_register_sources(&s->intc,
80f515e6
AZ		 755 _INTC_ARRAY(vectors_pci),
756 _INTC_ARRAY(groups_pci));
757 }
758
0fd3ca30
AJ		 759 if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
760 sh_intc_register_sources(&s->intc,
80f515e6 761 _INTC_ARRAY(vectors_irlm),
f26ae302 762 NULL, 0);
80f515e6
AZ		 763 }
764
c6d86a33
AZ		 765 sh_intc_register_sources(&s->intc,
766 _INTC_ARRAY(vectors_irl),
767 _INTC_ARRAY(groups_irl));
27c7ca7e
FB		 768 return s;
769}
c6d86a33
AZ		 770
771qemu_irq sh7750_irl(SH7750State *s)
772{
773 sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */
774 return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
775 1)[0];
776}
777
Qemu copy for testing