[qemu.git] / hw / sh_intc.c

/*
 * SuperH interrupt controller module
 *
 * Copyright (c) 2007 Magnus Damm
 * Based on sh_timer.c and arm_timer.c by Paul Brook
 * Copyright (c) 2005-2006 CodeSourcery.
 *
 * This code is licensed under the GPL.
 */

#include "sh_intc.h"
#include "hw.h"
#include "sh.h"

//#define DEBUG_INTC
//#define DEBUG_INTC_SOURCES

#define INTC_A7(x) ((x) & 0x1fffffff)

void sh_intc_toggle_source(struct intc_source *source,
			   int enable_adj, int assert_adj)
{
    int enable_changed = 0;
    int pending_changed = 0;
    int old_pending;

    if ((source->enable_count == source->enable_max) && (enable_adj == -1))
        enable_changed = -1;

    source->enable_count += enable_adj;

    if (source->enable_count == source->enable_max)
        enable_changed = 1;

    source->asserted += assert_adj;

    old_pending = source->pending;
    source->pending = source->asserted &&
      (source->enable_count == source->enable_max);

    if (old_pending != source->pending)
        pending_changed = 1;

    if (pending_changed) {
        if (source->pending) {
            source->parent->pending++;
	    if (source->parent->pending == 1)
                cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	}
	else {
            source->parent->pending--;
	    if (source->parent->pending == 0)
                cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	}
    }

  if (enable_changed || assert_adj || pending_changed) {
#ifdef DEBUG_INTC_SOURCES
            printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
		   source->parent->pending,
		   source->asserted,
		   source->enable_count,
		   source->enable_max,
		   source->vect,
		   source->asserted ? "asserted " :
		   assert_adj ? "deasserted" : "",
		   enable_changed == 1 ? "enabled " :
		   enable_changed == -1 ? "disabled " : "",
		   source->pending ? "pending" : "");
#endif
  }
}

static void sh_intc_set_irq (void *opaque, int n, int level)
{
  struct intc_desc *desc = opaque;
  struct intc_source *source = &(desc->sources[n]);

  if (level && !source->asserted)
    sh_intc_toggle_source(source, 0, 1);
  else if (!level && source->asserted)
    sh_intc_toggle_source(source, 0, -1);
}

int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
{
    unsigned int i;

    /* slow: use a linked lists of pending sources instead */
    /* wrong: take interrupt priority into account (one list per priority) */

    if (imask == 0x0f) {
        return -1; /* FIXME, update code to include priority per source */
    }

    for (i = 0; i < desc->nr_sources; i++) {
        struct intc_source *source = desc->sources + i;

	if (source->pending) {
#ifdef DEBUG_INTC_SOURCES
            printf("sh_intc: (%d) returning interrupt source 0x%x\n",
		   desc->pending, source->vect);
#endif
            return source->vect;
	}
    }

    abort();
}

#define INTC_MODE_NONE       0
#define INTC_MODE_DUAL_SET   1
#define INTC_MODE_DUAL_CLR   2
#define INTC_MODE_ENABLE_REG 3
#define INTC_MODE_MASK_REG   4
#define INTC_MODE_IS_PRIO    8

static unsigned int sh_intc_mode(unsigned long address,
				 unsigned long set_reg, unsigned long clr_reg)
{
    if ((address != INTC_A7(set_reg)) &&
	(address != INTC_A7(clr_reg)))
        return INTC_MODE_NONE;

    if (set_reg && clr_reg) {
        if (address == INTC_A7(set_reg))
            return INTC_MODE_DUAL_SET;
	else
            return INTC_MODE_DUAL_CLR;
    }

    if (set_reg)
        return INTC_MODE_ENABLE_REG;
    else
        return INTC_MODE_MASK_REG;
}

static void sh_intc_locate(struct intc_desc *desc,
			   unsigned long address,
			   unsigned long **datap,
			   intc_enum **enums,
			   unsigned int *first,
			   unsigned int *width,
			   unsigned int *modep)
{
    unsigned int i, mode;

    /* this is slow but works for now */

    if (desc->mask_regs) {
        for (i = 0; i < desc->nr_mask_regs; i++) {
	    struct intc_mask_reg *mr = desc->mask_regs + i;

	    mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
	    if (mode == INTC_MODE_NONE)
                continue;

	    *modep = mode;
	    *datap = &mr->value;
	    *enums = mr->enum_ids;
	    *first = mr->reg_width - 1;
	    *width = 1;
	    return;
	}
    }

    if (desc->prio_regs) {
        for (i = 0; i < desc->nr_prio_regs; i++) {
	    struct intc_prio_reg *pr = desc->prio_regs + i;

	    mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
	    if (mode == INTC_MODE_NONE)
                continue;

	    *modep = mode | INTC_MODE_IS_PRIO;
	    *datap = &pr->value;
	    *enums = pr->enum_ids;
	    *first = (pr->reg_width / pr->field_width) - 1;
	    *width = pr->field_width;
	    return;
	}
    }

    abort();
}

static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
				int enable, int is_group)
{
    struct intc_source *source = desc->sources + id;

    if (!id)
	return;

    if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
#ifdef DEBUG_INTC_SOURCES
        printf("sh_intc: reserved interrupt source %d modified\n", id);
#endif
	return;
    }

    if (source->vect)
        sh_intc_toggle_source(source, enable ? 1 : -1, 0);

#ifdef DEBUG_INTC
    else {
        printf("setting interrupt group %d to %d\n", id, !!enable);
    }
#endif

    if ((is_group || !source->vect) && source->next_enum_id) {
        sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
    }

#ifdef DEBUG_INTC
    if (!source->vect) {
        printf("setting interrupt group %d to %d - done\n", id, !!enable);
    }
#endif
}

static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
{
    struct intc_desc *desc = opaque;
    intc_enum *enum_ids = NULL;
    unsigned int first = 0;
    unsigned int width = 0;
    unsigned int mode = 0;
    unsigned long *valuep;

#ifdef DEBUG_INTC
    printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
#endif

    sh_intc_locate(desc, (unsigned long)offset, &valuep, 
		   &enum_ids, &first, &width, &mode);
    return *valuep;
}

static void sh_intc_write(void *opaque, target_phys_addr_t offset,
			  uint32_t value)
{
    struct intc_desc *desc = opaque;
    intc_enum *enum_ids = NULL;
    unsigned int first = 0;
    unsigned int width = 0;
    unsigned int mode = 0;
    unsigned int k;
    unsigned long *valuep;
    unsigned long mask;

#ifdef DEBUG_INTC
    printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
#endif

    sh_intc_locate(desc, (unsigned long)offset, &valuep, 
		   &enum_ids, &first, &width, &mode);

    switch (mode) {
    case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
    case INTC_MODE_DUAL_SET: value |= *valuep; break;
    case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
    default: abort();
    }

    for (k = 0; k <= first; k++) {
        mask = ((1 << width) - 1) << ((first - k) * width);

	if ((*valuep & mask) == (value & mask))
            continue;
#if 0
	printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n", 
	       k, first, enum_ids[k], (unsigned int)mask);
#endif
        sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
    }

    *valuep = value;

#ifdef DEBUG_INTC
    printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
#endif
}

static CPUReadMemoryFunc * const sh_intc_readfn[] = {
    sh_intc_read,
    sh_intc_read,
    sh_intc_read
};

static CPUWriteMemoryFunc * const sh_intc_writefn[] = {
    sh_intc_write,
    sh_intc_write,
    sh_intc_write
};

struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
{
    if (id)
        return desc->sources + id;

    return NULL;
}

static void sh_intc_register(struct intc_desc *desc, 
			     unsigned long address)
{
    if (address) {
        cpu_register_physical_memory_offset(P4ADDR(address), 4,
                                            desc->iomemtype, INTC_A7(address));
        cpu_register_physical_memory_offset(A7ADDR(address), 4,
                                            desc->iomemtype, INTC_A7(address));
    }
}

static void sh_intc_register_source(struct intc_desc *desc,
				    intc_enum source,
				    struct intc_group *groups,
				    int nr_groups)
{
    unsigned int i, k;
    struct intc_source *s;

    if (desc->mask_regs) {
        for (i = 0; i < desc->nr_mask_regs; i++) {
	    struct intc_mask_reg *mr = desc->mask_regs + i;

	    for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
                if (mr->enum_ids[k] != source)
                    continue;

		s = sh_intc_source(desc, mr->enum_ids[k]);
		if (s)
                    s->enable_max++;
	    }
	}
    }

    if (desc->prio_regs) {
        for (i = 0; i < desc->nr_prio_regs; i++) {
	    struct intc_prio_reg *pr = desc->prio_regs + i;

	    for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
                if (pr->enum_ids[k] != source)
                    continue;

		s = sh_intc_source(desc, pr->enum_ids[k]);
		if (s)
                    s->enable_max++;
	    }
	}
    }

    if (groups) {
        for (i = 0; i < nr_groups; i++) {
	    struct intc_group *gr = groups + i;

	    for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
                if (gr->enum_ids[k] != source)
                    continue;

		s = sh_intc_source(desc, gr->enum_ids[k]);
		if (s)
                    s->enable_max++;
	    }
	}
    }

}

void sh_intc_register_sources(struct intc_desc *desc,
			      struct intc_vect *vectors,
			      int nr_vectors,
			      struct intc_group *groups,
			      int nr_groups)
{
    unsigned int i, k;
    struct intc_source *s;

    for (i = 0; i < nr_vectors; i++) {
	struct intc_vect *vect = vectors + i;

	sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
	s = sh_intc_source(desc, vect->enum_id);
	if (s)
	    s->vect = vect->vect;

#ifdef DEBUG_INTC_SOURCES
	printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
	       vect->enum_id, s->vect, s->enable_count, s->enable_max);
#endif
    }

    if (groups) {
        for (i = 0; i < nr_groups; i++) {
	    struct intc_group *gr = groups + i;

	    s = sh_intc_source(desc, gr->enum_id);
	    s->next_enum_id = gr->enum_ids[0];

	    for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
                if (!gr->enum_ids[k])
                    continue;

		s = sh_intc_source(desc, gr->enum_ids[k - 1]);
		s->next_enum_id = gr->enum_ids[k];
	    }

#ifdef DEBUG_INTC_SOURCES
	    printf("sh_intc: registered group %d (%d/%d)\n",
		   gr->enum_id, s->enable_count, s->enable_max);
#endif
	}
    }
}

int sh_intc_init(struct intc_desc *desc,
		 int nr_sources,
		 struct intc_mask_reg *mask_regs,
		 int nr_mask_regs,
		 struct intc_prio_reg *prio_regs,
		 int nr_prio_regs)
{
    unsigned int i;

    desc->pending = 0;
    desc->nr_sources = nr_sources;
    desc->mask_regs = mask_regs;
    desc->nr_mask_regs = nr_mask_regs;
    desc->prio_regs = prio_regs;
    desc->nr_prio_regs = nr_prio_regs;

    i = sizeof(struct intc_source) * nr_sources;
    desc->sources = qemu_mallocz(i);

    for (i = 0; i < desc->nr_sources; i++) {
        struct intc_source *source = desc->sources + i;

        source->parent = desc;
    }

    desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
 
    desc->iomemtype = cpu_register_io_memory(sh_intc_readfn,
					     sh_intc_writefn, desc,
                                             DEVICE_NATIVE_ENDIAN);
    if (desc->mask_regs) {
        for (i = 0; i < desc->nr_mask_regs; i++) {
	    struct intc_mask_reg *mr = desc->mask_regs + i;

	    sh_intc_register(desc, mr->set_reg);
	    sh_intc_register(desc, mr->clr_reg);
	}
    }

    if (desc->prio_regs) {
        for (i = 0; i < desc->nr_prio_regs; i++) {
	    struct intc_prio_reg *pr = desc->prio_regs + i;

	    sh_intc_register(desc, pr->set_reg);
	    sh_intc_register(desc, pr->clr_reg);
	}
    }

    return 0;
}

/* Assert level <n> IRL interrupt. 
   0:deassert. 1:lowest priority,... 15:highest priority. */
void sh_intc_set_irl(void *opaque, int n, int level)
{
    struct intc_source *s = opaque;
    int i, irl = level ^ 15;
    for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
	if (i == irl)
	    sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
	else
	    if (s->asserted)
	        sh_intc_toggle_source(s, 0, -1);
    }
}
Commit	Line	Data
80f515e6 AZ	1	/*
	2	* SuperH interrupt controller module
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	* Based on sh_timer.c and arm_timer.c by Paul Brook
	6	* Copyright (c) 2005-2006 CodeSourcery.
	7	*
8e31bf38	8	* This code is licensed under the GPL.
80f515e6 AZ	9	*/
80f515e6 AZ	10
80f515e6	11	#include "sh_intc.h"
87ecb68b PB	12	#include "hw.h"
87ecb68b PB	13	#include "sh.h"
80f515e6 AZ	14
80f515e6 AZ	15	//#define DEBUG_INTC
e96e2044	16	//#define DEBUG_INTC_SOURCES
80f515e6 AZ	17
80f515e6 AZ	18	#define INTC_A7(x) ((x) & 0x1fffffff)
80f515e6	19
e96e2044 TS	20	void sh_intc_toggle_source(struct intc_source *source,
	21	int enable_adj, int assert_adj)
	22	{
	23	int enable_changed = 0;
	24	int pending_changed = 0;
	25	int old_pending;
	26
	27	if ((source->enable_count == source->enable_max) && (enable_adj == -1))
	28	enable_changed = -1;
	29
	30	source->enable_count += enable_adj;
	31
	32	if (source->enable_count == source->enable_max)
	33	enable_changed = 1;
	34
	35	source->asserted += assert_adj;
	36
	37	old_pending = source->pending;
	38	source->pending = source->asserted &&
	39	(source->enable_count == source->enable_max);
	40
	41	if (old_pending != source->pending)
	42	pending_changed = 1;
	43
	44	if (pending_changed) {
	45	if (source->pending) {
	46	source->parent->pending++;
	47	if (source->parent->pending == 1)
	48	cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	49	}
	50	else {
	51	source->parent->pending--;
	52	if (source->parent->pending == 0)
	53	cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	54	}
	55	}
	56
	57	if (enable_changed \|\| assert_adj \|\| pending_changed) {
	58	#ifdef DEBUG_INTC_SOURCES
	59	printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
	60	source->parent->pending,
	61	source->asserted,
	62	source->enable_count,
	63	source->enable_max,
	64	source->vect,
	65	source->asserted ? "asserted " :
	66	assert_adj ? "deasserted" : "",
	67	enable_changed == 1 ? "enabled " :
	68	enable_changed == -1 ? "disabled " : "",
	69	source->pending ? "pending" : "");
	70	#endif
	71	}
	72	}
	73
b79e1752	74	static void sh_intc_set_irq (void *opaque, int n, int level)
96e2fc41 AJ	75	{
	76	struct intc_desc *desc = opaque;
	77	struct intc_source *source = &(desc->sources[n]);
	78
4e7ed2d1 AJ	79	if (level && !source->asserted)
	80	sh_intc_toggle_source(source, 0, 1);
	81	else if (!level && source->asserted)
	82	sh_intc_toggle_source(source, 0, -1);
96e2fc41 AJ	83	}
96e2fc41 AJ	84
e96e2044 TS	85	int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
	86	{
	87	unsigned int i;
	88
	89	/* slow: use a linked lists of pending sources instead */
	90	/* wrong: take interrupt priority into account (one list per priority) */
	91
	92	if (imask == 0x0f) {
	93	return -1; /* FIXME, update code to include priority per source */
	94	}
	95
	96	for (i = 0; i < desc->nr_sources; i++) {
	97	struct intc_source *source = desc->sources + i;
	98
	99	if (source->pending) {
	100	#ifdef DEBUG_INTC_SOURCES
	101	printf("sh_intc: (%d) returning interrupt source 0x%x\n",
	102	desc->pending, source->vect);
	103	#endif
	104	return source->vect;
	105	}
	106	}
	107
43dc2a64	108	abort();
e96e2044 TS	109	}
e96e2044 TS	110
80f515e6 AZ	111	#define INTC_MODE_NONE 0
	112	#define INTC_MODE_DUAL_SET 1
	113	#define INTC_MODE_DUAL_CLR 2
	114	#define INTC_MODE_ENABLE_REG 3
	115	#define INTC_MODE_MASK_REG 4
	116	#define INTC_MODE_IS_PRIO 8
	117
	118	static unsigned int sh_intc_mode(unsigned long address,
	119	unsigned long set_reg, unsigned long clr_reg)
	120	{
	121	if ((address != INTC_A7(set_reg)) &&
	122	(address != INTC_A7(clr_reg)))
	123	return INTC_MODE_NONE;
	124
	125	if (set_reg && clr_reg) {
	126	if (address == INTC_A7(set_reg))
	127	return INTC_MODE_DUAL_SET;
	128	else
	129	return INTC_MODE_DUAL_CLR;
	130	}
	131
	132	if (set_reg)
	133	return INTC_MODE_ENABLE_REG;
	134	else
	135	return INTC_MODE_MASK_REG;
	136	}
	137
	138	static void sh_intc_locate(struct intc_desc *desc,
	139	unsigned long address,
	140	unsigned long **datap,
	141	intc_enum **enums,
	142	unsigned int *first,
	143	unsigned int *width,
	144	unsigned int *modep)
	145	{
	146	unsigned int i, mode;
	147
	148	/* this is slow but works for now */
	149
	150	if (desc->mask_regs) {
	151	for (i = 0; i < desc->nr_mask_regs; i++) {
	152	struct intc_mask_reg *mr = desc->mask_regs + i;
	153
	154	mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
	155	if (mode == INTC_MODE_NONE)
	156	continue;
	157
	158	*modep = mode;
	159	*datap = &mr->value;
	160	*enums = mr->enum_ids;
	161	*first = mr->reg_width - 1;
	162	*width = 1;
	163	return;
	164	}
	165	}
	166
	167	if (desc->prio_regs) {
	168	for (i = 0; i < desc->nr_prio_regs; i++) {
	169	struct intc_prio_reg *pr = desc->prio_regs + i;
	170
	171	mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
	172	if (mode == INTC_MODE_NONE)
	173	continue;
	174
175	*modep = mode \| INTC_MODE_IS_PRIO;
176	*datap = &pr->value;
177	*enums = pr->enum_ids;
178	*first = (pr->reg_width / pr->field_width) - 1;
179	*width = pr->field_width;
180	return;
181	}
182	}
183
43dc2a64	184	abort();
80f515e6 AZ	185	}
80f515e6 AZ	186
e96e2044 TS	187	static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
e96e2044 TS	188	int enable, int is_group)
80f515e6 AZ	189	{
80f515e6 AZ	190	struct intc_source *source = desc->sources + id;
80f515e6 AZ	191
	192	if (!id)
	193	return;
	194
	195	if (!source->next_enum_id && (!source->enable_max \|\| !source->vect)) {
e96e2044	196	#ifdef DEBUG_INTC_SOURCES
80f515e6 AZ	197	printf("sh_intc: reserved interrupt source %d modified\n", id);
	198	#endif
	199	return;
	200	}
	201
e96e2044 TS	202	if (source->vect)
e96e2044 TS	203	sh_intc_toggle_source(source, enable ? 1 : -1, 0);
80f515e6	204
80f515e6 AZ	205	#ifdef DEBUG_INTC
	206	else {
	207	printf("setting interrupt group %d to %d\n", id, !!enable);
	208	}
	209	#endif
	210
	211	if ((is_group \|\| !source->vect) && source->next_enum_id) {
e96e2044	212	sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
80f515e6 AZ	213	}
	214
	215	#ifdef DEBUG_INTC
	216	if (!source->vect) {
	217	printf("setting interrupt group %d to %d - done\n", id, !!enable);
	218	}
	219	#endif
	220	}
	221
c227f099	222	static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
80f515e6 AZ	223	{
	224	struct intc_desc *desc = opaque;
	225	intc_enum *enum_ids = NULL;
	226	unsigned int first = 0;
	227	unsigned int width = 0;
	228	unsigned int mode = 0;
	229	unsigned long *valuep;
	230
	231	#ifdef DEBUG_INTC
	232	printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
	233	#endif
	234
	235	sh_intc_locate(desc, (unsigned long)offset, &valuep,
	236	&enum_ids, &first, &width, &mode);
	237	return *valuep;
	238	}
	239
c227f099	240	static void sh_intc_write(void *opaque, target_phys_addr_t offset,
80f515e6 AZ	241	uint32_t value)
	242	{
	243	struct intc_desc *desc = opaque;
	244	intc_enum *enum_ids = NULL;
	245	unsigned int first = 0;
	246	unsigned int width = 0;
	247	unsigned int mode = 0;
	248	unsigned int k;
	249	unsigned long *valuep;
	250	unsigned long mask;
	251
	252	#ifdef DEBUG_INTC
	253	printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
	254	#endif
	255
	256	sh_intc_locate(desc, (unsigned long)offset, &valuep,
	257	&enum_ids, &first, &width, &mode);
	258
	259	switch (mode) {
	260	case INTC_MODE_ENABLE_REG \| INTC_MODE_IS_PRIO: break;
	261	case INTC_MODE_DUAL_SET: value \|= *valuep; break;
	262	case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
43dc2a64	263	default: abort();
80f515e6 AZ	264	}
	265
	266	for (k = 0; k <= first; k++) {
	267	mask = ((1 << width) - 1) << ((first - k) * width);
	268
	269	if ((*valuep & mask) == (value & mask))
	270	continue;
	271	#if 0
	272	printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
	273	k, first, enum_ids[k], (unsigned int)mask);
	274	#endif
e96e2044	275	sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
80f515e6 AZ	276	}
	277
	278	*valuep = value;
	279
	280	#ifdef DEBUG_INTC
	281	printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
	282	#endif
	283	}
	284
d60efc6b	285	static CPUReadMemoryFunc * const sh_intc_readfn[] = {
80f515e6 AZ	286	sh_intc_read,
	287	sh_intc_read,
	288	sh_intc_read
	289	};
	290
d60efc6b	291	static CPUWriteMemoryFunc * const sh_intc_writefn[] = {
80f515e6 AZ	292	sh_intc_write,
	293	sh_intc_write,
	294	sh_intc_write
	295	};
	296
	297	struct intc_source sh_intc_source(struct intc_desc desc, intc_enum id)
	298	{
	299	if (id)
	300	return desc->sources + id;
	301
	302	return NULL;
	303	}
	304
	305	static void sh_intc_register(struct intc_desc *desc,
	306	unsigned long address)
	307	{
5c16736a AZ	308	if (address) {
5c16736a AZ	309	cpu_register_physical_memory_offset(P4ADDR(address), 4,
8da3ff18	310	desc->iomemtype, INTC_A7(address));
5c16736a AZ	311	cpu_register_physical_memory_offset(A7ADDR(address), 4,
	312	desc->iomemtype, INTC_A7(address));
	313	}
80f515e6 AZ	314	}
	315
	316	static void sh_intc_register_source(struct intc_desc *desc,
	317	intc_enum source,
	318	struct intc_group *groups,
	319	int nr_groups)
	320	{
	321	unsigned int i, k;
	322	struct intc_source *s;
	323
	324	if (desc->mask_regs) {
	325	for (i = 0; i < desc->nr_mask_regs; i++) {
	326	struct intc_mask_reg *mr = desc->mask_regs + i;
	327
b1503cda	328	for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
80f515e6 AZ	329	if (mr->enum_ids[k] != source)
	330	continue;
	331
	332	s = sh_intc_source(desc, mr->enum_ids[k]);
	333	if (s)
	334	s->enable_max++;
	335	}
	336	}
	337	}
	338
	339	if (desc->prio_regs) {
	340	for (i = 0; i < desc->nr_prio_regs; i++) {
	341	struct intc_prio_reg *pr = desc->prio_regs + i;
	342
b1503cda	343	for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
80f515e6 AZ	344	if (pr->enum_ids[k] != source)
	345	continue;
	346
	347	s = sh_intc_source(desc, pr->enum_ids[k]);
	348	if (s)
	349	s->enable_max++;
	350	}
	351	}
	352	}
	353
	354	if (groups) {
	355	for (i = 0; i < nr_groups; i++) {
	356	struct intc_group *gr = groups + i;
	357
b1503cda	358	for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
80f515e6 AZ	359	if (gr->enum_ids[k] != source)
	360	continue;
	361
	362	s = sh_intc_source(desc, gr->enum_ids[k]);
	363	if (s)
	364	s->enable_max++;
	365	}
	366	}
	367	}
	368
	369	}
	370
	371	void sh_intc_register_sources(struct intc_desc *desc,
	372	struct intc_vect *vectors,
	373	int nr_vectors,
	374	struct intc_group *groups,
	375	int nr_groups)
	376	{
	377	unsigned int i, k;
	378	struct intc_source *s;
	379
	380	for (i = 0; i < nr_vectors; i++) {
	381	struct intc_vect *vect = vectors + i;
	382
	383	sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
	384	s = sh_intc_source(desc, vect->enum_id);
	385	if (s)
	386	s->vect = vect->vect;
	387
e96e2044	388	#ifdef DEBUG_INTC_SOURCES
80f515e6 AZ	389	printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
	390	vect->enum_id, s->vect, s->enable_count, s->enable_max);
	391	#endif
	392	}
	393
	394	if (groups) {
	395	for (i = 0; i < nr_groups; i++) {
	396	struct intc_group *gr = groups + i;
	397
	398	s = sh_intc_source(desc, gr->enum_id);
	399	s->next_enum_id = gr->enum_ids[0];
	400
b1503cda	401	for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
80f515e6 AZ	402	if (!gr->enum_ids[k])
	403	continue;
	404
	405	s = sh_intc_source(desc, gr->enum_ids[k - 1]);
	406	s->next_enum_id = gr->enum_ids[k];
	407	}
	408
e96e2044	409	#ifdef DEBUG_INTC_SOURCES
80f515e6 AZ	410	printf("sh_intc: registered group %d (%d/%d)\n",
	411	gr->enum_id, s->enable_count, s->enable_max);
	412	#endif
	413	}
	414	}
	415	}
	416
	417	int sh_intc_init(struct intc_desc *desc,
	418	int nr_sources,
	419	struct intc_mask_reg *mask_regs,
	420	int nr_mask_regs,
	421	struct intc_prio_reg *prio_regs,
	422	int nr_prio_regs)
	423	{
	424	unsigned int i;
	425
e96e2044	426	desc->pending = 0;
80f515e6 AZ	427	desc->nr_sources = nr_sources;
	428	desc->mask_regs = mask_regs;
	429	desc->nr_mask_regs = nr_mask_regs;
	430	desc->prio_regs = prio_regs;
	431	desc->nr_prio_regs = nr_prio_regs;
	432
	433	i = sizeof(struct intc_source) * nr_sources;
cc597832	434	desc->sources = qemu_mallocz(i);
80f515e6	435
e96e2044 TS	436	for (i = 0; i < desc->nr_sources; i++) {
	437	struct intc_source *source = desc->sources + i;
	438
	439	source->parent = desc;
	440	}
96e2fc41 AJ	441
96e2fc41 AJ	442	desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
80f515e6	443
1eed09cb	444	desc->iomemtype = cpu_register_io_memory(sh_intc_readfn,
2507c12a AG	445	sh_intc_writefn, desc,
2507c12a AG	446	DEVICE_NATIVE_ENDIAN);
80f515e6 AZ	447	if (desc->mask_regs) {
	448	for (i = 0; i < desc->nr_mask_regs; i++) {
	449	struct intc_mask_reg *mr = desc->mask_regs + i;
	450
	451	sh_intc_register(desc, mr->set_reg);
	452	sh_intc_register(desc, mr->clr_reg);
	453	}
	454	}
	455
	456	if (desc->prio_regs) {
	457	for (i = 0; i < desc->nr_prio_regs; i++) {
	458	struct intc_prio_reg *pr = desc->prio_regs + i;
	459
	460	sh_intc_register(desc, pr->set_reg);
	461	sh_intc_register(desc, pr->clr_reg);
	462	}
	463	}
	464
	465	return 0;
	466	}
c6d86a33 AZ	467
	468	/* Assert level <n> IRL interrupt.
	469	0:deassert. 1:lowest priority,... 15:highest priority. */
	470	void sh_intc_set_irl(void *opaque, int n, int level)
	471	{
	472	struct intc_source *s = opaque;
	473	int i, irl = level ^ 15;
	474	for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
	475	if (i == irl)
	476	sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
	477	else
	478	if (s->asserted)
	479	sh_intc_toggle_source(s, 0, -1);
	480	}
	481	}