[qemu.git] / hw / sh_intc.c

/*
 * SuperH interrupt controller module
 *
 * Copyright (c) 2007 Magnus Damm
 * Based on sh_timer.c and arm_timer.c by Paul Brook
 * Copyright (c) 2005-2006 CodeSourcery.
 *
 * This code is licenced under the GPL.
 */

#include <assert.h>
#include "sh_intc.h"
#include "hw.h"
#include "sh.h"

//#define DEBUG_INTC
//#define DEBUG_INTC_SOURCES

#define INTC_A7(x) ((x) & 0x1fffffff)
#define INTC_ARRAY(x) (sizeof(x) / sizeof(x[0]))

void sh_intc_toggle_source(struct intc_source *source,
			   int enable_adj, int assert_adj)
{
    int enable_changed = 0;
    int pending_changed = 0;
    int old_pending;

    if ((source->enable_count == source->enable_max) && (enable_adj == -1))
        enable_changed = -1;

    source->enable_count += enable_adj;

    if (source->enable_count == source->enable_max)
        enable_changed = 1;

    source->asserted += assert_adj;

    old_pending = source->pending;
    source->pending = source->asserted &&
      (source->enable_count == source->enable_max);

    if (old_pending != source->pending)
        pending_changed = 1;

    if (pending_changed) {
        if (source->pending) {
            source->parent->pending++;
	    if (source->parent->pending == 1)
                cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	}
	else {
            source->parent->pending--;
	    if (source->parent->pending == 0)
                cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	}
    }

  if (enable_changed || assert_adj || pending_changed) {
#ifdef DEBUG_INTC_SOURCES
            printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
		   source->parent->pending,
		   source->asserted,
		   source->enable_count,
		   source->enable_max,
		   source->vect,
		   source->asserted ? "asserted " :
		   assert_adj ? "deasserted" : "",
		   enable_changed == 1 ? "enabled " :
		   enable_changed == -1 ? "disabled " : "",
		   source->pending ? "pending" : "");
#endif
  }
}

void sh_intc_set_irq (void *opaque, int n, int level)
{
  struct intc_desc *desc = opaque;
  struct intc_source *source = &(desc->sources[n]);

  sh_intc_toggle_source(source, 0, level ? 1 : -1);  
}

int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
{
    unsigned int i;

    /* slow: use a linked lists of pending sources instead */
    /* wrong: take interrupt priority into account (one list per priority) */

    if (imask == 0x0f) {
        return -1; /* FIXME, update code to include priority per source */
    }

    for (i = 0; i < desc->nr_sources; i++) {
        struct intc_source *source = desc->sources + i;

	if (source->pending) {
#ifdef DEBUG_INTC_SOURCES
            printf("sh_intc: (%d) returning interrupt source 0x%x\n",
		   desc->pending, source->vect);
#endif
            return source->vect;
	}
    }

    assert(0);
}

#define INTC_MODE_NONE       0
#define INTC_MODE_DUAL_SET   1
#define INTC_MODE_DUAL_CLR   2
#define INTC_MODE_ENABLE_REG 3
#define INTC_MODE_MASK_REG   4
#define INTC_MODE_IS_PRIO    8

static unsigned int sh_intc_mode(unsigned long address,
				 unsigned long set_reg, unsigned long clr_reg)
{
    if ((address != INTC_A7(set_reg)) &&
	(address != INTC_A7(clr_reg)))
        return INTC_MODE_NONE;

    if (set_reg && clr_reg) {
        if (address == INTC_A7(set_reg))
            return INTC_MODE_DUAL_SET;
	else
            return INTC_MODE_DUAL_CLR;
    }

    if (set_reg)
        return INTC_MODE_ENABLE_REG;
    else
        return INTC_MODE_MASK_REG;
}

static void sh_intc_locate(struct intc_desc *desc,
			   unsigned long address,
			   unsigned long **datap,
			   intc_enum **enums,
			   unsigned int *first,
			   unsigned int *width,
			   unsigned int *modep)
{
    unsigned int i, mode;

    /* this is slow but works for now */

    if (desc->mask_regs) {
        for (i = 0; i < desc->nr_mask_regs; i++) {
	    struct intc_mask_reg *mr = desc->mask_regs + i;

	    mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
	    if (mode == INTC_MODE_NONE)
                continue;

	    *modep = mode;
	    *datap = &mr->value;
	    *enums = mr->enum_ids;
	    *first = mr->reg_width - 1;
	    *width = 1;
	    return;
	}
    }

    if (desc->prio_regs) {
        for (i = 0; i < desc->nr_prio_regs; i++) {
	    struct intc_prio_reg *pr = desc->prio_regs + i;

	    mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
	    if (mode == INTC_MODE_NONE)
                continue;

	    *modep = mode | INTC_MODE_IS_PRIO;
	    *datap = &pr->value;
	    *enums = pr->enum_ids;
	    *first = (pr->reg_width / pr->field_width) - 1;
	    *width = pr->field_width;
	    return;
	}
    }

    assert(0);
}

static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
				int enable, int is_group)
{
    struct intc_source *source = desc->sources + id;

    if (!id)
	return;

    if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
#ifdef DEBUG_INTC_SOURCES
        printf("sh_intc: reserved interrupt source %d modified\n", id);
#endif
	return;
    }

    if (source->vect)
        sh_intc_toggle_source(source, enable ? 1 : -1, 0);

#ifdef DEBUG_INTC
    else {
        printf("setting interrupt group %d to %d\n", id, !!enable);
    }
#endif

    if ((is_group || !source->vect) && source->next_enum_id) {
        sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
    }

#ifdef DEBUG_INTC
    if (!source->vect) {
        printf("setting interrupt group %d to %d - done\n", id, !!enable);
    }
#endif
}

static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
{
    struct intc_desc *desc = opaque;
    intc_enum *enum_ids = NULL;
    unsigned int first = 0;
    unsigned int width = 0;
    unsigned int mode = 0;
    unsigned long *valuep;

#ifdef DEBUG_INTC
    printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
#endif

    sh_intc_locate(desc, (unsigned long)offset, &valuep, 
		   &enum_ids, &first, &width, &mode);
    return *valuep;
}

static void sh_intc_write(void *opaque, target_phys_addr_t offset,
			  uint32_t value)
{
    struct intc_desc *desc = opaque;
    intc_enum *enum_ids = NULL;
    unsigned int first = 0;
    unsigned int width = 0;
    unsigned int mode = 0;
    unsigned int k;
    unsigned long *valuep;
    unsigned long mask;

#ifdef DEBUG_INTC
    printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
#endif

    sh_intc_locate(desc, (unsigned long)offset, &valuep, 
		   &enum_ids, &first, &width, &mode);

    switch (mode) {
    case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
    case INTC_MODE_DUAL_SET: value |= *valuep; break;
    case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
    default: assert(0);
    }

    for (k = 0; k <= first; k++) {
        mask = ((1 << width) - 1) << ((first - k) * width);

	if ((*valuep & mask) == (value & mask))
            continue;
#if 0
	printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n", 
	       k, first, enum_ids[k], (unsigned int)mask);
#endif
        sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
    }

    *valuep = value;

#ifdef DEBUG_INTC
    printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
#endif
}

static CPUReadMemoryFunc *sh_intc_readfn[] = {
    sh_intc_read,
    sh_intc_read,
    sh_intc_read
};

static CPUWriteMemoryFunc *sh_intc_writefn[] = {
    sh_intc_write,
    sh_intc_write,
    sh_intc_write
};

struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
{
    if (id)
        return desc->sources + id;

    return NULL;
}

static void sh_intc_register(struct intc_desc *desc, 
			     unsigned long address)
{
    if (address)
        cpu_register_physical_memory(INTC_A7(address), 4, desc->iomemtype);
}

static void sh_intc_register_source(struct intc_desc *desc,
				    intc_enum source,
				    struct intc_group *groups,
				    int nr_groups)
{
    unsigned int i, k;
    struct intc_source *s;

    if (desc->mask_regs) {
        for (i = 0; i < desc->nr_mask_regs; i++) {
	    struct intc_mask_reg *mr = desc->mask_regs + i;

	    for (k = 0; k < INTC_ARRAY(mr->enum_ids); k++) {
                if (mr->enum_ids[k] != source)
                    continue;

		s = sh_intc_source(desc, mr->enum_ids[k]);
		if (s)
                    s->enable_max++;
	    }
	}
    }

    if (desc->prio_regs) {
        for (i = 0; i < desc->nr_prio_regs; i++) {
	    struct intc_prio_reg *pr = desc->prio_regs + i;

	    for (k = 0; k < INTC_ARRAY(pr->enum_ids); k++) {
                if (pr->enum_ids[k] != source)
                    continue;

		s = sh_intc_source(desc, pr->enum_ids[k]);
		if (s)
                    s->enable_max++;
	    }
	}
    }

    if (groups) {
        for (i = 0; i < nr_groups; i++) {
	    struct intc_group *gr = groups + i;

	    for (k = 0; k < INTC_ARRAY(gr->enum_ids); k++) {
                if (gr->enum_ids[k] != source)
                    continue;

		s = sh_intc_source(desc, gr->enum_ids[k]);
		if (s)
                    s->enable_max++;
	    }
	}
    }

}

void sh_intc_register_sources(struct intc_desc *desc,
			      struct intc_vect *vectors,
			      int nr_vectors,
			      struct intc_group *groups,
			      int nr_groups)
{
    unsigned int i, k;
    struct intc_source *s;

    for (i = 0; i < nr_vectors; i++) {
	struct intc_vect *vect = vectors + i;

	sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
	s = sh_intc_source(desc, vect->enum_id);
	if (s)
	    s->vect = vect->vect;

#ifdef DEBUG_INTC_SOURCES
	printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
	       vect->enum_id, s->vect, s->enable_count, s->enable_max);
#endif
    }

    if (groups) {
        for (i = 0; i < nr_groups; i++) {
	    struct intc_group *gr = groups + i;

	    s = sh_intc_source(desc, gr->enum_id);
	    s->next_enum_id = gr->enum_ids[0];

	    for (k = 1; k < INTC_ARRAY(gr->enum_ids); k++) {
                if (!gr->enum_ids[k])
                    continue;

		s = sh_intc_source(desc, gr->enum_ids[k - 1]);
		s->next_enum_id = gr->enum_ids[k];
	    }

#ifdef DEBUG_INTC_SOURCES
	    printf("sh_intc: registered group %d (%d/%d)\n",
		   gr->enum_id, s->enable_count, s->enable_max);
#endif
	}
    }
}

int sh_intc_init(struct intc_desc *desc,
		 int nr_sources,
		 struct intc_mask_reg *mask_regs,
		 int nr_mask_regs,
		 struct intc_prio_reg *prio_regs,
		 int nr_prio_regs)
{
    unsigned int i;

    desc->pending = 0;
    desc->nr_sources = nr_sources;
    desc->mask_regs = mask_regs;
    desc->nr_mask_regs = nr_mask_regs;
    desc->prio_regs = prio_regs;
    desc->nr_prio_regs = nr_prio_regs;

    i = sizeof(struct intc_source) * nr_sources;
    desc->sources = malloc(i);
    if (!desc->sources)
        return -1;

    memset(desc->sources, 0, i);
    for (i = 0; i < desc->nr_sources; i++) {
        struct intc_source *source = desc->sources + i;

        source->parent = desc;
    }

    desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
 
    desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn,
					     sh_intc_writefn, desc);
    if (desc->mask_regs) {
        for (i = 0; i < desc->nr_mask_regs; i++) {
	    struct intc_mask_reg *mr = desc->mask_regs + i;

	    sh_intc_register(desc, mr->set_reg);
	    sh_intc_register(desc, mr->clr_reg);
	}
    }

    if (desc->prio_regs) {
        for (i = 0; i < desc->nr_prio_regs; i++) {
	    struct intc_prio_reg *pr = desc->prio_regs + i;

	    sh_intc_register(desc, pr->set_reg);
	    sh_intc_register(desc, pr->clr_reg);
	}
    }

    return 0;
}
Commit	Line	Data
80f515e6 AZ	1	/*
	2	* SuperH interrupt controller module
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	* Based on sh_timer.c and arm_timer.c by Paul Brook
	6	* Copyright (c) 2005-2006 CodeSourcery.
	7	*
	8	* This code is licenced under the GPL.
	9	*/
	10
	11	#include <assert.h>
	12	#include "sh_intc.h"
87ecb68b PB	13	#include "hw.h"
87ecb68b PB	14	#include "sh.h"
80f515e6 AZ	15
80f515e6 AZ	16	//#define DEBUG_INTC
e96e2044	17	//#define DEBUG_INTC_SOURCES
80f515e6 AZ	18
	19	#define INTC_A7(x) ((x) & 0x1fffffff)
	20	#define INTC_ARRAY(x) (sizeof(x) / sizeof(x[0]))
	21
e96e2044 TS	22	void sh_intc_toggle_source(struct intc_source *source,
	23	int enable_adj, int assert_adj)
	24	{
	25	int enable_changed = 0;
	26	int pending_changed = 0;
	27	int old_pending;
	28
	29	if ((source->enable_count == source->enable_max) && (enable_adj == -1))
	30	enable_changed = -1;
	31
	32	source->enable_count += enable_adj;
	33
	34	if (source->enable_count == source->enable_max)
	35	enable_changed = 1;
	36
	37	source->asserted += assert_adj;
	38
	39	old_pending = source->pending;
	40	source->pending = source->asserted &&
	41	(source->enable_count == source->enable_max);
	42
	43	if (old_pending != source->pending)
	44	pending_changed = 1;
	45
	46	if (pending_changed) {
	47	if (source->pending) {
	48	source->parent->pending++;
	49	if (source->parent->pending == 1)
	50	cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	51	}
	52	else {
	53	source->parent->pending--;
	54	if (source->parent->pending == 0)
	55	cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
	56	}
	57	}
	58
	59	if (enable_changed \|\| assert_adj \|\| pending_changed) {
	60	#ifdef DEBUG_INTC_SOURCES
	61	printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
	62	source->parent->pending,
	63	source->asserted,
	64	source->enable_count,
	65	source->enable_max,
	66	source->vect,
	67	source->asserted ? "asserted " :
	68	assert_adj ? "deasserted" : "",
	69	enable_changed == 1 ? "enabled " :
	70	enable_changed == -1 ? "disabled " : "",
	71	source->pending ? "pending" : "");
	72	#endif
	73	}
	74	}
	75
96e2fc41 AJ	76	void sh_intc_set_irq (void *opaque, int n, int level)
	77	{
	78	struct intc_desc *desc = opaque;
	79	struct intc_source *source = &(desc->sources[n]);
	80
	81	sh_intc_toggle_source(source, 0, level ? 1 : -1);
	82	}
	83
e96e2044 TS	84	int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
	85	{
	86	unsigned int i;
	87
	88	/* slow: use a linked lists of pending sources instead */
	89	/* wrong: take interrupt priority into account (one list per priority) */
	90
	91	if (imask == 0x0f) {
	92	return -1; /* FIXME, update code to include priority per source */
	93	}
	94
	95	for (i = 0; i < desc->nr_sources; i++) {
	96	struct intc_source *source = desc->sources + i;
	97
	98	if (source->pending) {
	99	#ifdef DEBUG_INTC_SOURCES
	100	printf("sh_intc: (%d) returning interrupt source 0x%x\n",
	101	desc->pending, source->vect);
	102	#endif
	103	return source->vect;
	104	}
	105	}
	106
	107	assert(0);
	108	}
	109
80f515e6 AZ	110	#define INTC_MODE_NONE 0
	111	#define INTC_MODE_DUAL_SET 1
	112	#define INTC_MODE_DUAL_CLR 2
	113	#define INTC_MODE_ENABLE_REG 3
	114	#define INTC_MODE_MASK_REG 4
	115	#define INTC_MODE_IS_PRIO 8
	116
	117	static unsigned int sh_intc_mode(unsigned long address,
	118	unsigned long set_reg, unsigned long clr_reg)
	119	{
	120	if ((address != INTC_A7(set_reg)) &&
	121	(address != INTC_A7(clr_reg)))
	122	return INTC_MODE_NONE;
	123
	124	if (set_reg && clr_reg) {
	125	if (address == INTC_A7(set_reg))
	126	return INTC_MODE_DUAL_SET;
	127	else
	128	return INTC_MODE_DUAL_CLR;
	129	}
	130
	131	if (set_reg)
	132	return INTC_MODE_ENABLE_REG;
	133	else
	134	return INTC_MODE_MASK_REG;
	135	}
	136
	137	static void sh_intc_locate(struct intc_desc *desc,
	138	unsigned long address,
	139	unsigned long **datap,
	140	intc_enum **enums,
	141	unsigned int *first,
	142	unsigned int *width,
	143	unsigned int *modep)
	144	{
	145	unsigned int i, mode;
	146
	147	/* this is slow but works for now */
	148
	149	if (desc->mask_regs) {
	150	for (i = 0; i < desc->nr_mask_regs; i++) {
	151	struct intc_mask_reg *mr = desc->mask_regs + i;
	152
	153	mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
	154	if (mode == INTC_MODE_NONE)
	155	continue;
	156
	157	*modep = mode;
	158	*datap = &mr->value;
	159	*enums = mr->enum_ids;
	160	*first = mr->reg_width - 1;
	161	*width = 1;
	162	return;
	163	}
	164	}
	165
	166	if (desc->prio_regs) {
	167	for (i = 0; i < desc->nr_prio_regs; i++) {
	168	struct intc_prio_reg *pr = desc->prio_regs + i;
	169
	170	mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
	171	if (mode == INTC_MODE_NONE)
	172	continue;
	173
174	*modep = mode \| INTC_MODE_IS_PRIO;
175	*datap = &pr->value;
176	*enums = pr->enum_ids;
177	*first = (pr->reg_width / pr->field_width) - 1;
178	*width = pr->field_width;
179	return;
180	}
181	}
182
183	assert(0);
184	}
185
e96e2044 TS	186	static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
e96e2044 TS	187	int enable, int is_group)
80f515e6 AZ	188	{
80f515e6 AZ	189	struct intc_source *source = desc->sources + id;
80f515e6 AZ	190
	191	if (!id)
	192	return;
	193
	194	if (!source->next_enum_id && (!source->enable_max \|\| !source->vect)) {
e96e2044	195	#ifdef DEBUG_INTC_SOURCES
80f515e6 AZ	196	printf("sh_intc: reserved interrupt source %d modified\n", id);
	197	#endif
	198	return;
	199	}
	200
e96e2044 TS	201	if (source->vect)
e96e2044 TS	202	sh_intc_toggle_source(source, enable ? 1 : -1, 0);
80f515e6	203
80f515e6 AZ	204	#ifdef DEBUG_INTC
	205	else {
	206	printf("setting interrupt group %d to %d\n", id, !!enable);
	207	}
	208	#endif
	209
	210	if ((is_group \|\| !source->vect) && source->next_enum_id) {
e96e2044	211	sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
80f515e6 AZ	212	}
	213
	214	#ifdef DEBUG_INTC
	215	if (!source->vect) {
	216	printf("setting interrupt group %d to %d - done\n", id, !!enable);
	217	}
	218	#endif
	219	}
	220
	221	static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
	222	{
	223	struct intc_desc *desc = opaque;
	224	intc_enum *enum_ids = NULL;
	225	unsigned int first = 0;
	226	unsigned int width = 0;
	227	unsigned int mode = 0;
	228	unsigned long *valuep;
	229
	230	#ifdef DEBUG_INTC
	231	printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
	232	#endif
	233
	234	sh_intc_locate(desc, (unsigned long)offset, &valuep,
	235	&enum_ids, &first, &width, &mode);
	236	return *valuep;
	237	}
	238
	239	static void sh_intc_write(void *opaque, target_phys_addr_t offset,
	240	uint32_t value)
	241	{
	242	struct intc_desc *desc = opaque;
	243	intc_enum *enum_ids = NULL;
	244	unsigned int first = 0;
	245	unsigned int width = 0;
	246	unsigned int mode = 0;
	247	unsigned int k;
	248	unsigned long *valuep;
	249	unsigned long mask;
	250
	251	#ifdef DEBUG_INTC
	252	printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
	253	#endif
	254
	255	sh_intc_locate(desc, (unsigned long)offset, &valuep,
	256	&enum_ids, &first, &width, &mode);
	257
	258	switch (mode) {
	259	case INTC_MODE_ENABLE_REG \| INTC_MODE_IS_PRIO: break;
	260	case INTC_MODE_DUAL_SET: value \|= *valuep; break;
	261	case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
	262	default: assert(0);
	263	}
	264
	265	for (k = 0; k <= first; k++) {
	266	mask = ((1 << width) - 1) << ((first - k) * width);
	267
	268	if ((*valuep & mask) == (value & mask))
	269	continue;
	270	#if 0
	271	printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
	272	k, first, enum_ids[k], (unsigned int)mask);
	273	#endif
e96e2044	274	sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
80f515e6 AZ	275	}
	276
	277	*valuep = value;
	278
	279	#ifdef DEBUG_INTC
	280	printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
	281	#endif
	282	}
	283
	284	static CPUReadMemoryFunc *sh_intc_readfn[] = {
	285	sh_intc_read,
	286	sh_intc_read,
	287	sh_intc_read
	288	};
	289
	290	static CPUWriteMemoryFunc *sh_intc_writefn[] = {
	291	sh_intc_write,
	292	sh_intc_write,
	293	sh_intc_write
	294	};
	295
	296	struct intc_source sh_intc_source(struct intc_desc desc, intc_enum id)
	297	{
	298	if (id)
	299	return desc->sources + id;
	300
	301	return NULL;
	302	}
	303
	304	static void sh_intc_register(struct intc_desc *desc,
	305	unsigned long address)
	306	{
	307	if (address)
	308	cpu_register_physical_memory(INTC_A7(address), 4, desc->iomemtype);
	309	}
	310
	311	static void sh_intc_register_source(struct intc_desc *desc,
	312	intc_enum source,
	313	struct intc_group *groups,
	314	int nr_groups)
	315	{
	316	unsigned int i, k;
	317	struct intc_source *s;
	318
	319	if (desc->mask_regs) {
	320	for (i = 0; i < desc->nr_mask_regs; i++) {
	321	struct intc_mask_reg *mr = desc->mask_regs + i;
	322
	323	for (k = 0; k < INTC_ARRAY(mr->enum_ids); k++) {
	324	if (mr->enum_ids[k] != source)
	325	continue;
	326
	327	s = sh_intc_source(desc, mr->enum_ids[k]);
	328	if (s)
	329	s->enable_max++;
	330	}
	331	}
	332	}
	333
	334	if (desc->prio_regs) {
	335	for (i = 0; i < desc->nr_prio_regs; i++) {
	336	struct intc_prio_reg *pr = desc->prio_regs + i;
	337
	338	for (k = 0; k < INTC_ARRAY(pr->enum_ids); k++) {
339	if (pr->enum_ids[k] != source)
340	continue;
341
342	s = sh_intc_source(desc, pr->enum_ids[k]);
343	if (s)
344	s->enable_max++;
345	}
346	}
347	}
348
349	if (groups) {
350	for (i = 0; i < nr_groups; i++) {
351	struct intc_group *gr = groups + i;
352
353	for (k = 0; k < INTC_ARRAY(gr->enum_ids); k++) {
354	if (gr->enum_ids[k] != source)
355	continue;
356
357	s = sh_intc_source(desc, gr->enum_ids[k]);
358	if (s)
359	s->enable_max++;
360	}
361	}
362	}
363
364	}
365
366	void sh_intc_register_sources(struct intc_desc *desc,
367	struct intc_vect *vectors,
368	int nr_vectors,
369	struct intc_group *groups,
370	int nr_groups)
371	{
372	unsigned int i, k;
373	struct intc_source *s;
374
375	for (i = 0; i < nr_vectors; i++) {
376	struct intc_vect *vect = vectors + i;
377
378	sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
379	s = sh_intc_source(desc, vect->enum_id);
380	if (s)
381	s->vect = vect->vect;
382
e96e2044	383	#ifdef DEBUG_INTC_SOURCES
80f515e6 AZ	384	printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
	385	vect->enum_id, s->vect, s->enable_count, s->enable_max);
	386	#endif
	387	}
	388
	389	if (groups) {
	390	for (i = 0; i < nr_groups; i++) {
	391	struct intc_group *gr = groups + i;
	392
	393	s = sh_intc_source(desc, gr->enum_id);
	394	s->next_enum_id = gr->enum_ids[0];
	395
	396	for (k = 1; k < INTC_ARRAY(gr->enum_ids); k++) {
	397	if (!gr->enum_ids[k])
	398	continue;
	399
	400	s = sh_intc_source(desc, gr->enum_ids[k - 1]);
	401	s->next_enum_id = gr->enum_ids[k];
	402	}
	403
e96e2044	404	#ifdef DEBUG_INTC_SOURCES
80f515e6 AZ	405	printf("sh_intc: registered group %d (%d/%d)\n",
	406	gr->enum_id, s->enable_count, s->enable_max);
	407	#endif
	408	}
	409	}
	410	}
	411
	412	int sh_intc_init(struct intc_desc *desc,
	413	int nr_sources,
	414	struct intc_mask_reg *mask_regs,
	415	int nr_mask_regs,
	416	struct intc_prio_reg *prio_regs,
	417	int nr_prio_regs)
	418	{
	419	unsigned int i;
	420
e96e2044	421	desc->pending = 0;
80f515e6 AZ	422	desc->nr_sources = nr_sources;
	423	desc->mask_regs = mask_regs;
	424	desc->nr_mask_regs = nr_mask_regs;
	425	desc->prio_regs = prio_regs;
	426	desc->nr_prio_regs = nr_prio_regs;
	427
	428	i = sizeof(struct intc_source) * nr_sources;
	429	desc->sources = malloc(i);
	430	if (!desc->sources)
	431	return -1;
	432
	433	memset(desc->sources, 0, i);
e96e2044 TS	434	for (i = 0; i < desc->nr_sources; i++) {
	435	struct intc_source *source = desc->sources + i;
	436
	437	source->parent = desc;
	438	}
96e2fc41 AJ	439
96e2fc41 AJ	440	desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
80f515e6 AZ	441
	442	desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn,
	443	sh_intc_writefn, desc);
	444	if (desc->mask_regs) {
	445	for (i = 0; i < desc->nr_mask_regs; i++) {
	446	struct intc_mask_reg *mr = desc->mask_regs + i;
	447
	448	sh_intc_register(desc, mr->set_reg);
	449	sh_intc_register(desc, mr->clr_reg);
	450	}
	451	}
	452
	453	if (desc->prio_regs) {
	454	for (i = 0; i < desc->nr_prio_regs; i++) {
	455	struct intc_prio_reg *pr = desc->prio_regs + i;
	456
	457	sh_intc_register(desc, pr->set_reg);
	458	sh_intc_register(desc, pr->clr_reg);
	459	}
	460	}
	461
	462	return 0;
	463	}