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[qemu.git] / hw / sh_pci.c
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1/*
2 * SuperH on-chip PCIC emulation.
3 *
4 * Copyright (c) 2008 Takashi YOSHII
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
cf154394 24#include "sysbus.h"
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25#include "sh.h"
26#include "pci.h"
b6243d99 27#include "pci_host.h"
1e5459a3 28#include "bswap.h"
1e39101c 29#include "exec-memory.h"
1e5459a3 30
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31typedef struct SHPCIState {
32 SysBusDevice busdev;
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33 PCIBus *bus;
34 PCIDevice *dev;
cf154394 35 qemu_irq irq[4];
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36 MemoryRegion memconfig_p4;
37 MemoryRegion memconfig_a7;
38 MemoryRegion isa;
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39 uint32_t par;
40 uint32_t mbr;
41 uint32_t iobr;
cf154394 42} SHPCIState;
1e5459a3 43
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44static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val,
45 unsigned size)
1e5459a3 46{
cf154394 47 SHPCIState *pcic = p;
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48 switch(addr) {
49 case 0 ... 0xfc:
50 cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
51 break;
52 case 0x1c0:
53 pcic->par = val;
54 break;
55 case 0x1c4:
5ba9e952 56 pcic->mbr = val & 0xff000001;
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57 break;
58 case 0x1c8:
5ba9e952 59 if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
fb57117a 60 memory_region_del_subregion(get_system_memory(), &pcic->isa);
5ba9e952 61 pcic->iobr = val & 0xfffc0001;
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62 memory_region_add_subregion(get_system_memory(),
63 pcic->iobr & 0xfffc0000, &pcic->isa);
5ba9e952 64 }
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65 break;
66 case 0x220:
67 pci_data_write(pcic->bus, pcic->par, val, 4);
68 break;
69 }
70}
71
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72static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr,
73 unsigned size)
1e5459a3 74{
cf154394 75 SHPCIState *pcic = p;
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76 switch(addr) {
77 case 0 ... 0xfc:
78 return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
79 case 0x1c0:
80 return pcic->par;
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81 case 0x1c4:
82 return pcic->mbr;
83 case 0x1c8:
84 return pcic->iobr;
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85 case 0x220:
86 return pci_data_read(pcic->bus, pcic->par, 4);
87 }
88 return 0;
89}
90
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91static const MemoryRegionOps sh_pci_reg_ops = {
92 .read = sh_pci_reg_read,
93 .write = sh_pci_reg_write,
94 .endianness = DEVICE_NATIVE_ENDIAN,
95 .valid = {
96 .min_access_size = 4,
97 .max_access_size = 4,
98 },
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99};
100
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101static int sh_pci_map_irq(PCIDevice *d, int irq_num)
102{
103 return (d->devfn >> 3);
104}
105
106static void sh_pci_set_irq(void *opaque, int irq_num, int level)
107{
108 qemu_irq *pic = opaque;
109
110 qemu_set_irq(pic[irq_num], level);
111}
112
113static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base)
114{
115 SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
116
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117 memory_region_add_subregion(get_system_memory(),
118 P4ADDR(base),
119 &s->memconfig_p4);
120 memory_region_add_subregion(get_system_memory(),
121 A7ADDR(base),
122 &s->memconfig_a7);
cf154394 123 s->iobr = 0xfe240000;
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124 memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa);
125}
126
127static void sh_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
128{
129 SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
130
131 memory_region_del_subregion(get_system_memory(), &s->memconfig_p4);
132 memory_region_del_subregion(get_system_memory(), &s->memconfig_a7);
133 memory_region_del_subregion(get_system_memory(), &s->isa);
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134}
135
136static int sh_pci_init_device(SysBusDevice *dev)
137{
138 SHPCIState *s;
139 int i;
140
141 s = FROM_SYSBUS(SHPCIState, dev);
142 for (i = 0; i < 4; i++) {
143 sysbus_init_irq(dev, &s->irq[i]);
144 }
145 s->bus = pci_register_bus(&s->busdev.qdev, "pci",
146 sh_pci_set_irq, sh_pci_map_irq,
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147 s->irq,
148 get_system_memory(),
149 get_system_io(),
1e39101c 150 PCI_DEVFN(0, 0), 4);
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151 memory_region_init_io(&s->memconfig_p4, &sh_pci_reg_ops, s,
152 "sh_pci", 0x224);
73c92f9a 153 memory_region_init_alias(&s->memconfig_a7, "sh_pci.2", &s->memconfig_p4,
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154 0, 0x224);
155 isa_mmio_setup(&s->isa, 0x40000);
156 sysbus_init_mmio_cb2(dev, sh_pci_map, sh_pci_unmap);
157 sysbus_init_mmio_region(dev, &s->memconfig_a7);
158 sysbus_init_mmio_region(dev, &s->isa);
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159 s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host");
160 return 0;
161}
162
163static int sh_pci_host_init(PCIDevice *d)
164{
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165 pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
166 pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
167 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
168 return 0;
169}
170
171static PCIDeviceInfo sh_pci_host_info = {
172 .qdev.name = "sh_pci_host",
173 .qdev.size = sizeof(PCIDevice),
174 .init = sh_pci_host_init,
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175 .vendor_id = PCI_VENDOR_ID_HITACHI,
176 .device_id = PCI_DEVICE_ID_HITACHI_SH7751R,
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177};
178
179static void sh_pci_register_devices(void)
1e5459a3 180{
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181 sysbus_register_dev("sh_pci", sizeof(SHPCIState),
182 sh_pci_init_device);
183 pci_qdev_register(&sh_pci_host_info);
1e5459a3 184}
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185
186device_init(sh_pci_register_devices)