[qemu.git] / hw / sh_serial.c

/*
 * QEMU SCI/SCIF serial port emulation
 *
 * Copyright (c) 2007 Magnus Damm
 *
 * Based on serial.c - QEMU 16450 UART emulation
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sh.h"
#include "qemu-char.h"
#include <assert.h>

//#define DEBUG_SERIAL

#define SH_SERIAL_FLAG_TEND (1 << 0)
#define SH_SERIAL_FLAG_TDE  (1 << 1)
#define SH_SERIAL_FLAG_RDF  (1 << 2)
#define SH_SERIAL_FLAG_BRK  (1 << 3)
#define SH_SERIAL_FLAG_DR   (1 << 4)

#define SH_RX_FIFO_LENGTH (16)

typedef struct {
    uint8_t smr;
    uint8_t brr;
    uint8_t scr;
    uint8_t dr; /* ftdr / tdr */
    uint8_t sr; /* fsr / ssr */
    uint16_t fcr;
    uint8_t sptr;

    uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
    uint8_t rx_cnt;
    uint8_t rx_tail;
    uint8_t rx_head;

    int freq;
    int feat;
    int flags;
    int rtrg;

    CharDriverState *chr;

    qemu_irq eri;
    qemu_irq rxi;
    qemu_irq txi;
    qemu_irq tei;
    qemu_irq bri;
} sh_serial_state;

static void sh_serial_clear_fifo(sh_serial_state * s)
{
    memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
    s->rx_cnt = 0;
    s->rx_head = 0;
    s->rx_tail = 0;
}

static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
{
    sh_serial_state *s = opaque;
    unsigned char ch;

#ifdef DEBUG_SERIAL
    printf("sh_serial: write offs=0x%02x val=0x%02x\n",
	   offs, val);
#endif
    switch(offs) {
    case 0x00: /* SMR */
        s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
        return;
    case 0x04: /* BRR */
        s->brr = val;
	return;
    case 0x08: /* SCR */
        /* TODO : For SH7751, SCIF mask should be 0xfb. */
        s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
        if (!(val & (1 << 5)))
            s->flags |= SH_SERIAL_FLAG_TEND;
        if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
	    qemu_set_irq(s->txi, val & (1 << 7));
        }
        if (!(val & (1 << 6))) {
	    qemu_set_irq(s->rxi, 0);
        }
        return;
    case 0x0c: /* FTDR / TDR */
        if (s->chr) {
            ch = val;
            qemu_chr_write(s->chr, &ch, 1);
	}
	s->dr = val;
	s->flags &= ~SH_SERIAL_FLAG_TDE;
        return;
#if 0
    case 0x14: /* FRDR / RDR */
        ret = 0;
        break;
#endif
    }
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x10: /* FSR */
            if (!(val & (1 << 6)))
                s->flags &= ~SH_SERIAL_FLAG_TEND;
            if (!(val & (1 << 5)))
                s->flags &= ~SH_SERIAL_FLAG_TDE;
            if (!(val & (1 << 4)))
                s->flags &= ~SH_SERIAL_FLAG_BRK;
            if (!(val & (1 << 1)))
                s->flags &= ~SH_SERIAL_FLAG_RDF;
            if (!(val & (1 << 0)))
                s->flags &= ~SH_SERIAL_FLAG_DR;

            if (!(val & (1 << 1)) || !(val & (1 << 0))) {
                if (s->rxi) {
                    qemu_set_irq(s->rxi, 0);
                }
            }
            return;
        case 0x18: /* FCR */
            s->fcr = val;
            switch ((val >> 6) & 3) {
            case 0:
                s->rtrg = 1;
                break;
            case 1:
                s->rtrg = 4;
                break;
            case 2:
                s->rtrg = 8;
                break;
            case 3:
                s->rtrg = 14;
                break;
            }
            if (val & (1 << 1)) {
                sh_serial_clear_fifo(s);
                s->sr &= ~(1 << 1);
            }

            return;
        case 0x20: /* SPTR */
            s->sptr = val & 0xf3;
            return;
        case 0x24: /* LSR */
            return;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
#endif
        case 0x1c:
            s->sptr = val & 0x8f;
            return;
        }
    }

    fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
    assert(0);
}

static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
{
    sh_serial_state *s = opaque;
    uint32_t ret = ~0;

#if 0
    switch(offs) {
    case 0x00:
        ret = s->smr;
        break;
    case 0x04:
        ret = s->brr;
	break;
    case 0x08:
        ret = s->scr;
        break;
    case 0x14:
        ret = 0;
        break;
    }
#endif
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x00: /* SMR */
            ret = s->smr;
            break;
        case 0x08: /* SCR */
            ret = s->scr;
            break;
        case 0x10: /* FSR */
            ret = 0;
            if (s->flags & SH_SERIAL_FLAG_TEND)
                ret |= (1 << 6);
            if (s->flags & SH_SERIAL_FLAG_TDE)
                ret |= (1 << 5);
            if (s->flags & SH_SERIAL_FLAG_BRK)
                ret |= (1 << 4);
            if (s->flags & SH_SERIAL_FLAG_RDF)
                ret |= (1 << 1);
            if (s->flags & SH_SERIAL_FLAG_DR)
                ret |= (1 << 0);

            if (s->scr & (1 << 5))
                s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;

            break;
        case 0x14:
            if (s->rx_cnt > 0) {
                ret = s->rx_fifo[s->rx_tail++];
                s->rx_cnt--;
                if (s->rx_tail == SH_RX_FIFO_LENGTH)
                    s->rx_tail = 0;
                if (s->rx_cnt < s->rtrg)
                    s->flags &= ~SH_SERIAL_FLAG_RDF;
            }
            break;
#if 0
        case 0x18:
            ret = s->fcr;
            break;
#endif
        case 0x1c:
            ret = s->rx_cnt;
            break;
        case 0x20:
            ret = s->sptr;
            break;
        case 0x24:
            ret = 0;
            break;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
        case 0x14:
            ret = s->rx_fifo[0];
            break;
#endif
        case 0x1c:
            ret = s->sptr;
            break;
        }
    }
#ifdef DEBUG_SERIAL
    printf("sh_serial: read offs=0x%02x val=0x%x\n",
	   offs, ret);
#endif

    if (ret & ~((1 << 16) - 1)) {
        fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
	assert(0);
    }

    return ret;
}

static int sh_serial_can_receive(sh_serial_state *s)
{
    return s->scr & (1 << 4);
}

static void sh_serial_receive_byte(sh_serial_state *s, int ch)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
            s->rx_fifo[s->rx_head++] = ch;
            if (s->rx_head == SH_RX_FIFO_LENGTH)
                s->rx_head = 0;
            s->rx_cnt++;
            if (s->rx_cnt >= s->rtrg) {
                s->flags |= SH_SERIAL_FLAG_RDF;
                if (s->scr & (1 << 6) && s->rxi) {
                    qemu_set_irq(s->rxi, 1);
                }
            }
        }
    } else {
        s->rx_fifo[0] = ch;
    }
}

static void sh_serial_receive_break(sh_serial_state *s)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF)
        s->sr |= (1 << 4);
}

static int sh_serial_can_receive1(void *opaque)
{
    sh_serial_state *s = opaque;
    return sh_serial_can_receive(s);
}

static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    sh_serial_state *s = opaque;
    sh_serial_receive_byte(s, buf[0]);
}

static void sh_serial_event(void *opaque, int event)
{
    sh_serial_state *s = opaque;
    if (event == CHR_EVENT_BREAK)
        sh_serial_receive_break(s);
}

static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
{
    sh_serial_state *s = opaque;
    return sh_serial_ioport_read(s, addr);
}

static void sh_serial_write (void *opaque,
                             target_phys_addr_t addr, uint32_t value)
{
    sh_serial_state *s = opaque;
    sh_serial_ioport_write(s, addr, value);
}

static CPUReadMemoryFunc *sh_serial_readfn[] = {
    &sh_serial_read,
    &sh_serial_read,
    &sh_serial_read,
};

static CPUWriteMemoryFunc *sh_serial_writefn[] = {
    &sh_serial_write,
    &sh_serial_write,
    &sh_serial_write,
};

void sh_serial_init (target_phys_addr_t base, int feat,
		     uint32_t freq, CharDriverState *chr,
		     qemu_irq eri_source,
		     qemu_irq rxi_source,
		     qemu_irq txi_source,
		     qemu_irq tei_source,
		     qemu_irq bri_source)
{
    sh_serial_state *s;
    int s_io_memory;

    s = qemu_mallocz(sizeof(sh_serial_state));

    s->feat = feat;
    s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
    s->rtrg = 1;

    s->smr = 0;
    s->brr = 0xff;
    s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
    s->sptr = 0;

    if (feat & SH_SERIAL_FEAT_SCIF) {
        s->fcr = 0;
    }
    else {
        s->dr = 0xff;
    }

    sh_serial_clear_fifo(s);

    s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
					 sh_serial_writefn, s);
    cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
    cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);

    s->chr = chr;

    if (chr)
        qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
			      sh_serial_event, s);

    s->eri = eri_source;
    s->rxi = rxi_source;
    s->txi = txi_source;
    s->tei = tei_source;
    s->bri = bri_source;
}
Commit	Line	Data
2f062c72 TS	1	/*
	2	* QEMU SCI/SCIF serial port emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	*
	6	* Based on serial.c - QEMU 16450 UART emulation
	7	* Copyright (c) 2003-2004 Fabrice Bellard
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*/
87ecb68b PB	27	#include "hw.h"
	28	#include "sh.h"
	29	#include "qemu-char.h"
2f062c72 TS	30	#include <assert.h>
	31
	32	//#define DEBUG_SERIAL
	33
	34	#define SH_SERIAL_FLAG_TEND (1 << 0)
	35	#define SH_SERIAL_FLAG_TDE (1 << 1)
	36	#define SH_SERIAL_FLAG_RDF (1 << 2)
	37	#define SH_SERIAL_FLAG_BRK (1 << 3)
	38	#define SH_SERIAL_FLAG_DR (1 << 4)
	39
63242a00 AJ	40	#define SH_RX_FIFO_LENGTH (16)
63242a00 AJ	41
2f062c72 TS	42	typedef struct {
	43	uint8_t smr;
	44	uint8_t brr;
	45	uint8_t scr;
	46	uint8_t dr; /* ftdr / tdr */
	47	uint8_t sr; /* fsr / ssr */
	48	uint16_t fcr;
	49	uint8_t sptr;
	50
63242a00	51	uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
2f062c72	52	uint8_t rx_cnt;
63242a00 AJ	53	uint8_t rx_tail;
63242a00 AJ	54	uint8_t rx_head;
2f062c72	55
2f062c72 TS	56	int freq;
	57	int feat;
	58	int flags;
63242a00	59	int rtrg;
2f062c72 TS	60
2f062c72 TS	61	CharDriverState *chr;
bf5b7423	62
4e7ed2d1 AJ	63	qemu_irq eri;
	64	qemu_irq rxi;
	65	qemu_irq txi;
	66	qemu_irq tei;
	67	qemu_irq bri;
2f062c72 TS	68	} sh_serial_state;
2f062c72 TS	69
63242a00 AJ	70	static void sh_serial_clear_fifo(sh_serial_state * s)
	71	{
	72	memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
	73	s->rx_cnt = 0;
	74	s->rx_head = 0;
	75	s->rx_tail = 0;
	76	}
	77
2f062c72 TS	78	static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
	79	{
	80	sh_serial_state *s = opaque;
	81	unsigned char ch;
	82
	83	#ifdef DEBUG_SERIAL
8da3ff18 PB	84	printf("sh_serial: write offs=0x%02x val=0x%02x\n",
8da3ff18 PB	85	offs, val);
2f062c72 TS	86	#endif
	87	switch(offs) {
	88	case 0x00: /* SMR */
	89	s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
	90	return;
	91	case 0x04: /* BRR */
	92	s->brr = val;
	93	return;
	94	case 0x08: /* SCR */
63242a00	95	/* TODO : For SH7751, SCIF mask should be 0xfb. */
bf5b7423	96	s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
2f062c72 TS	97	if (!(val & (1 << 5)))
2f062c72 TS	98	s->flags \|= SH_SERIAL_FLAG_TEND;
bf5b7423	99	if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
4e7ed2d1	100	qemu_set_irq(s->txi, val & (1 << 7));
bf5b7423	101	}
4e7ed2d1 AJ	102	if (!(val & (1 << 6))) {
4e7ed2d1 AJ	103	qemu_set_irq(s->rxi, 0);
63242a00	104	}
2f062c72 TS	105	return;
	106	case 0x0c: /* FTDR / TDR */
	107	if (s->chr) {
	108	ch = val;
	109	qemu_chr_write(s->chr, &ch, 1);
	110	}
	111	s->dr = val;
	112	s->flags &= ~SH_SERIAL_FLAG_TDE;
	113	return;
	114	#if 0
	115	case 0x14: /* FRDR / RDR */
	116	ret = 0;
	117	break;
	118	#endif
	119	}
	120	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	121	switch(offs) {
	122	case 0x10: /* FSR */
	123	if (!(val & (1 << 6)))
	124	s->flags &= ~SH_SERIAL_FLAG_TEND;
	125	if (!(val & (1 << 5)))
	126	s->flags &= ~SH_SERIAL_FLAG_TDE;
	127	if (!(val & (1 << 4)))
	128	s->flags &= ~SH_SERIAL_FLAG_BRK;
	129	if (!(val & (1 << 1)))
	130	s->flags &= ~SH_SERIAL_FLAG_RDF;
	131	if (!(val & (1 << 0)))
	132	s->flags &= ~SH_SERIAL_FLAG_DR;
63242a00 AJ	133
63242a00 AJ	134	if (!(val & (1 << 1)) \|\| !(val & (1 << 0))) {
4e7ed2d1 AJ	135	if (s->rxi) {
4e7ed2d1 AJ	136	qemu_set_irq(s->rxi, 0);
63242a00 AJ	137	}
63242a00 AJ	138	}
2f062c72 TS	139	return;
	140	case 0x18: /* FCR */
	141	s->fcr = val;
63242a00 AJ	142	switch ((val >> 6) & 3) {
	143	case 0:
	144	s->rtrg = 1;
	145	break;
	146	case 1:
	147	s->rtrg = 4;
	148	break;
	149	case 2:
	150	s->rtrg = 8;
	151	break;
	152	case 3:
	153	s->rtrg = 14;
	154	break;
	155	}
	156	if (val & (1 << 1)) {
	157	sh_serial_clear_fifo(s);
	158	s->sr &= ~(1 << 1);
	159	}
	160
2f062c72 TS	161	return;
2f062c72 TS	162	case 0x20: /* SPTR */
63242a00	163	s->sptr = val & 0xf3;
2f062c72 TS	164	return;
	165	case 0x24: /* LSR */
	166	return;
	167	}
	168	}
	169	else {
2f062c72	170	switch(offs) {
d1f193b0	171	#if 0
2f062c72 TS	172	case 0x0c:
	173	ret = s->dr;
	174	break;
	175	case 0x10:
	176	ret = 0;
	177	break;
d1f193b0	178	#endif
2f062c72	179	case 0x1c:
d1f193b0 AJ	180	s->sptr = val & 0x8f;
d1f193b0 AJ	181	return;
2f062c72	182	}
2f062c72 TS	183	}
	184
	185	fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
	186	assert(0);
	187	}
	188
	189	static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
	190	{
	191	sh_serial_state *s = opaque;
	192	uint32_t ret = ~0;
	193
	194	#if 0
	195	switch(offs) {
	196	case 0x00:
	197	ret = s->smr;
	198	break;
	199	case 0x04:
	200	ret = s->brr;
	201	break;
	202	case 0x08:
	203	ret = s->scr;
	204	break;
	205	case 0x14:
	206	ret = 0;
	207	break;
	208	}
	209	#endif
	210	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	211	switch(offs) {
bf5b7423 AJ	212	case 0x00: /* SMR */
	213	ret = s->smr;
	214	break;
	215	case 0x08: /* SCR */
	216	ret = s->scr;
	217	break;
2f062c72 TS	218	case 0x10: /* FSR */
	219	ret = 0;
	220	if (s->flags & SH_SERIAL_FLAG_TEND)
	221	ret \|= (1 << 6);
	222	if (s->flags & SH_SERIAL_FLAG_TDE)
	223	ret \|= (1 << 5);
	224	if (s->flags & SH_SERIAL_FLAG_BRK)
	225	ret \|= (1 << 4);
	226	if (s->flags & SH_SERIAL_FLAG_RDF)
	227	ret \|= (1 << 1);
	228	if (s->flags & SH_SERIAL_FLAG_DR)
	229	ret \|= (1 << 0);
	230
63242a00	231	if (s->scr & (1 << 5))
2f062c72 TS	232	s->flags \|= SH_SERIAL_FLAG_TDE \| SH_SERIAL_FLAG_TEND;
2f062c72 TS	233
63242a00 AJ	234	break;
	235	case 0x14:
	236	if (s->rx_cnt > 0) {
	237	ret = s->rx_fifo[s->rx_tail++];
	238	s->rx_cnt--;
	239	if (s->rx_tail == SH_RX_FIFO_LENGTH)
	240	s->rx_tail = 0;
	241	if (s->rx_cnt < s->rtrg)
	242	s->flags &= ~SH_SERIAL_FLAG_RDF;
	243	}
2f062c72 TS	244	break;
	245	#if 0
	246	case 0x18:
	247	ret = s->fcr;
	248	break;
	249	#endif
	250	case 0x1c:
	251	ret = s->rx_cnt;
	252	break;
	253	case 0x20:
	254	ret = s->sptr;
	255	break;
	256	case 0x24:
	257	ret = 0;
	258	break;
	259	}
	260	}
	261	else {
2f062c72	262	switch(offs) {
d1f193b0	263	#if 0
2f062c72 TS	264	case 0x0c:
	265	ret = s->dr;
	266	break;
	267	case 0x10:
	268	ret = 0;
	269	break;
63242a00 AJ	270	case 0x14:
	271	ret = s->rx_fifo[0];
	272	break;
d1f193b0	273	#endif
2f062c72 TS	274	case 0x1c:
	275	ret = s->sptr;
	276	break;
	277	}
2f062c72 TS	278	}
2f062c72 TS	279	#ifdef DEBUG_SERIAL
8da3ff18 PB	280	printf("sh_serial: read offs=0x%02x val=0x%x\n",
8da3ff18 PB	281	offs, ret);
2f062c72 TS	282	#endif
	283
	284	if (ret & ~((1 << 16) - 1)) {
	285	fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
	286	assert(0);
	287	}
	288
	289	return ret;
	290	}
	291
	292	static int sh_serial_can_receive(sh_serial_state *s)
	293	{
63242a00	294	return s->scr & (1 << 4);
2f062c72 TS	295	}
	296
	297	static void sh_serial_receive_byte(sh_serial_state *s, int ch)
	298	{
63242a00 AJ	299	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	300	if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
	301	s->rx_fifo[s->rx_head++] = ch;
	302	if (s->rx_head == SH_RX_FIFO_LENGTH)
	303	s->rx_head = 0;
	304	s->rx_cnt++;
	305	if (s->rx_cnt >= s->rtrg) {
	306	s->flags \|= SH_SERIAL_FLAG_RDF;
	307	if (s->scr & (1 << 6) && s->rxi) {
4e7ed2d1	308	qemu_set_irq(s->rxi, 1);
63242a00 AJ	309	}
	310	}
	311	}
	312	} else {
	313	s->rx_fifo[0] = ch;
	314	}
2f062c72 TS	315	}
	316
	317	static void sh_serial_receive_break(sh_serial_state *s)
	318	{
63242a00 AJ	319	if (s->feat & SH_SERIAL_FEAT_SCIF)
63242a00 AJ	320	s->sr \|= (1 << 4);
2f062c72 TS	321	}
	322
	323	static int sh_serial_can_receive1(void *opaque)
	324	{
	325	sh_serial_state *s = opaque;
	326	return sh_serial_can_receive(s);
	327	}
	328
	329	static void sh_serial_receive1(void opaque, const uint8_t buf, int size)
	330	{
	331	sh_serial_state *s = opaque;
	332	sh_serial_receive_byte(s, buf[0]);
	333	}
	334
	335	static void sh_serial_event(void *opaque, int event)
	336	{
	337	sh_serial_state *s = opaque;
	338	if (event == CHR_EVENT_BREAK)
	339	sh_serial_receive_break(s);
	340	}
	341
9596ebb7	342	static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
2f062c72 TS	343	{
2f062c72 TS	344	sh_serial_state *s = opaque;
8da3ff18	345	return sh_serial_ioport_read(s, addr);
2f062c72 TS	346	}
2f062c72 TS	347
9596ebb7 PB	348	static void sh_serial_write (void *opaque,
9596ebb7 PB	349	target_phys_addr_t addr, uint32_t value)
2f062c72 TS	350	{
2f062c72 TS	351	sh_serial_state *s = opaque;
8da3ff18	352	sh_serial_ioport_write(s, addr, value);
2f062c72 TS	353	}
	354
	355	static CPUReadMemoryFunc *sh_serial_readfn[] = {
	356	&sh_serial_read,
	357	&sh_serial_read,
	358	&sh_serial_read,
	359	};
	360
	361	static CPUWriteMemoryFunc *sh_serial_writefn[] = {
	362	&sh_serial_write,
	363	&sh_serial_write,
	364	&sh_serial_write,
	365	};
	366
	367	void sh_serial_init (target_phys_addr_t base, int feat,
bf5b7423	368	uint32_t freq, CharDriverState *chr,
4e7ed2d1 AJ	369	qemu_irq eri_source,
	370	qemu_irq rxi_source,
	371	qemu_irq txi_source,
	372	qemu_irq tei_source,
	373	qemu_irq bri_source)
2f062c72 TS	374	{
	375	sh_serial_state *s;
	376	int s_io_memory;
	377
	378	s = qemu_mallocz(sizeof(sh_serial_state));
2f062c72	379
2f062c72 TS	380	s->feat = feat;
2f062c72 TS	381	s->flags = SH_SERIAL_FLAG_TEND \| SH_SERIAL_FLAG_TDE;
63242a00	382	s->rtrg = 1;
2f062c72 TS	383
	384	s->smr = 0;
	385	s->brr = 0xff;
b7d35e65	386	s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
2f062c72 TS	387	s->sptr = 0;
	388
	389	if (feat & SH_SERIAL_FEAT_SCIF) {
	390	s->fcr = 0;
	391	}
	392	else {
	393	s->dr = 0xff;
	394	}
	395
63242a00	396	sh_serial_clear_fifo(s);
2f062c72 TS	397
	398	s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
	399	sh_serial_writefn, s);
5c16736a AZ	400	cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
5c16736a AZ	401	cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
2f062c72 TS	402
	403	s->chr = chr;
	404
	405	if (chr)
	406	qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
	407	sh_serial_event, s);
bf5b7423 AJ	408
	409	s->eri = eri_source;
	410	s->rxi = rxi_source;
	411	s->txi = txi_source;
	412	s->tei = tei_source;
	413	s->bri = bri_source;
2f062c72	414	}