[qemu.git] / hw / sh_serial.c

/*
 * QEMU SCI/SCIF serial port emulation
 *
 * Copyright (c) 2007 Magnus Damm
 *
 * Based on serial.c - QEMU 16450 UART emulation
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sh.h"
#include "qemu-char.h"

//#define DEBUG_SERIAL

#define SH_SERIAL_FLAG_TEND (1 << 0)
#define SH_SERIAL_FLAG_TDE  (1 << 1)
#define SH_SERIAL_FLAG_RDF  (1 << 2)
#define SH_SERIAL_FLAG_BRK  (1 << 3)
#define SH_SERIAL_FLAG_DR   (1 << 4)

#define SH_RX_FIFO_LENGTH (16)

typedef struct {
    uint8_t smr;
    uint8_t brr;
    uint8_t scr;
    uint8_t dr; /* ftdr / tdr */
    uint8_t sr; /* fsr / ssr */
    uint16_t fcr;
    uint8_t sptr;

    uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
    uint8_t rx_cnt;
    uint8_t rx_tail;
    uint8_t rx_head;

    int freq;
    int feat;
    int flags;
    int rtrg;

    CharDriverState *chr;

    qemu_irq eri;
    qemu_irq rxi;
    qemu_irq txi;
    qemu_irq tei;
    qemu_irq bri;
} sh_serial_state;

static void sh_serial_clear_fifo(sh_serial_state * s)
{
    memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
    s->rx_cnt = 0;
    s->rx_head = 0;
    s->rx_tail = 0;
}

static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
{
    sh_serial_state *s = opaque;
    unsigned char ch;

#ifdef DEBUG_SERIAL
    printf("sh_serial: write offs=0x%02x val=0x%02x\n",
	   offs, val);
#endif
    switch(offs) {
    case 0x00: /* SMR */
        s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
        return;
    case 0x04: /* BRR */
        s->brr = val;
	return;
    case 0x08: /* SCR */
        /* TODO : For SH7751, SCIF mask should be 0xfb. */
        s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
        if (!(val & (1 << 5)))
            s->flags |= SH_SERIAL_FLAG_TEND;
        if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
	    qemu_set_irq(s->txi, val & (1 << 7));
        }
        if (!(val & (1 << 6))) {
	    qemu_set_irq(s->rxi, 0);
        }
        return;
    case 0x0c: /* FTDR / TDR */
        if (s->chr) {
            ch = val;
            qemu_chr_write(s->chr, &ch, 1);
	}
	s->dr = val;
	s->flags &= ~SH_SERIAL_FLAG_TDE;
        return;
#if 0
    case 0x14: /* FRDR / RDR */
        ret = 0;
        break;
#endif
    }
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x10: /* FSR */
            if (!(val & (1 << 6)))
                s->flags &= ~SH_SERIAL_FLAG_TEND;
            if (!(val & (1 << 5)))
                s->flags &= ~SH_SERIAL_FLAG_TDE;
            if (!(val & (1 << 4)))
                s->flags &= ~SH_SERIAL_FLAG_BRK;
            if (!(val & (1 << 1)))
                s->flags &= ~SH_SERIAL_FLAG_RDF;
            if (!(val & (1 << 0)))
                s->flags &= ~SH_SERIAL_FLAG_DR;

            if (!(val & (1 << 1)) || !(val & (1 << 0))) {
                if (s->rxi) {
                    qemu_set_irq(s->rxi, 0);
                }
            }
            return;
        case 0x18: /* FCR */
            s->fcr = val;
            switch ((val >> 6) & 3) {
            case 0:
                s->rtrg = 1;
                break;
            case 1:
                s->rtrg = 4;
                break;
            case 2:
                s->rtrg = 8;
                break;
            case 3:
                s->rtrg = 14;
                break;
            }
            if (val & (1 << 1)) {
                sh_serial_clear_fifo(s);
                s->sr &= ~(1 << 1);
            }

            return;
        case 0x20: /* SPTR */
            s->sptr = val & 0xf3;
            return;
        case 0x24: /* LSR */
            return;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
#endif
        case 0x1c:
            s->sptr = val & 0x8f;
            return;
        }
    }

    fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
    abort();
}

static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
{
    sh_serial_state *s = opaque;
    uint32_t ret = ~0;

#if 0
    switch(offs) {
    case 0x00:
        ret = s->smr;
        break;
    case 0x04:
        ret = s->brr;
	break;
    case 0x08:
        ret = s->scr;
        break;
    case 0x14:
        ret = 0;
        break;
    }
#endif
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x00: /* SMR */
            ret = s->smr;
            break;
        case 0x08: /* SCR */
            ret = s->scr;
            break;
        case 0x10: /* FSR */
            ret = 0;
            if (s->flags & SH_SERIAL_FLAG_TEND)
                ret |= (1 << 6);
            if (s->flags & SH_SERIAL_FLAG_TDE)
                ret |= (1 << 5);
            if (s->flags & SH_SERIAL_FLAG_BRK)
                ret |= (1 << 4);
            if (s->flags & SH_SERIAL_FLAG_RDF)
                ret |= (1 << 1);
            if (s->flags & SH_SERIAL_FLAG_DR)
                ret |= (1 << 0);

            if (s->scr & (1 << 5))
                s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;

            break;
        case 0x14:
            if (s->rx_cnt > 0) {
                ret = s->rx_fifo[s->rx_tail++];
                s->rx_cnt--;
                if (s->rx_tail == SH_RX_FIFO_LENGTH)
                    s->rx_tail = 0;
                if (s->rx_cnt < s->rtrg)
                    s->flags &= ~SH_SERIAL_FLAG_RDF;
            }
            break;
#if 0
        case 0x18:
            ret = s->fcr;
            break;
#endif
        case 0x1c:
            ret = s->rx_cnt;
            break;
        case 0x20:
            ret = s->sptr;
            break;
        case 0x24:
            ret = 0;
            break;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
        case 0x14:
            ret = s->rx_fifo[0];
            break;
#endif
        case 0x1c:
            ret = s->sptr;
            break;
        }
    }
#ifdef DEBUG_SERIAL
    printf("sh_serial: read offs=0x%02x val=0x%x\n",
	   offs, ret);
#endif

    if (ret & ~((1 << 16) - 1)) {
        fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
        abort();
    }

    return ret;
}

static int sh_serial_can_receive(sh_serial_state *s)
{
    return s->scr & (1 << 4);
}

static void sh_serial_receive_byte(sh_serial_state *s, int ch)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
            s->rx_fifo[s->rx_head++] = ch;
            if (s->rx_head == SH_RX_FIFO_LENGTH)
                s->rx_head = 0;
            s->rx_cnt++;
            if (s->rx_cnt >= s->rtrg) {
                s->flags |= SH_SERIAL_FLAG_RDF;
                if (s->scr & (1 << 6) && s->rxi) {
                    qemu_set_irq(s->rxi, 1);
                }
            }
        }
    } else {
        s->rx_fifo[0] = ch;
    }
}

static void sh_serial_receive_break(sh_serial_state *s)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF)
        s->sr |= (1 << 4);
}

static int sh_serial_can_receive1(void *opaque)
{
    sh_serial_state *s = opaque;
    return sh_serial_can_receive(s);
}

static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    sh_serial_state *s = opaque;
    sh_serial_receive_byte(s, buf[0]);
}

static void sh_serial_event(void *opaque, int event)
{
    sh_serial_state *s = opaque;
    if (event == CHR_EVENT_BREAK)
        sh_serial_receive_break(s);
}

static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
{
    sh_serial_state *s = opaque;
    return sh_serial_ioport_read(s, addr);
}

static void sh_serial_write (void *opaque,
                             target_phys_addr_t addr, uint32_t value)
{
    sh_serial_state *s = opaque;
    sh_serial_ioport_write(s, addr, value);
}

static CPUReadMemoryFunc * const sh_serial_readfn[] = {
    &sh_serial_read,
    &sh_serial_read,
    &sh_serial_read,
};

static CPUWriteMemoryFunc * const sh_serial_writefn[] = {
    &sh_serial_write,
    &sh_serial_write,
    &sh_serial_write,
};

void sh_serial_init (target_phys_addr_t base, int feat,
		     uint32_t freq, CharDriverState *chr,
		     qemu_irq eri_source,
		     qemu_irq rxi_source,
		     qemu_irq txi_source,
		     qemu_irq tei_source,
		     qemu_irq bri_source)
{
    sh_serial_state *s;
    int s_io_memory;

    s = qemu_mallocz(sizeof(sh_serial_state));

    s->feat = feat;
    s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
    s->rtrg = 1;

    s->smr = 0;
    s->brr = 0xff;
    s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
    s->sptr = 0;

    if (feat & SH_SERIAL_FEAT_SCIF) {
        s->fcr = 0;
    }
    else {
        s->dr = 0xff;
    }

    sh_serial_clear_fifo(s);

    s_io_memory = cpu_register_io_memory(sh_serial_readfn,
					 sh_serial_writefn, s);
    cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
    cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);

    s->chr = chr;

    if (chr)
        qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
			      sh_serial_event, s);

    s->eri = eri_source;
    s->rxi = rxi_source;
    s->txi = txi_source;
    s->tei = tei_source;
    s->bri = bri_source;
}
Commit	Line	Data
2f062c72 TS	1	/*
	2	* QEMU SCI/SCIF serial port emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	*
	6	* Based on serial.c - QEMU 16450 UART emulation
	7	* Copyright (c) 2003-2004 Fabrice Bellard
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*/
87ecb68b PB	27	#include "hw.h"
	28	#include "sh.h"
	29	#include "qemu-char.h"
2f062c72 TS	30
	31	//#define DEBUG_SERIAL
	32
	33	#define SH_SERIAL_FLAG_TEND (1 << 0)
	34	#define SH_SERIAL_FLAG_TDE (1 << 1)
	35	#define SH_SERIAL_FLAG_RDF (1 << 2)
	36	#define SH_SERIAL_FLAG_BRK (1 << 3)
	37	#define SH_SERIAL_FLAG_DR (1 << 4)
	38
63242a00 AJ	39	#define SH_RX_FIFO_LENGTH (16)
63242a00 AJ	40
2f062c72 TS	41	typedef struct {
	42	uint8_t smr;
	43	uint8_t brr;
	44	uint8_t scr;
	45	uint8_t dr; /* ftdr / tdr */
	46	uint8_t sr; /* fsr / ssr */
	47	uint16_t fcr;
	48	uint8_t sptr;
	49
63242a00	50	uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
2f062c72	51	uint8_t rx_cnt;
63242a00 AJ	52	uint8_t rx_tail;
63242a00 AJ	53	uint8_t rx_head;
2f062c72	54
2f062c72 TS	55	int freq;
	56	int feat;
	57	int flags;
63242a00	58	int rtrg;
2f062c72 TS	59
2f062c72 TS	60	CharDriverState *chr;
bf5b7423	61
4e7ed2d1 AJ	62	qemu_irq eri;
	63	qemu_irq rxi;
	64	qemu_irq txi;
	65	qemu_irq tei;
	66	qemu_irq bri;
2f062c72 TS	67	} sh_serial_state;
2f062c72 TS	68
63242a00 AJ	69	static void sh_serial_clear_fifo(sh_serial_state * s)
	70	{
	71	memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
	72	s->rx_cnt = 0;
	73	s->rx_head = 0;
	74	s->rx_tail = 0;
	75	}
	76
2f062c72 TS	77	static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
	78	{
	79	sh_serial_state *s = opaque;
	80	unsigned char ch;
	81
	82	#ifdef DEBUG_SERIAL
8da3ff18 PB	83	printf("sh_serial: write offs=0x%02x val=0x%02x\n",
8da3ff18 PB	84	offs, val);
2f062c72 TS	85	#endif
	86	switch(offs) {
	87	case 0x00: /* SMR */
	88	s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
	89	return;
	90	case 0x04: /* BRR */
	91	s->brr = val;
	92	return;
	93	case 0x08: /* SCR */
63242a00	94	/* TODO : For SH7751, SCIF mask should be 0xfb. */
bf5b7423	95	s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
2f062c72 TS	96	if (!(val & (1 << 5)))
2f062c72 TS	97	s->flags \|= SH_SERIAL_FLAG_TEND;
bf5b7423	98	if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
4e7ed2d1	99	qemu_set_irq(s->txi, val & (1 << 7));
bf5b7423	100	}
4e7ed2d1 AJ	101	if (!(val & (1 << 6))) {
4e7ed2d1 AJ	102	qemu_set_irq(s->rxi, 0);
63242a00	103	}
2f062c72 TS	104	return;
	105	case 0x0c: /* FTDR / TDR */
	106	if (s->chr) {
	107	ch = val;
	108	qemu_chr_write(s->chr, &ch, 1);
	109	}
	110	s->dr = val;
	111	s->flags &= ~SH_SERIAL_FLAG_TDE;
	112	return;
	113	#if 0
	114	case 0x14: /* FRDR / RDR */
	115	ret = 0;
	116	break;
	117	#endif
	118	}
	119	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	120	switch(offs) {
	121	case 0x10: /* FSR */
	122	if (!(val & (1 << 6)))
	123	s->flags &= ~SH_SERIAL_FLAG_TEND;
	124	if (!(val & (1 << 5)))
	125	s->flags &= ~SH_SERIAL_FLAG_TDE;
	126	if (!(val & (1 << 4)))
	127	s->flags &= ~SH_SERIAL_FLAG_BRK;
	128	if (!(val & (1 << 1)))
	129	s->flags &= ~SH_SERIAL_FLAG_RDF;
	130	if (!(val & (1 << 0)))
	131	s->flags &= ~SH_SERIAL_FLAG_DR;
63242a00 AJ	132
63242a00 AJ	133	if (!(val & (1 << 1)) \|\| !(val & (1 << 0))) {
4e7ed2d1 AJ	134	if (s->rxi) {
4e7ed2d1 AJ	135	qemu_set_irq(s->rxi, 0);
63242a00 AJ	136	}
63242a00 AJ	137	}
2f062c72 TS	138	return;
	139	case 0x18: /* FCR */
	140	s->fcr = val;
63242a00 AJ	141	switch ((val >> 6) & 3) {
	142	case 0:
	143	s->rtrg = 1;
	144	break;
	145	case 1:
	146	s->rtrg = 4;
	147	break;
	148	case 2:
	149	s->rtrg = 8;
	150	break;
	151	case 3:
	152	s->rtrg = 14;
	153	break;
	154	}
	155	if (val & (1 << 1)) {
	156	sh_serial_clear_fifo(s);
	157	s->sr &= ~(1 << 1);
	158	}
	159
2f062c72 TS	160	return;
2f062c72 TS	161	case 0x20: /* SPTR */
63242a00	162	s->sptr = val & 0xf3;
2f062c72 TS	163	return;
	164	case 0x24: /* LSR */
	165	return;
	166	}
	167	}
	168	else {
2f062c72	169	switch(offs) {
d1f193b0	170	#if 0
2f062c72 TS	171	case 0x0c:
	172	ret = s->dr;
	173	break;
	174	case 0x10:
	175	ret = 0;
	176	break;
d1f193b0	177	#endif
2f062c72	178	case 0x1c:
d1f193b0 AJ	179	s->sptr = val & 0x8f;
d1f193b0 AJ	180	return;
2f062c72	181	}
2f062c72 TS	182	}
	183
	184	fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
43dc2a64	185	abort();
2f062c72 TS	186	}
	187
	188	static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
	189	{
	190	sh_serial_state *s = opaque;
	191	uint32_t ret = ~0;
	192
	193	#if 0
	194	switch(offs) {
	195	case 0x00:
	196	ret = s->smr;
	197	break;
	198	case 0x04:
	199	ret = s->brr;
	200	break;
	201	case 0x08:
	202	ret = s->scr;
	203	break;
	204	case 0x14:
	205	ret = 0;
	206	break;
	207	}
	208	#endif
	209	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	210	switch(offs) {
bf5b7423 AJ	211	case 0x00: /* SMR */
	212	ret = s->smr;
	213	break;
	214	case 0x08: /* SCR */
	215	ret = s->scr;
	216	break;
2f062c72 TS	217	case 0x10: /* FSR */
	218	ret = 0;
	219	if (s->flags & SH_SERIAL_FLAG_TEND)
	220	ret \|= (1 << 6);
	221	if (s->flags & SH_SERIAL_FLAG_TDE)
	222	ret \|= (1 << 5);
	223	if (s->flags & SH_SERIAL_FLAG_BRK)
	224	ret \|= (1 << 4);
	225	if (s->flags & SH_SERIAL_FLAG_RDF)
	226	ret \|= (1 << 1);
	227	if (s->flags & SH_SERIAL_FLAG_DR)
	228	ret \|= (1 << 0);
	229
63242a00	230	if (s->scr & (1 << 5))
2f062c72 TS	231	s->flags \|= SH_SERIAL_FLAG_TDE \| SH_SERIAL_FLAG_TEND;
2f062c72 TS	232
63242a00 AJ	233	break;
	234	case 0x14:
	235	if (s->rx_cnt > 0) {
	236	ret = s->rx_fifo[s->rx_tail++];
	237	s->rx_cnt--;
	238	if (s->rx_tail == SH_RX_FIFO_LENGTH)
	239	s->rx_tail = 0;
	240	if (s->rx_cnt < s->rtrg)
	241	s->flags &= ~SH_SERIAL_FLAG_RDF;
	242	}
2f062c72 TS	243	break;
	244	#if 0
	245	case 0x18:
	246	ret = s->fcr;
	247	break;
	248	#endif
	249	case 0x1c:
	250	ret = s->rx_cnt;
	251	break;
	252	case 0x20:
	253	ret = s->sptr;
	254	break;
	255	case 0x24:
	256	ret = 0;
	257	break;
	258	}
	259	}
	260	else {
2f062c72	261	switch(offs) {
d1f193b0	262	#if 0
2f062c72 TS	263	case 0x0c:
	264	ret = s->dr;
	265	break;
	266	case 0x10:
	267	ret = 0;
	268	break;
63242a00 AJ	269	case 0x14:
	270	ret = s->rx_fifo[0];
	271	break;
d1f193b0	272	#endif
2f062c72 TS	273	case 0x1c:
	274	ret = s->sptr;
	275	break;
	276	}
2f062c72 TS	277	}
2f062c72 TS	278	#ifdef DEBUG_SERIAL
8da3ff18 PB	279	printf("sh_serial: read offs=0x%02x val=0x%x\n",
8da3ff18 PB	280	offs, ret);
2f062c72 TS	281	#endif
	282
	283	if (ret & ~((1 << 16) - 1)) {
	284	fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
43dc2a64	285	abort();
2f062c72 TS	286	}
	287
	288	return ret;
	289	}
	290
	291	static int sh_serial_can_receive(sh_serial_state *s)
	292	{
63242a00	293	return s->scr & (1 << 4);
2f062c72 TS	294	}
	295
	296	static void sh_serial_receive_byte(sh_serial_state *s, int ch)
	297	{
63242a00 AJ	298	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	299	if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
	300	s->rx_fifo[s->rx_head++] = ch;
	301	if (s->rx_head == SH_RX_FIFO_LENGTH)
	302	s->rx_head = 0;
	303	s->rx_cnt++;
	304	if (s->rx_cnt >= s->rtrg) {
	305	s->flags \|= SH_SERIAL_FLAG_RDF;
	306	if (s->scr & (1 << 6) && s->rxi) {
4e7ed2d1	307	qemu_set_irq(s->rxi, 1);
63242a00 AJ	308	}
	309	}
	310	}
	311	} else {
	312	s->rx_fifo[0] = ch;
	313	}
2f062c72 TS	314	}
	315
	316	static void sh_serial_receive_break(sh_serial_state *s)
	317	{
63242a00 AJ	318	if (s->feat & SH_SERIAL_FEAT_SCIF)
63242a00 AJ	319	s->sr \|= (1 << 4);
2f062c72 TS	320	}
	321
	322	static int sh_serial_can_receive1(void *opaque)
	323	{
	324	sh_serial_state *s = opaque;
	325	return sh_serial_can_receive(s);
	326	}
	327
	328	static void sh_serial_receive1(void opaque, const uint8_t buf, int size)
	329	{
	330	sh_serial_state *s = opaque;
	331	sh_serial_receive_byte(s, buf[0]);
	332	}
	333
	334	static void sh_serial_event(void *opaque, int event)
	335	{
	336	sh_serial_state *s = opaque;
	337	if (event == CHR_EVENT_BREAK)
	338	sh_serial_receive_break(s);
	339	}
	340
c227f099	341	static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
2f062c72 TS	342	{
2f062c72 TS	343	sh_serial_state *s = opaque;
8da3ff18	344	return sh_serial_ioport_read(s, addr);
2f062c72 TS	345	}
2f062c72 TS	346
9596ebb7	347	static void sh_serial_write (void *opaque,
c227f099	348	target_phys_addr_t addr, uint32_t value)
2f062c72 TS	349	{
2f062c72 TS	350	sh_serial_state *s = opaque;
8da3ff18	351	sh_serial_ioport_write(s, addr, value);
2f062c72 TS	352	}
2f062c72 TS	353
d60efc6b	354	static CPUReadMemoryFunc * const sh_serial_readfn[] = {
2f062c72 TS	355	&sh_serial_read,
	356	&sh_serial_read,
	357	&sh_serial_read,
	358	};
	359
d60efc6b	360	static CPUWriteMemoryFunc * const sh_serial_writefn[] = {
2f062c72 TS	361	&sh_serial_write,
	362	&sh_serial_write,
	363	&sh_serial_write,
	364	};
	365
c227f099	366	void sh_serial_init (target_phys_addr_t base, int feat,
bf5b7423	367	uint32_t freq, CharDriverState *chr,
4e7ed2d1 AJ	368	qemu_irq eri_source,
	369	qemu_irq rxi_source,
	370	qemu_irq txi_source,
	371	qemu_irq tei_source,
	372	qemu_irq bri_source)
2f062c72 TS	373	{
	374	sh_serial_state *s;
	375	int s_io_memory;
	376
	377	s = qemu_mallocz(sizeof(sh_serial_state));
2f062c72	378
2f062c72 TS	379	s->feat = feat;
2f062c72 TS	380	s->flags = SH_SERIAL_FLAG_TEND \| SH_SERIAL_FLAG_TDE;
63242a00	381	s->rtrg = 1;
2f062c72 TS	382
	383	s->smr = 0;
	384	s->brr = 0xff;
b7d35e65	385	s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
2f062c72 TS	386	s->sptr = 0;
	387
	388	if (feat & SH_SERIAL_FEAT_SCIF) {
	389	s->fcr = 0;
	390	}
	391	else {
	392	s->dr = 0xff;
	393	}
	394
63242a00	395	sh_serial_clear_fifo(s);
2f062c72	396
1eed09cb	397	s_io_memory = cpu_register_io_memory(sh_serial_readfn,
2f062c72	398	sh_serial_writefn, s);
5c16736a AZ	399	cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
5c16736a AZ	400	cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
2f062c72 TS	401
	402	s->chr = chr;
	403
	404	if (chr)
	405	qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
	406	sh_serial_event, s);
bf5b7423 AJ	407
	408	s->eri = eri_source;
	409	s->rxi = rxi_source;
	410	s->txi = txi_source;
	411	s->tei = tei_source;
	412	s->bri = bri_source;
2f062c72	413	}