[qemu.git] / hw / sh_timer.c

/*
 * SuperH Timer modules.
 *
 * Copyright (c) 2007 Magnus Damm
 * Based on arm_timer.c by Paul Brook
 * Copyright (c) 2005-2006 CodeSourcery.
 *
 * This code is licenced under the GPL.
 */

#include "vl.h"

//#define DEBUG_TIMER

#define TIMER_TCR_TPSC          (7 << 0)
#define TIMER_TCR_CKEG          (3 << 3)
#define TIMER_TCR_UNIE          (1 << 5)
#define TIMER_TCR_ICPE          (3 << 6)
#define TIMER_TCR_UNF           (1 << 8)
#define TIMER_TCR_ICPF          (1 << 9)
#define TIMER_TCR_RESERVED      (0x3f << 10)

#define TIMER_FEAT_CAPT   (1 << 0)
#define TIMER_FEAT_EXTCLK (1 << 1)

typedef struct {
    ptimer_state *timer;
    uint32_t tcnt;
    uint32_t tcor;
    uint32_t tcr;
    uint32_t tcpr;
    int freq;
    int int_level;
    int feat;
    int enabled;
    qemu_irq irq;
} sh_timer_state;

/* Check all active timers, and schedule the next timer interrupt. */

static void sh_timer_update(sh_timer_state *s)
{
#if 0 /* not yet */
    /* Update interrupts.  */
    if (s->int_level && (s->tcr & TIMER_TCR_UNIE)) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
#endif
}

uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
{
    sh_timer_state *s = (sh_timer_state *)opaque;

    switch (offset >> 2) {
    case 0:
        return s->tcor;
    case 1:
        return ptimer_get_count(s->timer);
    case 2:
        return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
    case 3:
        if (s->feat & TIMER_FEAT_CAPT)
            return s->tcpr;
    default:
        cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
                   (int)offset);
        return 0;
    }
}

static void sh_timer_write(void *opaque, target_phys_addr_t offset,
                            uint32_t value)
{
    sh_timer_state *s = (sh_timer_state *)opaque;
    int freq;

    switch (offset >> 2) {
    case 0:
        s->tcor = value;
        ptimer_set_limit(s->timer, s->tcor, 0);
        break;
    case 1:
        s->tcnt = value;
        ptimer_set_count(s->timer, s->tcnt);
        break;
    case 2:
        if (s->enabled) {
            /* Pause the timer if it is running.  This may cause some
               inaccuracy dure to rounding, but avoids a whole lot of other
               messyness.  */
            ptimer_stop(s->timer);
        }
        freq = s->freq;
        /* ??? Need to recalculate expiry time after changing divisor.  */
        switch (value & TIMER_TCR_TPSC) {
        case 0: freq >>= 2; break;
        case 1: freq >>= 4; break;
        case 2: freq >>= 6; break;
        case 3: freq >>= 8; break;
        case 4: freq >>= 10; break;
	case 6:
	case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
	default: cpu_abort (cpu_single_env,
			   "sh_timer_write: Reserved TPSC value\n"); break;
        }
        switch ((value & TIMER_TCR_CKEG) >> 3) {
	case 0: break;
        case 1:
        case 2:
        case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
	default: cpu_abort (cpu_single_env,
			   "sh_timer_write: Reserved CKEG value\n"); break;
        }
        switch ((value & TIMER_TCR_ICPE) >> 6) {
	case 0: break;
        case 2:
        case 3: if (s->feat & TIMER_FEAT_CAPT) break;
	default: cpu_abort (cpu_single_env,
			   "sh_timer_write: Reserved ICPE value\n"); break;
        }
	if ((value & TIMER_TCR_UNF) == 0)
            s->int_level = 0;

	value &= ~TIMER_TCR_UNF;

	if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
            cpu_abort (cpu_single_env,
		       "sh_timer_write: Reserved ICPF value\n");

	value &= ~TIMER_TCR_ICPF; /* capture not supported */

	if (value & TIMER_TCR_RESERVED)
            cpu_abort (cpu_single_env,
		       "sh_timer_write: Reserved TCR bits set\n");
        s->tcr = value;
        ptimer_set_limit(s->timer, s->tcor, 0);
        ptimer_set_freq(s->timer, freq);
        if (s->enabled) {
            /* Restart the timer if still enabled.  */
            ptimer_run(s->timer, 0);
        }
        break;
    case 3:
        if (s->feat & TIMER_FEAT_CAPT) {
            s->tcpr = value;
	    break;
	}
    default:
        cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
                   (int)offset);
    }
    sh_timer_update(s);
}

static void sh_timer_start_stop(void *opaque, int enable)
{
    sh_timer_state *s = (sh_timer_state *)opaque;

#ifdef DEBUG_TIMER
    printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
#endif

    if (s->enabled && !enable) {
        ptimer_stop(s->timer);
    }
    if (!s->enabled && enable) {
        ptimer_run(s->timer, 0);
    }
    s->enabled = !!enable;

#ifdef DEBUG_TIMER
    printf("sh_timer_start_stop done %d\n", s->enabled);
#endif
}

static void sh_timer_tick(void *opaque)
{
    sh_timer_state *s = (sh_timer_state *)opaque;
    s->int_level = s->enabled;
    sh_timer_update(s);
}

static void *sh_timer_init(uint32_t freq, int feat)
{
    sh_timer_state *s;
    QEMUBH *bh;

    s = (sh_timer_state *)qemu_mallocz(sizeof(sh_timer_state));
    s->freq = freq;
    s->feat = feat;
    s->tcor = 0xffffffff;
    s->tcnt = 0xffffffff;
    s->tcpr = 0xdeadbeef;
    s->tcor = 0;
    s->enabled = 0;

    bh = qemu_bh_new(sh_timer_tick, s);
    s->timer = ptimer_init(bh);
    /* ??? Save/restore.  */
    return s;
}

typedef struct {
    void *timer[3];
    int level[3];
    uint32_t tocr;
    uint32_t tstr;
    target_phys_addr_t base;
    int feat;
} tmu012_state;

static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
{
    tmu012_state *s = (tmu012_state *)opaque;

#ifdef DEBUG_TIMER
    printf("tmu012_read 0x%lx\n", (unsigned long) offset);
#endif
    offset -= s->base;

    if (offset >= 0x20) {
        if (!(s->feat & TMU012_FEAT_3CHAN))
	    cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
		       (int)offset);
        return sh_timer_read(s->timer[2], offset - 0x20);
    }

    if (offset >= 0x14)
        return sh_timer_read(s->timer[1], offset - 0x14);

    if (offset >= 0x08)
        return sh_timer_read(s->timer[0], offset - 0x08);

    if (offset == 4)
        return s->tstr;

    if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
        return s->tocr;

    cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
	       (int)offset);
    return 0;
}

static void tmu012_write(void *opaque, target_phys_addr_t offset,
                        uint32_t value)
{
    tmu012_state *s = (tmu012_state *)opaque;

#ifdef DEBUG_TIMER
    printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
#endif
    offset -= s->base;

    if (offset >= 0x20) {
        if (!(s->feat & TMU012_FEAT_3CHAN))
	    cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
		       (int)offset);
        sh_timer_write(s->timer[2], offset - 0x20, value);
	return;
    }

    if (offset >= 0x14) {
        sh_timer_write(s->timer[1], offset - 0x14, value);
	return;
    }

    if (offset >= 0x08) {
        sh_timer_write(s->timer[0], offset - 0x08, value);
	return;
    }

    if (offset == 4) {
        sh_timer_start_stop(s->timer[0], value & (1 << 0));
        sh_timer_start_stop(s->timer[1], value & (1 << 1));
        if (s->feat & TMU012_FEAT_3CHAN)
            sh_timer_start_stop(s->timer[2], value & (1 << 2));
	else
            if (value & (1 << 2))
                cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n");

	s->tstr = value;
	return;
    }

    if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
        s->tocr = value & (1 << 0);
    }
}

static CPUReadMemoryFunc *tmu012_readfn[] = {
    tmu012_read,
    tmu012_read,
    tmu012_read
};

static CPUWriteMemoryFunc *tmu012_writefn[] = {
    tmu012_write,
    tmu012_write,
    tmu012_write
};

void tmu012_init(uint32_t base, int feat, uint32_t freq)
{
    int iomemtype;
    tmu012_state *s;
    int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;

    s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
    s->base = base;
    s->feat = feat;
    s->timer[0] = sh_timer_init(freq, timer_feat);
    s->timer[1] = sh_timer_init(freq, timer_feat);
    if (feat & TMU012_FEAT_3CHAN)
        s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT);
    iomemtype = cpu_register_io_memory(0, tmu012_readfn,
                                       tmu012_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    /* ??? Save/restore.  */
}
Commit	Line	Data
cd1a3f68 TS	1	/*
	2	* SuperH Timer modules.
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	* Based on arm_timer.c by Paul Brook
	6	* Copyright (c) 2005-2006 CodeSourcery.
	7	*
	8	* This code is licenced under the GPL.
	9	*/
	10
	11	#include "vl.h"
	12
	13	//#define DEBUG_TIMER
	14
	15	#define TIMER_TCR_TPSC (7 << 0)
	16	#define TIMER_TCR_CKEG (3 << 3)
	17	#define TIMER_TCR_UNIE (1 << 5)
	18	#define TIMER_TCR_ICPE (3 << 6)
	19	#define TIMER_TCR_UNF (1 << 8)
	20	#define TIMER_TCR_ICPF (1 << 9)
	21	#define TIMER_TCR_RESERVED (0x3f << 10)
	22
	23	#define TIMER_FEAT_CAPT (1 << 0)
	24	#define TIMER_FEAT_EXTCLK (1 << 1)
	25
	26	typedef struct {
	27	ptimer_state *timer;
	28	uint32_t tcnt;
	29	uint32_t tcor;
	30	uint32_t tcr;
	31	uint32_t tcpr;
	32	int freq;
	33	int int_level;
	34	int feat;
	35	int enabled;
	36	qemu_irq irq;
	37	} sh_timer_state;
	38
	39	/* Check all active timers, and schedule the next timer interrupt. */
	40
	41	static void sh_timer_update(sh_timer_state *s)
	42	{
	43	#if 0 /* not yet */
	44	/* Update interrupts. */
	45	if (s->int_level && (s->tcr & TIMER_TCR_UNIE)) {
	46	qemu_irq_raise(s->irq);
	47	} else {
	48	qemu_irq_lower(s->irq);
	49	}
	50	#endif
	51	}
	52
	53	uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
	54	{
	55	sh_timer_state s = (sh_timer_state )opaque;
	56
	57	switch (offset >> 2) {
	58	case 0:
	59	return s->tcor;
	60	case 1:
	61	return ptimer_get_count(s->timer);
	62	case 2:
	63	return s->tcr \| (s->int_level ? TIMER_TCR_UNF : 0);
	64	case 3:
65	if (s->feat & TIMER_FEAT_CAPT)
66	return s->tcpr;
67	default:
68	cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
69	(int)offset);
70	return 0;
71	}
72	}
73
74	static void sh_timer_write(void *opaque, target_phys_addr_t offset,
75	uint32_t value)
76	{
77	sh_timer_state s = (sh_timer_state )opaque;
78	int freq;
79
80	switch (offset >> 2) {
81	case 0:
82	s->tcor = value;
83	ptimer_set_limit(s->timer, s->tcor, 0);
84	break;
85	case 1:
86	s->tcnt = value;
87	ptimer_set_count(s->timer, s->tcnt);
88	break;
89	case 2:
90	if (s->enabled) {
91	/* Pause the timer if it is running. This may cause some
92	inaccuracy dure to rounding, but avoids a whole lot of other
93	messyness. */
94	ptimer_stop(s->timer);
95	}
96	freq = s->freq;
97	/* ??? Need to recalculate expiry time after changing divisor. */
98	switch (value & TIMER_TCR_TPSC) {
99	case 0: freq >>= 2; break;
100	case 1: freq >>= 4; break;
101	case 2: freq >>= 6; break;
102	case 3: freq >>= 8; break;
103	case 4: freq >>= 10; break;
104	case 6:
105	case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
106	default: cpu_abort (cpu_single_env,
107	"sh_timer_write: Reserved TPSC value\n"); break;
108	}
109	switch ((value & TIMER_TCR_CKEG) >> 3) {
110	case 0: break;
111	case 1:
112	case 2:
113	case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
114	default: cpu_abort (cpu_single_env,
115	"sh_timer_write: Reserved CKEG value\n"); break;
116	}
117	switch ((value & TIMER_TCR_ICPE) >> 6) {
118	case 0: break;
119	case 2:
120	case 3: if (s->feat & TIMER_FEAT_CAPT) break;
121	default: cpu_abort (cpu_single_env,
122	"sh_timer_write: Reserved ICPE value\n"); break;
123	}
124	if ((value & TIMER_TCR_UNF) == 0)
125	s->int_level = 0;
126
127	value &= ~TIMER_TCR_UNF;
128
129	if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
130	cpu_abort (cpu_single_env,
131	"sh_timer_write: Reserved ICPF value\n");
132
133	value &= ~TIMER_TCR_ICPF; /* capture not supported */
134
135	if (value & TIMER_TCR_RESERVED)
136	cpu_abort (cpu_single_env,
137	"sh_timer_write: Reserved TCR bits set\n");
138	s->tcr = value;
139	ptimer_set_limit(s->timer, s->tcor, 0);
140	ptimer_set_freq(s->timer, freq);
141	if (s->enabled) {
142	/* Restart the timer if still enabled. */
143	ptimer_run(s->timer, 0);
144	}
145	break;
146	case 3:
147	if (s->feat & TIMER_FEAT_CAPT) {
148	s->tcpr = value;
149	break;
150	}
151	default:
152	cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
153	(int)offset);
154	}
155	sh_timer_update(s);
156	}
157
158	static void sh_timer_start_stop(void *opaque, int enable)
159	{
160	sh_timer_state s = (sh_timer_state )opaque;
161
162	#ifdef DEBUG_TIMER
163	printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
164	#endif
165
166	if (s->enabled && !enable) {
167	ptimer_stop(s->timer);
168	}
169	if (!s->enabled && enable) {
170	ptimer_run(s->timer, 0);
171	}
172	s->enabled = !!enable;
173
174	#ifdef DEBUG_TIMER
175	printf("sh_timer_start_stop done %d\n", s->enabled);
176	#endif
177	}
178
179	static void sh_timer_tick(void *opaque)
180	{
181	sh_timer_state s = (sh_timer_state )opaque;
182	s->int_level = s->enabled;
183	sh_timer_update(s);
184	}
185
186	static void *sh_timer_init(uint32_t freq, int feat)
187	{
188	sh_timer_state *s;
189	QEMUBH *bh;
190
191	s = (sh_timer_state *)qemu_mallocz(sizeof(sh_timer_state));
192	s->freq = freq;
193	s->feat = feat;
194	s->tcor = 0xffffffff;
195	s->tcnt = 0xffffffff;
196	s->tcpr = 0xdeadbeef;
197	s->tcor = 0;
198	s->enabled = 0;
199
200	bh = qemu_bh_new(sh_timer_tick, s);
201	s->timer = ptimer_init(bh);
202	/* ??? Save/restore. */
203	return s;
204	}
205
206	typedef struct {
207	void *timer[3];
208	int level[3];
209	uint32_t tocr;
210	uint32_t tstr;
211	target_phys_addr_t base;
212	int feat;
213	} tmu012_state;
214
215	static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
216	{
217	tmu012_state s = (tmu012_state )opaque;
218
219	#ifdef DEBUG_TIMER
220	printf("tmu012_read 0x%lx\n", (unsigned long) offset);
221	#endif
222	offset -= s->base;
223
224	if (offset >= 0x20) {
225	if (!(s->feat & TMU012_FEAT_3CHAN))
226	cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
227	(int)offset);
228	return sh_timer_read(s->timer[2], offset - 0x20);
229	}
230
231	if (offset >= 0x14)
232	return sh_timer_read(s->timer[1], offset - 0x14);
233
234	if (offset >= 0x08)
235	return sh_timer_read(s->timer[0], offset - 0x08);
236
237	if (offset == 4)
238	return s->tstr;
239
240	if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
241	return s->tocr;
242
243	cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
244	(int)offset);
245	return 0;
246	}
247
248	static void tmu012_write(void *opaque, target_phys_addr_t offset,
249	uint32_t value)
250	{
251	tmu012_state s = (tmu012_state )opaque;
252
253	#ifdef DEBUG_TIMER
254	printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
255	#endif
256	offset -= s->base;
257
258	if (offset >= 0x20) {
259	if (!(s->feat & TMU012_FEAT_3CHAN))
260	cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
261	(int)offset);
262	sh_timer_write(s->timer[2], offset - 0x20, value);
263	return;
264	}
265
266	if (offset >= 0x14) {
267	sh_timer_write(s->timer[1], offset - 0x14, value);
268	return;
269	}
270
271	if (offset >= 0x08) {
272	sh_timer_write(s->timer[0], offset - 0x08, value);
273	return;
274	}
275
276	if (offset == 4) {
277	sh_timer_start_stop(s->timer[0], value & (1 << 0));
278	sh_timer_start_stop(s->timer[1], value & (1 << 1));
279	if (s->feat & TMU012_FEAT_3CHAN)
280	sh_timer_start_stop(s->timer[2], value & (1 << 2));
281	else
282	if (value & (1 << 2))
283	cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n");
284
285	s->tstr = value;
286	return;
287	}
288
289	if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
290	s->tocr = value & (1 << 0);
291	}
292	}
293
294	static CPUReadMemoryFunc *tmu012_readfn[] = {
295	tmu012_read,
296	tmu012_read,
297	tmu012_read
298	};
299
300	static CPUWriteMemoryFunc *tmu012_writefn[] = {
301	tmu012_write,
302	tmu012_write,
303	tmu012_write
304	};
305
306	void tmu012_init(uint32_t base, int feat, uint32_t freq)
307	{
308	int iomemtype;
309	tmu012_state *s;
310	int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
311
312	s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
313	s->base = base;
314	s->feat = feat;
315	s->timer[0] = sh_timer_init(freq, timer_feat);
316	s->timer[1] = sh_timer_init(freq, timer_feat);
317	if (feat & TMU012_FEAT_3CHAN)
318	s->timer[2] = sh_timer_init(freq, timer_feat \| TIMER_FEAT_CAPT);
319	iomemtype = cpu_register_io_memory(0, tmu012_readfn,
320	tmu012_writefn, s);
321	cpu_register_physical_memory(base, 0x00001000, iomemtype);
322	/* ??? Save/restore. */
323	}