[qemu.git] / hw / slavio_intctl.c

/*
 * QEMU Sparc SLAVIO interrupt controller emulation
 * 
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ

#ifdef DEBUG_IRQ
#define DPRINTF(fmt, args...) \
do { printf("IRQ: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

/*
 * Registers of interrupt controller in sun4m.
 *
 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * There is a system master controller and one for each cpu.
 * 
 */

#define MAX_CPUS 16

typedef struct SLAVIO_INTCTLState {
    uint32_t intreg_pending[MAX_CPUS];
    uint32_t intregm_pending;
    uint32_t intregm_disabled;
    uint32_t target_cpu;
#ifdef DEBUG_IRQ_COUNT
    uint64_t irq_count[32];
#endif
} SLAVIO_INTCTLState;

#define INTCTL_MAXADDR 0xf
#define INTCTLM_MAXADDR 0xf
static void slavio_check_interrupts(void *opaque);

// per-cpu interrupt controller
static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;
    int cpu;

    cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
    saddr = (addr & INTCTL_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	return s->intreg_pending[cpu];
    default:
	break;
    }
    return 0;
}

static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;
    int cpu;

    cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
    saddr = (addr & INTCTL_MAXADDR) >> 2;
    switch (saddr) {
    case 1: // clear pending softints
	if (val & 0x4000)
	    val |= 80000000;
	val &= 0xfffe0000;
	s->intreg_pending[cpu] &= ~val;
	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
	break;
    case 2: // set softint
	val &= 0xfffe0000;
	s->intreg_pending[cpu] |= val;
	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
    slavio_intctl_mem_readl,
    slavio_intctl_mem_readl,
    slavio_intctl_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
    slavio_intctl_mem_writel,
    slavio_intctl_mem_writel,
    slavio_intctl_mem_writel,
};

// master system interrupt controller
static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;

    saddr = (addr & INTCTLM_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	return s->intregm_pending & 0x7fffffff;
    case 1:
	return s->intregm_disabled;
    case 4:
	return s->target_cpu;
    default:
	break;
    }
    return 0;
}

static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;

    saddr = (addr & INTCTLM_MAXADDR) >> 2;
    switch (saddr) {
    case 2: // clear (enable)
	// Force clear unused bits
	val &= ~0x7fb2007f;
	s->intregm_disabled &= ~val;
	DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
	slavio_check_interrupts(s);
	break;
    case 3: // set (disable, clear pending)
	// Force clear unused bits
	val &= ~0x7fb2007f;
	s->intregm_disabled |= val;
	s->intregm_pending &= ~val;
	DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
	break;
    case 4:
	s->target_cpu = val & (MAX_CPUS - 1);
	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
    slavio_intctlm_mem_readl,
    slavio_intctlm_mem_readl,
    slavio_intctlm_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
    slavio_intctlm_mem_writel,
    slavio_intctlm_mem_writel,
    slavio_intctlm_mem_writel,
};

void slavio_pic_info(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
	term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
    }
    term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
}

void slavio_irq_info(void *opaque)
{
#ifndef DEBUG_IRQ_COUNT
    term_printf("irq statistic code not compiled.\n");
#else
    SLAVIO_INTCTLState *s = opaque;
    int i;
    int64_t count;

    term_printf("IRQ statistics:\n");
    for (i = 0; i < 32; i++) {
        count = s->irq_count[i];
        if (count > 0)
            term_printf("%2d: %lld\n", i, count);
    }
#endif
}

static const uint32_t intbit_to_level[32] = {
    2, 3, 5, 7, 9, 11, 0, 14,	3, 5, 7, 9, 11, 13, 12, 12,
    6, 0, 4, 10, 8, 0, 11, 0,	0, 0, 0, 0, 15, 0, 0, 0,
};

static void slavio_check_interrupts(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t pending = s->intregm_pending;
    unsigned int i, max = 0;

    pending &= ~s->intregm_disabled;

    if (pending && !(s->intregm_disabled & 0x80000000)) {
	for (i = 0; i < 32; i++) {
	    if (pending & (1 << i)) {
		if (max < intbit_to_level[i])
		    max = intbit_to_level[i];
	    }
	}
	if (cpu_single_env->interrupt_index == 0) {
	    DPRINTF("Triggered pil %d\n", max);
#ifdef DEBUG_IRQ_COUNT
	    s->irq_count[max]++;
#endif
	    cpu_single_env->interrupt_index = TT_EXTINT | max;
	    cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
	}
	else
	    DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, cpu_single_env->interrupt_index);
    }
    else
	DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
}

/*
 * "irq" here is the bit number in the system interrupt register to
 * separate serial and keyboard interrupts sharing a level.
 */
void slavio_pic_set_irq(void *opaque, int irq, int level)
{
    SLAVIO_INTCTLState *s = opaque;

    DPRINTF("Set irq %d level %d\n", irq, level);
    if (irq < 32) {
	uint32_t mask = 1 << irq;
	uint32_t pil = intbit_to_level[irq];
	if (pil > 0) {
	    if (level) {
		s->intregm_pending |= mask;
		s->intreg_pending[s->target_cpu] |= 1 << pil;
	    }
	    else {
		s->intregm_pending &= ~mask;
		s->intreg_pending[s->target_cpu] &= ~(1 << pil);
	    }
	}
    }
    slavio_check_interrupts(s);
}

static void slavio_intctl_save(QEMUFile *f, void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;
    
    for (i = 0; i < MAX_CPUS; i++) {
	qemu_put_be32s(f, &s->intreg_pending[i]);
    }
    qemu_put_be32s(f, &s->intregm_pending);
    qemu_put_be32s(f, &s->intregm_disabled);
    qemu_put_be32s(f, &s->target_cpu);
}

static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    for (i = 0; i < MAX_CPUS; i++) {
	qemu_get_be32s(f, &s->intreg_pending[i]);
    }
    qemu_get_be32s(f, &s->intregm_pending);
    qemu_get_be32s(f, &s->intregm_disabled);
    qemu_get_be32s(f, &s->target_cpu);
    return 0;
}

static void slavio_intctl_reset(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
	s->intreg_pending[i] = 0;
    }
    s->intregm_disabled = ~0xffb2007f;
    s->intregm_pending = 0;
    s->target_cpu = 0;
}

void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
{
    int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
    SLAVIO_INTCTLState *s;

    s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
    if (!s)
        return NULL;

    for (i = 0; i < MAX_CPUS; i++) {
	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
    }

    slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
    cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);

    register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
    qemu_register_reset(slavio_intctl_reset, s);
    slavio_intctl_reset(s);
    return s;
}
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO interrupt controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
e80cfcfc FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25	//#define DEBUG_IRQ_COUNT
66321a11 FB	26	//#define DEBUG_IRQ
	27
	28	#ifdef DEBUG_IRQ
	29	#define DPRINTF(fmt, args...) \
	30	do { printf("IRQ: " fmt , ##args); } while (0)
	31	#else
	32	#define DPRINTF(fmt, args...)
	33	#endif
e80cfcfc FB	34
	35	/*
	36	* Registers of interrupt controller in sun4m.
	37	*
	38	* This is the interrupt controller part of chip STP2001 (Slave I/O), also
	39	* produced as NCR89C105. See
	40	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	41	*
	42	* There is a system master controller and one for each cpu.
	43	*
	44	*/
	45
	46	#define MAX_CPUS 16
	47
	48	typedef struct SLAVIO_INTCTLState {
	49	uint32_t intreg_pending[MAX_CPUS];
	50	uint32_t intregm_pending;
	51	uint32_t intregm_disabled;
	52	uint32_t target_cpu;
	53	#ifdef DEBUG_IRQ_COUNT
	54	uint64_t irq_count[32];
	55	#endif
	56	} SLAVIO_INTCTLState;
	57
	58	#define INTCTL_MAXADDR 0xf
	59	#define INTCTLM_MAXADDR 0xf
66321a11	60	static void slavio_check_interrupts(void *opaque);
e80cfcfc FB	61
	62	// per-cpu interrupt controller
	63	static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
	64	{
	65	SLAVIO_INTCTLState *s = opaque;
	66	uint32_t saddr;
	67	int cpu;
	68
	69	cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
	70	saddr = (addr & INTCTL_MAXADDR) >> 2;
	71	switch (saddr) {
	72	case 0:
	73	return s->intreg_pending[cpu];
	74	default:
	75	break;
	76	}
	77	return 0;
	78	}
	79
	80	static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	81	{
	82	SLAVIO_INTCTLState *s = opaque;
	83	uint32_t saddr;
	84	int cpu;
	85
	86	cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
	87	saddr = (addr & INTCTL_MAXADDR) >> 2;
	88	switch (saddr) {
	89	case 1: // clear pending softints
	90	if (val & 0x4000)
	91	val \|= 80000000;
	92	val &= 0xfffe0000;
	93	s->intreg_pending[cpu] &= ~val;
66321a11	94	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
e80cfcfc FB	95	break;
	96	case 2: // set softint
	97	val &= 0xfffe0000;
	98	s->intreg_pending[cpu] \|= val;
66321a11	99	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
e80cfcfc FB	100	break;
	101	default:
	102	break;
	103	}
	104	}
	105
	106	static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
	107	slavio_intctl_mem_readl,
	108	slavio_intctl_mem_readl,
	109	slavio_intctl_mem_readl,
	110	};
	111
	112	static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
	113	slavio_intctl_mem_writel,
	114	slavio_intctl_mem_writel,
	115	slavio_intctl_mem_writel,
	116	};
	117
	118	// master system interrupt controller
	119	static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
	120	{
	121	SLAVIO_INTCTLState *s = opaque;
	122	uint32_t saddr;
	123
	124	saddr = (addr & INTCTLM_MAXADDR) >> 2;
	125	switch (saddr) {
	126	case 0:
6bae7071	127	return s->intregm_pending & 0x7fffffff;
e80cfcfc FB	128	case 1:
	129	return s->intregm_disabled;
	130	case 4:
	131	return s->target_cpu;
	132	default:
	133	break;
	134	}
	135	return 0;
	136	}
	137
	138	static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	139	{
	140	SLAVIO_INTCTLState *s = opaque;
	141	uint32_t saddr;
	142
	143	saddr = (addr & INTCTLM_MAXADDR) >> 2;
	144	switch (saddr) {
	145	case 2: // clear (enable)
6bae7071 FB	146	// Force clear unused bits
6bae7071 FB	147	val &= ~0x7fb2007f;
e80cfcfc	148	s->intregm_disabled &= ~val;
66321a11 FB	149	DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
66321a11 FB	150	slavio_check_interrupts(s);
e80cfcfc FB	151	break;
e80cfcfc FB	152	case 3: // set (disable, clear pending)
6bae7071	153	// Force clear unused bits
e80cfcfc FB	154	val &= ~0x7fb2007f;
	155	s->intregm_disabled \|= val;
	156	s->intregm_pending &= ~val;
66321a11	157	DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
e80cfcfc FB	158	break;
	159	case 4:
	160	s->target_cpu = val & (MAX_CPUS - 1);
66321a11	161	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
e80cfcfc FB	162	break;
	163	default:
	164	break;
	165	}
	166	}
	167
	168	static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
	169	slavio_intctlm_mem_readl,
	170	slavio_intctlm_mem_readl,
	171	slavio_intctlm_mem_readl,
	172	};
	173
	174	static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
	175	slavio_intctlm_mem_writel,
	176	slavio_intctlm_mem_writel,
	177	slavio_intctlm_mem_writel,
	178	};
	179
	180	void slavio_pic_info(void *opaque)
	181	{
	182	SLAVIO_INTCTLState *s = opaque;
	183	int i;
	184
	185	for (i = 0; i < MAX_CPUS; i++) {
	186	term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
	187	}
	188	term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
	189	}
	190
	191	void slavio_irq_info(void *opaque)
	192	{
	193	#ifndef DEBUG_IRQ_COUNT
	194	term_printf("irq statistic code not compiled.\n");
	195	#else
	196	SLAVIO_INTCTLState *s = opaque;
	197	int i;
	198	int64_t count;
	199
	200	term_printf("IRQ statistics:\n");
	201	for (i = 0; i < 32; i++) {
	202	count = s->irq_count[i];
	203	if (count > 0)
	204	term_printf("%2d: %lld\n", i, count);
	205	}
	206	#endif
	207	}
	208
	209	static const uint32_t intbit_to_level[32] = {
	210	2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
	211	6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 0, 0,
	212	};
	213
66321a11 FB	214	static void slavio_check_interrupts(void *opaque)
	215	{
	216	SLAVIO_INTCTLState *s = opaque;
	217	uint32_t pending = s->intregm_pending;
	218	unsigned int i, max = 0;
	219
	220	pending &= ~s->intregm_disabled;
	221
	222	if (pending && !(s->intregm_disabled & 0x80000000)) {
	223	for (i = 0; i < 32; i++) {
	224	if (pending & (1 << i)) {
	225	if (max < intbit_to_level[i])
	226	max = intbit_to_level[i];
	227	}
	228	}
	229	if (cpu_single_env->interrupt_index == 0) {
	230	DPRINTF("Triggered pil %d\n", max);
	231	#ifdef DEBUG_IRQ_COUNT
	232	s->irq_count[max]++;
	233	#endif
	234	cpu_single_env->interrupt_index = TT_EXTINT \| max;
	235	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
	236	}
	237	else
	238	DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, cpu_single_env->interrupt_index);
	239	}
	240	else
	241	DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
	242	}
	243
e80cfcfc FB	244	/*
	245	* "irq" here is the bit number in the system interrupt register to
	246	* separate serial and keyboard interrupts sharing a level.
	247	*/
	248	void slavio_pic_set_irq(void *opaque, int irq, int level)
	249	{
	250	SLAVIO_INTCTLState *s = opaque;
	251
66321a11	252	DPRINTF("Set irq %d level %d\n", irq, level);
e80cfcfc FB	253	if (irq < 32) {
	254	uint32_t mask = 1 << irq;
	255	uint32_t pil = intbit_to_level[irq];
	256	if (pil > 0) {
	257	if (level) {
	258	s->intregm_pending \|= mask;
	259	s->intreg_pending[s->target_cpu] \|= 1 << pil;
	260	}
	261	else {
	262	s->intregm_pending &= ~mask;
	263	s->intreg_pending[s->target_cpu] &= ~(1 << pil);
	264	}
e80cfcfc FB	265	}
e80cfcfc FB	266	}
66321a11	267	slavio_check_interrupts(s);
e80cfcfc FB	268	}
	269
	270	static void slavio_intctl_save(QEMUFile f, void opaque)
	271	{
	272	SLAVIO_INTCTLState *s = opaque;
	273	int i;
	274
	275	for (i = 0; i < MAX_CPUS; i++) {
	276	qemu_put_be32s(f, &s->intreg_pending[i]);
	277	}
	278	qemu_put_be32s(f, &s->intregm_pending);
	279	qemu_put_be32s(f, &s->intregm_disabled);
	280	qemu_put_be32s(f, &s->target_cpu);
	281	}
	282
	283	static int slavio_intctl_load(QEMUFile f, void opaque, int version_id)
	284	{
	285	SLAVIO_INTCTLState *s = opaque;
	286	int i;
	287
	288	if (version_id != 1)
	289	return -EINVAL;
	290
	291	for (i = 0; i < MAX_CPUS; i++) {
	292	qemu_get_be32s(f, &s->intreg_pending[i]);
	293	}
	294	qemu_get_be32s(f, &s->intregm_pending);
	295	qemu_get_be32s(f, &s->intregm_disabled);
	296	qemu_get_be32s(f, &s->target_cpu);
	297	return 0;
	298	}
	299
	300	static void slavio_intctl_reset(void *opaque)
	301	{
	302	SLAVIO_INTCTLState *s = opaque;
	303	int i;
	304
	305	for (i = 0; i < MAX_CPUS; i++) {
	306	s->intreg_pending[i] = 0;
	307	}
6bae7071	308	s->intregm_disabled = ~0xffb2007f;
e80cfcfc FB	309	s->intregm_pending = 0;
	310	s->target_cpu = 0;
	311	}
	312
	313	void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
	314	{
	315	int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
	316	SLAVIO_INTCTLState *s;
	317
	318	s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
	319	if (!s)
	320	return NULL;
	321
	322	for (i = 0; i < MAX_CPUS; i++) {
	323	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
	324	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
	325	}
	326
	327	slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
	328	cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);
	329
	330	register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
	331	qemu_register_reset(slavio_intctl_reset, s);
	332	slavio_intctl_reset(s);
	333	return s;
	334	}
	335