[qemu.git] / hw / slavio_intctl.c

/*
 * QEMU Sparc SLAVIO interrupt controller emulation
 * 
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ

#ifdef DEBUG_IRQ
#define DPRINTF(fmt, args...) \
do { printf("IRQ: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

/*
 * Registers of interrupt controller in sun4m.
 *
 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * There is a system master controller and one for each cpu.
 * 
 */

#define MAX_CPUS 16

typedef struct SLAVIO_INTCTLState {
    uint32_t intreg_pending[MAX_CPUS];
    uint32_t intregm_pending;
    uint32_t intregm_disabled;
    uint32_t target_cpu;
#ifdef DEBUG_IRQ_COUNT
    uint64_t irq_count[32];
#endif
    CPUState *cpu_envs[MAX_CPUS];
} SLAVIO_INTCTLState;

#define INTCTL_MAXADDR 0xf
#define INTCTLM_MAXADDR 0xf
static void slavio_check_interrupts(void *opaque);

// per-cpu interrupt controller
static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;
    int cpu;

    cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
    saddr = (addr & INTCTL_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	return s->intreg_pending[cpu];
    default:
	break;
    }
    return 0;
}

static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;
    int cpu;

    cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
    saddr = (addr & INTCTL_MAXADDR) >> 2;
    switch (saddr) {
    case 1: // clear pending softints
	if (val & 0x4000)
	    val |= 80000000;
	val &= 0xfffe0000;
	s->intreg_pending[cpu] &= ~val;
	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
	break;
    case 2: // set softint
	val &= 0xfffe0000;
	s->intreg_pending[cpu] |= val;
        slavio_check_interrupts(s);
	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
    slavio_intctl_mem_readl,
    slavio_intctl_mem_readl,
    slavio_intctl_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
    slavio_intctl_mem_writel,
    slavio_intctl_mem_writel,
    slavio_intctl_mem_writel,
};

// master system interrupt controller
static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;

    saddr = (addr & INTCTLM_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	return s->intregm_pending & 0x7fffffff;
    case 1:
	return s->intregm_disabled;
    case 4:
	return s->target_cpu;
    default:
	break;
    }
    return 0;
}

static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;

    saddr = (addr & INTCTLM_MAXADDR) >> 2;
    switch (saddr) {
    case 2: // clear (enable)
	// Force clear unused bits
	val &= ~0x4fb2007f;
	s->intregm_disabled &= ~val;
	DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
	slavio_check_interrupts(s);
	break;
    case 3: // set (disable, clear pending)
	// Force clear unused bits
	val &= ~0x4fb2007f;
	s->intregm_disabled |= val;
	s->intregm_pending &= ~val;
	DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
	break;
    case 4:
	s->target_cpu = val & (MAX_CPUS - 1);
	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
    slavio_intctlm_mem_readl,
    slavio_intctlm_mem_readl,
    slavio_intctlm_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
    slavio_intctlm_mem_writel,
    slavio_intctlm_mem_writel,
    slavio_intctlm_mem_writel,
};

void slavio_pic_info(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
	term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
    }
    term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
}

void slavio_irq_info(void *opaque)
{
#ifndef DEBUG_IRQ_COUNT
    term_printf("irq statistic code not compiled.\n");
#else
    SLAVIO_INTCTLState *s = opaque;
    int i;
    int64_t count;

    term_printf("IRQ statistics:\n");
    for (i = 0; i < 32; i++) {
        count = s->irq_count[i];
        if (count > 0)
            term_printf("%2d: %lld\n", i, count);
    }
#endif
}

static const uint32_t intbit_to_level[32] = {
    2, 3, 5, 7, 9, 11, 0, 14,	3, 5, 7, 9, 11, 13, 12, 12,
    6, 0, 4, 10, 8, 0, 11, 0,	0, 0, 0, 0, 15, 0, 15, 0,
};

static void slavio_check_interrupts(void *opaque)
{
    CPUState *env;
    SLAVIO_INTCTLState *s = opaque;
    uint32_t pending = s->intregm_pending;
    unsigned int i, j, max = 0;

    pending &= ~s->intregm_disabled;

    if (pending && !(s->intregm_disabled & 0x80000000)) {
	for (i = 0; i < 32; i++) {
	    if (pending & (1 << i)) {
		if (max < intbit_to_level[i])
		    max = intbit_to_level[i];
	    }
	}
        env = s->cpu_envs[s->target_cpu];
        if (!env) {
	    DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
        }
	else {
            if (env->halted)
                env->halted = 0;
            if (env->interrupt_index == 0) {
                DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
#ifdef DEBUG_IRQ_COUNT
                s->irq_count[max]++;
#endif
                env->interrupt_index = TT_EXTINT | max;
                cpu_interrupt(env, CPU_INTERRUPT_HARD);
            }
            else
                DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
	}
    }
    else
	DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
    
    for (i = 0; i < MAX_CPUS; i++) {
        max = 0;
        env = s->cpu_envs[i];
        if (!env)
            continue;
        for (j = 17; j < 32; j++) {
            if (s->intreg_pending[i] & (1 << j)) {
                if (max < j - 16)
                    max = j - 16;
            }
        }
	if (max > 0) {
            if (env->halted)
                env->halted = 0;
            if (env->interrupt_index == 0) {
                DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
#ifdef DEBUG_IRQ_COUNT
                s->irq_count[max]++;
#endif
                env->interrupt_index = TT_EXTINT | max;
                cpu_interrupt(env, CPU_INTERRUPT_HARD);
            }
        }
    }
}

/*
 * "irq" here is the bit number in the system interrupt register to
 * separate serial and keyboard interrupts sharing a level.
 */
void slavio_pic_set_irq(void *opaque, int irq, int level)
{
    SLAVIO_INTCTLState *s = opaque;

    DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
    if (irq < 32) {
	uint32_t mask = 1 << irq;
	uint32_t pil = intbit_to_level[irq];
	if (pil > 0) {
	    if (level) {
		s->intregm_pending |= mask;
		s->intreg_pending[s->target_cpu] |= 1 << pil;
	    }
	    else {
		s->intregm_pending &= ~mask;
		s->intreg_pending[s->target_cpu] &= ~(1 << pil);
	    }
	}
    }
    slavio_check_interrupts(s);
}

void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
{
    SLAVIO_INTCTLState *s = opaque;

    DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
    if (cpu == (unsigned int)-1) {
        slavio_pic_set_irq(opaque, irq, level);
        return;
    }
    if (irq < 32) {
	uint32_t pil = intbit_to_level[irq];
    	if (pil > 0) {
	    if (level) {
		s->intreg_pending[cpu] |= 1 << pil;
	    }
	    else {
		s->intreg_pending[cpu] &= ~(1 << pil);
	    }
	}
    }
    slavio_check_interrupts(s);
}

static void slavio_intctl_save(QEMUFile *f, void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;
    
    for (i = 0; i < MAX_CPUS; i++) {
	qemu_put_be32s(f, &s->intreg_pending[i]);
    }
    qemu_put_be32s(f, &s->intregm_pending);
    qemu_put_be32s(f, &s->intregm_disabled);
    qemu_put_be32s(f, &s->target_cpu);
}

static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    for (i = 0; i < MAX_CPUS; i++) {
	qemu_get_be32s(f, &s->intreg_pending[i]);
    }
    qemu_get_be32s(f, &s->intregm_pending);
    qemu_get_be32s(f, &s->intregm_disabled);
    qemu_get_be32s(f, &s->target_cpu);
    return 0;
}

static void slavio_intctl_reset(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
	s->intreg_pending[i] = 0;
    }
    s->intregm_disabled = ~0xffb2007f;
    s->intregm_pending = 0;
    s->target_cpu = 0;
}

void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
{
    SLAVIO_INTCTLState *s = opaque;
    s->cpu_envs[cpu] = env;
}

void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
{
    int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
    SLAVIO_INTCTLState *s;

    s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
    if (!s)
        return NULL;

    for (i = 0; i < MAX_CPUS; i++) {
	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
    }

    slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
    cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);

    register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
    qemu_register_reset(slavio_intctl_reset, s);
    slavio_intctl_reset(s);
    return s;
}
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO interrupt controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
e80cfcfc FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25	//#define DEBUG_IRQ_COUNT
66321a11 FB	26	//#define DEBUG_IRQ
	27
	28	#ifdef DEBUG_IRQ
	29	#define DPRINTF(fmt, args...) \
	30	do { printf("IRQ: " fmt , ##args); } while (0)
	31	#else
	32	#define DPRINTF(fmt, args...)
	33	#endif
e80cfcfc FB	34
	35	/*
	36	* Registers of interrupt controller in sun4m.
	37	*
	38	* This is the interrupt controller part of chip STP2001 (Slave I/O), also
	39	* produced as NCR89C105. See
	40	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	41	*
	42	* There is a system master controller and one for each cpu.
	43	*
	44	*/
	45
	46	#define MAX_CPUS 16
	47
	48	typedef struct SLAVIO_INTCTLState {
	49	uint32_t intreg_pending[MAX_CPUS];
	50	uint32_t intregm_pending;
	51	uint32_t intregm_disabled;
	52	uint32_t target_cpu;
	53	#ifdef DEBUG_IRQ_COUNT
	54	uint64_t irq_count[32];
	55	#endif
ba3c64fb	56	CPUState *cpu_envs[MAX_CPUS];
e80cfcfc FB	57	} SLAVIO_INTCTLState;
	58
	59	#define INTCTL_MAXADDR 0xf
	60	#define INTCTLM_MAXADDR 0xf
66321a11	61	static void slavio_check_interrupts(void *opaque);
e80cfcfc FB	62
	63	// per-cpu interrupt controller
	64	static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
	65	{
	66	SLAVIO_INTCTLState *s = opaque;
	67	uint32_t saddr;
	68	int cpu;
	69
	70	cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
	71	saddr = (addr & INTCTL_MAXADDR) >> 2;
	72	switch (saddr) {
	73	case 0:
	74	return s->intreg_pending[cpu];
	75	default:
	76	break;
	77	}
	78	return 0;
	79	}
	80
	81	static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	82	{
	83	SLAVIO_INTCTLState *s = opaque;
	84	uint32_t saddr;
	85	int cpu;
	86
	87	cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
	88	saddr = (addr & INTCTL_MAXADDR) >> 2;
	89	switch (saddr) {
	90	case 1: // clear pending softints
	91	if (val & 0x4000)
	92	val \|= 80000000;
	93	val &= 0xfffe0000;
	94	s->intreg_pending[cpu] &= ~val;
66321a11	95	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
e80cfcfc FB	96	break;
	97	case 2: // set softint
	98	val &= 0xfffe0000;
	99	s->intreg_pending[cpu] \|= val;
ba3c64fb	100	slavio_check_interrupts(s);
66321a11	101	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
e80cfcfc FB	102	break;
	103	default:
	104	break;
	105	}
	106	}
	107
	108	static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
	109	slavio_intctl_mem_readl,
	110	slavio_intctl_mem_readl,
	111	slavio_intctl_mem_readl,
	112	};
	113
	114	static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
	115	slavio_intctl_mem_writel,
	116	slavio_intctl_mem_writel,
	117	slavio_intctl_mem_writel,
	118	};
	119
	120	// master system interrupt controller
	121	static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
	122	{
	123	SLAVIO_INTCTLState *s = opaque;
	124	uint32_t saddr;
	125
	126	saddr = (addr & INTCTLM_MAXADDR) >> 2;
	127	switch (saddr) {
	128	case 0:
6bae7071	129	return s->intregm_pending & 0x7fffffff;
e80cfcfc FB	130	case 1:
	131	return s->intregm_disabled;
	132	case 4:
	133	return s->target_cpu;
	134	default:
	135	break;
	136	}
	137	return 0;
	138	}
	139
	140	static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	141	{
	142	SLAVIO_INTCTLState *s = opaque;
	143	uint32_t saddr;
	144
	145	saddr = (addr & INTCTLM_MAXADDR) >> 2;
	146	switch (saddr) {
	147	case 2: // clear (enable)
6bae7071	148	// Force clear unused bits
3475187d	149	val &= ~0x4fb2007f;
e80cfcfc	150	s->intregm_disabled &= ~val;
66321a11 FB	151	DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
66321a11 FB	152	slavio_check_interrupts(s);
e80cfcfc FB	153	break;
e80cfcfc FB	154	case 3: // set (disable, clear pending)
6bae7071	155	// Force clear unused bits
3475187d	156	val &= ~0x4fb2007f;
e80cfcfc FB	157	s->intregm_disabled \|= val;
e80cfcfc FB	158	s->intregm_pending &= ~val;
66321a11	159	DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
e80cfcfc FB	160	break;
	161	case 4:
	162	s->target_cpu = val & (MAX_CPUS - 1);
66321a11	163	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
e80cfcfc FB	164	break;
	165	default:
	166	break;
	167	}
	168	}
	169
	170	static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
	171	slavio_intctlm_mem_readl,
	172	slavio_intctlm_mem_readl,
	173	slavio_intctlm_mem_readl,
	174	};
	175
	176	static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
	177	slavio_intctlm_mem_writel,
	178	slavio_intctlm_mem_writel,
	179	slavio_intctlm_mem_writel,
	180	};
	181
	182	void slavio_pic_info(void *opaque)
	183	{
	184	SLAVIO_INTCTLState *s = opaque;
	185	int i;
	186
	187	for (i = 0; i < MAX_CPUS; i++) {
	188	term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
	189	}
	190	term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
	191	}
	192
	193	void slavio_irq_info(void *opaque)
	194	{
	195	#ifndef DEBUG_IRQ_COUNT
	196	term_printf("irq statistic code not compiled.\n");
	197	#else
	198	SLAVIO_INTCTLState *s = opaque;
	199	int i;
	200	int64_t count;
	201
	202	term_printf("IRQ statistics:\n");
	203	for (i = 0; i < 32; i++) {
	204	count = s->irq_count[i];
	205	if (count > 0)
	206	term_printf("%2d: %lld\n", i, count);
	207	}
	208	#endif
	209	}
	210
	211	static const uint32_t intbit_to_level[32] = {
	212	2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
3475187d	213	6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
e80cfcfc FB	214	};
e80cfcfc FB	215
66321a11 FB	216	static void slavio_check_interrupts(void *opaque)
66321a11 FB	217	{
c68ea704	218	CPUState *env;
66321a11 FB	219	SLAVIO_INTCTLState *s = opaque;
66321a11 FB	220	uint32_t pending = s->intregm_pending;
ba3c64fb	221	unsigned int i, j, max = 0;
66321a11 FB	222
	223	pending &= ~s->intregm_disabled;
	224
	225	if (pending && !(s->intregm_disabled & 0x80000000)) {
	226	for (i = 0; i < 32; i++) {
	227	if (pending & (1 << i)) {
	228	if (max < intbit_to_level[i])
	229	max = intbit_to_level[i];
	230	}
	231	}
ba3c64fb FB	232	env = s->cpu_envs[s->target_cpu];
	233	if (!env) {
	234	DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
	235	}
	236	else {
	237	if (env->halted)
	238	env->halted = 0;
	239	if (env->interrupt_index == 0) {
	240	DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
66321a11	241	#ifdef DEBUG_IRQ_COUNT
ba3c64fb	242	s->irq_count[max]++;
66321a11	243	#endif
ba3c64fb FB	244	env->interrupt_index = TT_EXTINT \| max;
	245	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	246	}
	247	else
	248	DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
66321a11	249	}
66321a11 FB	250	}
	251	else
	252	DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
ba3c64fb FB	253
	254	for (i = 0; i < MAX_CPUS; i++) {
	255	max = 0;
	256	env = s->cpu_envs[i];
	257	if (!env)
	258	continue;
	259	for (j = 17; j < 32; j++) {
	260	if (s->intreg_pending[i] & (1 << j)) {
	261	if (max < j - 16)
	262	max = j - 16;
	263	}
	264	}
	265	if (max > 0) {
	266	if (env->halted)
	267	env->halted = 0;
	268	if (env->interrupt_index == 0) {
	269	DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
	270	#ifdef DEBUG_IRQ_COUNT
	271	s->irq_count[max]++;
	272	#endif
	273	env->interrupt_index = TT_EXTINT \| max;
	274	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	275	}
	276	}
	277	}
66321a11 FB	278	}
66321a11 FB	279
e80cfcfc FB	280	/*
	281	* "irq" here is the bit number in the system interrupt register to
	282	* separate serial and keyboard interrupts sharing a level.
	283	*/
	284	void slavio_pic_set_irq(void *opaque, int irq, int level)
	285	{
	286	SLAVIO_INTCTLState *s = opaque;
	287
ba3c64fb	288	DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
e80cfcfc FB	289	if (irq < 32) {
	290	uint32_t mask = 1 << irq;
	291	uint32_t pil = intbit_to_level[irq];
	292	if (pil > 0) {
	293	if (level) {
	294	s->intregm_pending \|= mask;
	295	s->intreg_pending[s->target_cpu] \|= 1 << pil;
	296	}
	297	else {
	298	s->intregm_pending &= ~mask;
	299	s->intreg_pending[s->target_cpu] &= ~(1 << pil);
	300	}
e80cfcfc FB	301	}
e80cfcfc FB	302	}
66321a11	303	slavio_check_interrupts(s);
e80cfcfc FB	304	}
e80cfcfc FB	305
ba3c64fb FB	306	void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
	307	{
	308	SLAVIO_INTCTLState *s = opaque;
	309
	310	DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
	311	if (cpu == (unsigned int)-1) {
	312	slavio_pic_set_irq(opaque, irq, level);
	313	return;
	314	}
	315	if (irq < 32) {
	316	uint32_t pil = intbit_to_level[irq];
	317	if (pil > 0) {
	318	if (level) {
	319	s->intreg_pending[cpu] \|= 1 << pil;
	320	}
	321	else {
	322	s->intreg_pending[cpu] &= ~(1 << pil);
	323	}
	324	}
	325	}
	326	slavio_check_interrupts(s);
	327	}
	328
e80cfcfc FB	329	static void slavio_intctl_save(QEMUFile f, void opaque)
	330	{
	331	SLAVIO_INTCTLState *s = opaque;
	332	int i;
	333
	334	for (i = 0; i < MAX_CPUS; i++) {
	335	qemu_put_be32s(f, &s->intreg_pending[i]);
	336	}
	337	qemu_put_be32s(f, &s->intregm_pending);
	338	qemu_put_be32s(f, &s->intregm_disabled);
	339	qemu_put_be32s(f, &s->target_cpu);
	340	}
	341
	342	static int slavio_intctl_load(QEMUFile f, void opaque, int version_id)
	343	{
	344	SLAVIO_INTCTLState *s = opaque;
	345	int i;
	346
	347	if (version_id != 1)
	348	return -EINVAL;
	349
	350	for (i = 0; i < MAX_CPUS; i++) {
	351	qemu_get_be32s(f, &s->intreg_pending[i]);
	352	}
	353	qemu_get_be32s(f, &s->intregm_pending);
	354	qemu_get_be32s(f, &s->intregm_disabled);
	355	qemu_get_be32s(f, &s->target_cpu);
	356	return 0;
	357	}
	358
	359	static void slavio_intctl_reset(void *opaque)
	360	{
	361	SLAVIO_INTCTLState *s = opaque;
	362	int i;
	363
	364	for (i = 0; i < MAX_CPUS; i++) {
	365	s->intreg_pending[i] = 0;
	366	}
6bae7071	367	s->intregm_disabled = ~0xffb2007f;
e80cfcfc FB	368	s->intregm_pending = 0;
	369	s->target_cpu = 0;
	370	}
	371
ba3c64fb FB	372	void slavio_intctl_set_cpu(void opaque, unsigned int cpu, CPUState env)
	373	{
	374	SLAVIO_INTCTLState *s = opaque;
	375	s->cpu_envs[cpu] = env;
	376	}
	377
e80cfcfc FB	378	void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
	379	{
	380	int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
	381	SLAVIO_INTCTLState *s;
	382
	383	s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
	384	if (!s)
	385	return NULL;
	386
	387	for (i = 0; i < MAX_CPUS; i++) {
	388	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
	389	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
	390	}
	391
	392	slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
	393	cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);
	394
	395	register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
	396	qemu_register_reset(slavio_intctl_reset, s);
	397	slavio_intctl_reset(s);
	398	return s;
	399	}
	400