[qemu.git] / hw / slavio_misc.c

/*
 * QEMU Sparc SLAVIO aux io port emulation
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"
#include "sysemu.h"

/* debug misc */
//#define DEBUG_MISC

/*
 * This is the auxio port, chip control and system control part of
 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * This also includes the PMC CPU idle controller.
 */

#ifdef DEBUG_MISC
#define MISC_DPRINTF(fmt, args...) \
do { printf("MISC: " fmt , ##args); } while (0)
#else
#define MISC_DPRINTF(fmt, args...)
#endif

typedef struct MiscState {
    qemu_irq irq;
    uint8_t config;
    uint8_t aux1, aux2;
    uint8_t diag, mctrl;
    uint32_t sysctrl;
    uint16_t leds;
    qemu_irq cpu_halt;
    qemu_irq fdc_tc;
} MiscState;

#define MISC_SIZE 1
#define SYSCTRL_SIZE 4
#define LED_MAXADDR 1
#define LED_SIZE (LED_MAXADDR + 1)

#define MISC_MASK 0x0fff0000
#define MISC_LEDS 0x01600000
#define MISC_CFG  0x01800000
#define MISC_DIAG 0x01a00000
#define MISC_MDM  0x01b00000
#define MISC_SYS  0x01f00000

#define AUX1_TC        0x02

#define AUX2_PWROFF    0x01
#define AUX2_PWRINTCLR 0x02
#define AUX2_PWRFAIL   0x20

#define CFG_PWRINTEN   0x08

#define SYS_RESET      0x01
#define SYS_RESETSTAT  0x02

static void slavio_misc_update_irq(void *opaque)
{
    MiscState *s = opaque;

    if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
        MISC_DPRINTF("Raise IRQ\n");
        qemu_irq_raise(s->irq);
    } else {
        MISC_DPRINTF("Lower IRQ\n");
        qemu_irq_lower(s->irq);
    }
}

static void slavio_misc_reset(void *opaque)
{
    MiscState *s = opaque;

    // Diagnostic and system control registers not cleared in reset
    s->config = s->aux1 = s->aux2 = s->mctrl = 0;
}

void slavio_set_power_fail(void *opaque, int power_failing)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
    if (power_failing && (s->config & CFG_PWRINTEN)) {
        s->aux2 |= AUX2_PWRFAIL;
    } else {
        s->aux2 &= ~AUX2_PWRFAIL;
    }
    slavio_misc_update_irq(s);
}

static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
    s->config = val & 0xff;
    slavio_misc_update_irq(s);
}

static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->config;
    MISC_DPRINTF("Read config %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc *slavio_cfg_mem_read[3] = {
    slavio_cfg_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_cfg_mem_write[3] = {
    slavio_cfg_mem_writeb,
    NULL,
    NULL,
};

static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
    s->diag = val & 0xff;
}

static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->diag;
    MISC_DPRINTF("Read diag %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc *slavio_diag_mem_read[3] = {
    slavio_diag_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_diag_mem_write[3] = {
    slavio_diag_mem_writeb,
    NULL,
    NULL,
};

static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
    s->mctrl = val & 0xff;
}

static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->mctrl;
    MISC_DPRINTF("Read modem control %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc *slavio_mdm_mem_read[3] = {
    slavio_mdm_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_mdm_mem_write[3] = {
    slavio_mdm_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
    if (val & AUX1_TC) {
        // Send a pulse to floppy terminal count line
        if (s->fdc_tc) {
            qemu_irq_raise(s->fdc_tc);
            qemu_irq_lower(s->fdc_tc);
        }
        val &= ~AUX1_TC;
    }
    s->aux1 = val & 0xff;
}

static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux1;
    MISC_DPRINTF("Read aux1 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
    slavio_aux1_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
    slavio_aux1_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    val &= AUX2_PWRINTCLR | AUX2_PWROFF;
    MISC_DPRINTF("Write aux2 %2.2x\n", val);
    val |= s->aux2 & AUX2_PWRFAIL;
    if (val & AUX2_PWRINTCLR) // Clear Power Fail int
        val &= AUX2_PWROFF;
    s->aux2 = val;
    if (val & AUX2_PWROFF)
        qemu_system_shutdown_request();
    slavio_misc_update_irq(s);
}

static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux2;
    MISC_DPRINTF("Read aux2 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
    slavio_aux2_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
    slavio_aux2_mem_writeb,
    NULL,
    NULL,
};

static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
    qemu_irq_raise(s->cpu_halt);
}

static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
{
    uint32_t ret = 0;

    MISC_DPRINTF("Read power management %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc *apc_mem_read[3] = {
    apc_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *apc_mem_write[3] = {
    apc_mem_writeb,
    NULL,
    NULL,
};

static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->sysctrl;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read system control %08x\n", ret);
    return ret;
}

static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write system control %08x\n", val);
    switch (addr) {
    case 0:
        if (val & SYS_RESET) {
            s->sysctrl = SYS_RESETSTAT;
            qemu_system_reset_request();
        }
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_readl,
};

static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_writel,
};

static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr) {
    case 0:
        ret = s->leds;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
    return ret;
}

static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
    switch (addr) {
    case 0:
        s->leds = val;
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
    NULL,
    slavio_led_mem_readw,
    NULL,
};

static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
    NULL,
    slavio_led_mem_writew,
    NULL,
};

static void slavio_misc_save(QEMUFile *f, void *opaque)
{
    MiscState *s = opaque;
    uint32_t tmp = 0;
    uint8_t tmp8;

    qemu_put_be32s(f, &tmp); /* ignored, was IRQ.  */
    qemu_put_8s(f, &s->config);
    qemu_put_8s(f, &s->aux1);
    qemu_put_8s(f, &s->aux2);
    qemu_put_8s(f, &s->diag);
    qemu_put_8s(f, &s->mctrl);
    tmp8 = s->sysctrl & 0xff;
    qemu_put_8s(f, &tmp8);
}

static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
{
    MiscState *s = opaque;
    uint32_t tmp;
    uint8_t tmp8;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, &tmp);
    qemu_get_8s(f, &s->config);
    qemu_get_8s(f, &s->aux1);
    qemu_get_8s(f, &s->aux2);
    qemu_get_8s(f, &s->diag);
    qemu_get_8s(f, &s->mctrl);
    qemu_get_8s(f, &tmp8);
    s->sysctrl = (uint32_t)tmp8;
    return 0;
}

void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
                       target_phys_addr_t aux1_base,
                       target_phys_addr_t aux2_base, qemu_irq irq,
                       qemu_irq cpu_halt, qemu_irq **fdc_tc)
{
    int io;
    MiscState *s;

    s = qemu_mallocz(sizeof(MiscState));
    if (!s)
        return NULL;

    if (base) {
        /* 8 bit registers */

        // Slavio control
        io = cpu_register_io_memory(0, slavio_cfg_mem_read,
                                    slavio_cfg_mem_write, s);
        cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);

        // Diagnostics
        io = cpu_register_io_memory(0, slavio_diag_mem_read,
                                    slavio_diag_mem_write, s);
        cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);

        // Modem control
        io = cpu_register_io_memory(0, slavio_mdm_mem_read,
                                    slavio_mdm_mem_write, s);
        cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);

        /* 16 bit registers */
        io = cpu_register_io_memory(0, slavio_led_mem_read,
                                    slavio_led_mem_write, s);
        /* ss600mp diag LEDs */
        cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);

        /* 32 bit registers */
        io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
                                    slavio_sysctrl_mem_write, s);
        // System control
        cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
    }

    // AUX 1 (Misc System Functions)
    if (aux1_base) {
        io = cpu_register_io_memory(0, slavio_aux1_mem_read,
                                    slavio_aux1_mem_write, s);
        cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
    }

    // AUX 2 (Software Powerdown Control)
    if (aux2_base) {
        io = cpu_register_io_memory(0, slavio_aux2_mem_read,
                                    slavio_aux2_mem_write, s);
        cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
    }

    // Power management (APC) XXX: not a Slavio device
    if (power_base) {
        io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
        cpu_register_physical_memory(power_base, MISC_SIZE, io);
    }

    s->irq = irq;
    s->cpu_halt = cpu_halt;
    *fdc_tc = &s->fdc_tc;

    register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
                    s);
    qemu_register_reset(slavio_misc_reset, s);
    slavio_misc_reset(s);

    return s;
}
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sparc SLAVIO aux io port emulation
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "sun4m.h"
	26	#include "sysemu.h"
	27
3475187d FB	28	/* debug misc */
	29	//#define DEBUG_MISC
	30
	31	/*
	32	* This is the auxio port, chip control and system control part of
	33	* chip STP2001 (Slave I/O), also produced as NCR89C105. See
	34	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	35	*
	36	* This also includes the PMC CPU idle controller.
	37	*/
	38
	39	#ifdef DEBUG_MISC
	40	#define MISC_DPRINTF(fmt, args...) \
	41	do { printf("MISC: " fmt , ##args); } while (0)
	42	#else
	43	#define MISC_DPRINTF(fmt, args...)
	44	#endif
	45
	46	typedef struct MiscState {
d537cf6c	47	qemu_irq irq;
3475187d FB	48	uint8_t config;
3475187d FB	49	uint8_t aux1, aux2;
bfa30a38 BS	50	uint8_t diag, mctrl;
bfa30a38 BS	51	uint32_t sysctrl;
6a3b9cc9	52	uint16_t leds;
6d0c293d	53	qemu_irq cpu_halt;
2be17ebd	54	qemu_irq fdc_tc;
3475187d FB	55	} MiscState;
3475187d FB	56
5aca8c3b	57	#define MISC_SIZE 1
a8f48dcc	58	#define SYSCTRL_SIZE 4
d5296cb5	59	#define LED_MAXADDR 1
6a3b9cc9	60	#define LED_SIZE (LED_MAXADDR + 1)
3475187d	61
7debeb82 BS	62	#define MISC_MASK 0x0fff0000
	63	#define MISC_LEDS 0x01600000
	64	#define MISC_CFG 0x01800000
7debeb82 BS	65	#define MISC_DIAG 0x01a00000
	66	#define MISC_MDM 0x01b00000
	67	#define MISC_SYS 0x01f00000
7debeb82	68
2be17ebd BS	69	#define AUX1_TC 0x02
2be17ebd BS	70
7debeb82 BS	71	#define AUX2_PWROFF 0x01
	72	#define AUX2_PWRINTCLR 0x02
	73	#define AUX2_PWRFAIL 0x20
	74
	75	#define CFG_PWRINTEN 0x08
	76
	77	#define SYS_RESET 0x01
	78	#define SYS_RESETSTAT 0x02
	79
3475187d FB	80	static void slavio_misc_update_irq(void *opaque)
	81	{
	82	MiscState *s = opaque;
	83
7debeb82	84	if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
d537cf6c PB	85	MISC_DPRINTF("Raise IRQ\n");
d537cf6c PB	86	qemu_irq_raise(s->irq);
3475187d	87	} else {
d537cf6c PB	88	MISC_DPRINTF("Lower IRQ\n");
d537cf6c PB	89	qemu_irq_lower(s->irq);
3475187d FB	90	}
	91	}
	92
	93	static void slavio_misc_reset(void *opaque)
	94	{
	95	MiscState *s = opaque;
	96
4e3b1ea1	97	// Diagnostic and system control registers not cleared in reset
3475187d FB	98	s->config = s->aux1 = s->aux2 = s->mctrl = 0;
	99	}
	100
	101	void slavio_set_power_fail(void *opaque, int power_failing)
	102	{
	103	MiscState *s = opaque;
	104
	105	MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
7debeb82 BS	106	if (power_failing && (s->config & CFG_PWRINTEN)) {
7debeb82 BS	107	s->aux2 \|= AUX2_PWRFAIL;
3475187d	108	} else {
7debeb82	109	s->aux2 &= ~AUX2_PWRFAIL;
3475187d FB	110	}
	111	slavio_misc_update_irq(s);
	112	}
	113
a8f48dcc BS	114	static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
	115	uint32_t val)
	116	{
	117	MiscState *s = opaque;
	118
	119	MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
	120	s->config = val & 0xff;
	121	slavio_misc_update_irq(s);
	122	}
	123
	124	static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
	125	{
	126	MiscState *s = opaque;
	127	uint32_t ret = 0;
	128
	129	ret = s->config;
	130	MISC_DPRINTF("Read config %2.2x\n", ret);
	131	return ret;
	132	}
	133
	134	static CPUReadMemoryFunc *slavio_cfg_mem_read[3] = {
	135	slavio_cfg_mem_readb,
	136	NULL,
	137	NULL,
	138	};
	139
	140	static CPUWriteMemoryFunc *slavio_cfg_mem_write[3] = {
	141	slavio_cfg_mem_writeb,
	142	NULL,
	143	NULL,
	144	};
	145
	146	static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
bfa30a38	147	uint32_t val)
3475187d FB	148	{
	149	MiscState *s = opaque;
	150
a8f48dcc BS	151	MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
a8f48dcc BS	152	s->diag = val & 0xff;
3475187d FB	153	}
3475187d FB	154
a8f48dcc	155	static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
3475187d FB	156	{
	157	MiscState *s = opaque;
	158	uint32_t ret = 0;
	159
a8f48dcc BS	160	ret = s->diag;
	161	MISC_DPRINTF("Read diag %2.2x\n", ret);
	162	return ret;
	163	}
	164
	165	static CPUReadMemoryFunc *slavio_diag_mem_read[3] = {
	166	slavio_diag_mem_readb,
	167	NULL,
	168	NULL,
	169	};
	170
	171	static CPUWriteMemoryFunc *slavio_diag_mem_write[3] = {
	172	slavio_diag_mem_writeb,
	173	NULL,
	174	NULL,
	175	};
	176
	177	static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
	178	uint32_t val)
	179	{
	180	MiscState *s = opaque;
	181
	182	MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
	183	s->mctrl = val & 0xff;
	184	}
	185
	186	static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
	187	{
	188	MiscState *s = opaque;
	189	uint32_t ret = 0;
	190
	191	ret = s->mctrl;
	192	MISC_DPRINTF("Read modem control %2.2x\n", ret);
3475187d FB	193	return ret;
	194	}
	195
a8f48dcc BS	196	static CPUReadMemoryFunc *slavio_mdm_mem_read[3] = {
a8f48dcc BS	197	slavio_mdm_mem_readb,
7c560456 BS	198	NULL,
7c560456 BS	199	NULL,
3475187d FB	200	};
3475187d FB	201
a8f48dcc BS	202	static CPUWriteMemoryFunc *slavio_mdm_mem_write[3] = {
a8f48dcc BS	203	slavio_mdm_mem_writeb,
7c560456 BS	204	NULL,
7c560456 BS	205	NULL,
3475187d FB	206	};
3475187d FB	207
0019ad53 BS	208	static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
	209	uint32_t val)
	210	{
	211	MiscState *s = opaque;
	212
	213	MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
2be17ebd BS	214	if (val & AUX1_TC) {
	215	// Send a pulse to floppy terminal count line
	216	if (s->fdc_tc) {
	217	qemu_irq_raise(s->fdc_tc);
	218	qemu_irq_lower(s->fdc_tc);
	219	}
	220	val &= ~AUX1_TC;
	221	}
0019ad53 BS	222	s->aux1 = val & 0xff;
	223	}
	224
	225	static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
	226	{
	227	MiscState *s = opaque;
	228	uint32_t ret = 0;
	229
	230	ret = s->aux1;
	231	MISC_DPRINTF("Read aux1 %2.2x\n", ret);
	232
	233	return ret;
	234	}
	235
	236	static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
	237	slavio_aux1_mem_readb,
	238	NULL,
	239	NULL,
	240	};
	241
	242	static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
	243	slavio_aux1_mem_writeb,
	244	NULL,
	245	NULL,
	246	};
	247
	248	static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
	249	uint32_t val)
	250	{
	251	MiscState *s = opaque;
	252
	253	val &= AUX2_PWRINTCLR \| AUX2_PWROFF;
	254	MISC_DPRINTF("Write aux2 %2.2x\n", val);
	255	val \|= s->aux2 & AUX2_PWRFAIL;
	256	if (val & AUX2_PWRINTCLR) // Clear Power Fail int
	257	val &= AUX2_PWROFF;
	258	s->aux2 = val;
	259	if (val & AUX2_PWROFF)
	260	qemu_system_shutdown_request();
	261	slavio_misc_update_irq(s);
	262	}
	263
	264	static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
	265	{
	266	MiscState *s = opaque;
	267	uint32_t ret = 0;
	268
	269	ret = s->aux2;
	270	MISC_DPRINTF("Read aux2 %2.2x\n", ret);
	271
	272	return ret;
	273	}
	274
	275	static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
	276	slavio_aux2_mem_readb,
	277	NULL,
	278	NULL,
	279	};
	280
	281	static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
	282	slavio_aux2_mem_writeb,
	283	NULL,
	284	NULL,
	285	};
286
287	static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
288	{
289	MiscState *s = opaque;
290
291	MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
6d0c293d	292	qemu_irq_raise(s->cpu_halt);
0019ad53 BS	293	}
	294
	295	static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
	296	{
	297	uint32_t ret = 0;
	298
	299	MISC_DPRINTF("Read power management %2.2x\n", ret);
	300	return ret;
	301	}
	302
	303	static CPUReadMemoryFunc *apc_mem_read[3] = {
	304	apc_mem_readb,
	305	NULL,
	306	NULL,
	307	};
	308
	309	static CPUWriteMemoryFunc *apc_mem_write[3] = {
	310	apc_mem_writeb,
	311	NULL,
	312	NULL,
	313	};
	314
bfa30a38 BS	315	static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
	316	{
	317	MiscState *s = opaque;
a8f48dcc	318	uint32_t ret = 0;
bfa30a38	319
a8f48dcc	320	switch (addr) {
bfa30a38 BS	321	case 0:
	322	ret = s->sysctrl;
	323	break;
	324	default:
	325	break;
	326	}
5626b017	327	MISC_DPRINTF("Read system control %08x\n", ret);
bfa30a38 BS	328	return ret;
	329	}
	330
	331	static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
	332	uint32_t val)
	333	{
	334	MiscState *s = opaque;
bfa30a38	335
5626b017	336	MISC_DPRINTF("Write system control %08x\n", val);
a8f48dcc	337	switch (addr) {
bfa30a38	338	case 0:
7debeb82 BS	339	if (val & SYS_RESET) {
7debeb82 BS	340	s->sysctrl = SYS_RESETSTAT;
bfa30a38 BS	341	qemu_system_reset_request();
	342	}
	343	break;
	344	default:
	345	break;
	346	}
	347	}
	348
	349	static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
7c560456 BS	350	NULL,
7c560456 BS	351	NULL,
bfa30a38 BS	352	slavio_sysctrl_mem_readl,
	353	};
	354
	355	static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
7c560456 BS	356	NULL,
7c560456 BS	357	NULL,
bfa30a38 BS	358	slavio_sysctrl_mem_writel,
	359	};
	360
7c560456	361	static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
6a3b9cc9 BS	362	{
6a3b9cc9 BS	363	MiscState *s = opaque;
a8f48dcc	364	uint32_t ret = 0;
6a3b9cc9	365
a8f48dcc	366	switch (addr) {
6a3b9cc9 BS	367	case 0:
	368	ret = s->leds;
	369	break;
	370	default:
	371	break;
	372	}
5626b017	373	MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
6a3b9cc9 BS	374	return ret;
	375	}
	376
7c560456	377	static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
6a3b9cc9 BS	378	uint32_t val)
	379	{
	380	MiscState *s = opaque;
6a3b9cc9	381
5626b017	382	MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
a8f48dcc	383	switch (addr) {
6a3b9cc9	384	case 0:
d5296cb5	385	s->leds = val;
6a3b9cc9 BS	386	break;
	387	default:
	388	break;
	389	}
	390	}
	391
	392	static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
7c560456 BS	393	NULL,
	394	slavio_led_mem_readw,
	395	NULL,
6a3b9cc9 BS	396	};
	397
	398	static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
7c560456 BS	399	NULL,
	400	slavio_led_mem_writew,
	401	NULL,
6a3b9cc9 BS	402	};
6a3b9cc9 BS	403
3475187d FB	404	static void slavio_misc_save(QEMUFile f, void opaque)
	405	{
	406	MiscState *s = opaque;
22548760	407	uint32_t tmp = 0;
bfa30a38	408	uint8_t tmp8;
3475187d	409
d537cf6c	410	qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
3475187d FB	411	qemu_put_8s(f, &s->config);
	412	qemu_put_8s(f, &s->aux1);
	413	qemu_put_8s(f, &s->aux2);
	414	qemu_put_8s(f, &s->diag);
	415	qemu_put_8s(f, &s->mctrl);
bfa30a38 BS	416	tmp8 = s->sysctrl & 0xff;
bfa30a38 BS	417	qemu_put_8s(f, &tmp8);
3475187d FB	418	}
	419
	420	static int slavio_misc_load(QEMUFile f, void opaque, int version_id)
	421	{
	422	MiscState *s = opaque;
22548760	423	uint32_t tmp;
bfa30a38	424	uint8_t tmp8;
3475187d FB	425
	426	if (version_id != 1)
	427	return -EINVAL;
	428
d537cf6c	429	qemu_get_be32s(f, &tmp);
3475187d FB	430	qemu_get_8s(f, &s->config);
	431	qemu_get_8s(f, &s->aux1);
	432	qemu_get_8s(f, &s->aux2);
	433	qemu_get_8s(f, &s->diag);
	434	qemu_get_8s(f, &s->mctrl);
bfa30a38 BS	435	qemu_get_8s(f, &tmp8);
bfa30a38 BS	436	s->sysctrl = (uint32_t)tmp8;
3475187d FB	437	return 0;
	438	}
	439
5dcb6b91	440	void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
0019ad53 BS	441	target_phys_addr_t aux1_base,
0019ad53 BS	442	target_phys_addr_t aux2_base, qemu_irq irq,
6d0c293d	443	qemu_irq cpu_halt, qemu_irq **fdc_tc)
3475187d	444	{
0019ad53	445	int io;
3475187d FB	446	MiscState *s;
	447
	448	s = qemu_mallocz(sizeof(MiscState));
	449	if (!s)
	450	return NULL;
	451
0019ad53 BS	452	if (base) {
0019ad53 BS	453	/* 8 bit registers */
a8f48dcc	454
0019ad53	455	// Slavio control
a8f48dcc BS	456	io = cpu_register_io_memory(0, slavio_cfg_mem_read,
	457	slavio_cfg_mem_write, s);
	458	cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
	459
0019ad53	460	// Diagnostics
a8f48dcc BS	461	io = cpu_register_io_memory(0, slavio_diag_mem_read,
	462	slavio_diag_mem_write, s);
	463	cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
	464
0019ad53	465	// Modem control
a8f48dcc BS	466	io = cpu_register_io_memory(0, slavio_mdm_mem_read,
	467	slavio_mdm_mem_write, s);
	468	cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
0019ad53 BS	469
	470	/* 16 bit registers */
	471	io = cpu_register_io_memory(0, slavio_led_mem_read,
	472	slavio_led_mem_write, s);
	473	/* ss600mp diag LEDs */
	474	cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);
	475
	476	/* 32 bit registers */
	477	io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
	478	slavio_sysctrl_mem_write, s);
	479	// System control
	480	cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
	481	}
	482
	483	// AUX 1 (Misc System Functions)
	484	if (aux1_base) {
	485	io = cpu_register_io_memory(0, slavio_aux1_mem_read,
	486	slavio_aux1_mem_write, s);
	487	cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
	488	}
	489
	490	// AUX 2 (Software Powerdown Control)
	491	if (aux2_base) {
	492	io = cpu_register_io_memory(0, slavio_aux2_mem_read,
	493	slavio_aux2_mem_write, s);
	494	cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
	495	}
	496
	497	// Power management (APC) XXX: not a Slavio device
	498	if (power_base) {
	499	io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
	500	cpu_register_physical_memory(power_base, MISC_SIZE, io);
	501	}
bfa30a38	502
3475187d	503	s->irq = irq;
6d0c293d	504	s->cpu_halt = cpu_halt;
2be17ebd	505	*fdc_tc = &s->fdc_tc;
3475187d	506
bfa30a38 BS	507	register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
bfa30a38 BS	508	s);
3475187d FB	509	qemu_register_reset(slavio_misc_reset, s);
3475187d FB	510	slavio_misc_reset(s);
0019ad53	511
3475187d FB	512	return s;
3475187d FB	513	}