[qemu.git] / hw / slavio_timer.c

/*
 * QEMU Sparc SLAVIO timer controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sun4m.h"
#include "qemu/timer.h"
#include "ptimer.h"
#include "sysbus.h"
#include "trace.h"

/*
 * Registers of hardware timer in sun4m.
 *
 * This is the timer/counter part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
 * are zero. Bit 31 is 1 when count has been reached.
 *
 * Per-CPU timers interrupt local CPU, system timer uses normal
 * interrupt routing.
 *
 */

#define MAX_CPUS 16

typedef struct CPUTimerState {
    qemu_irq irq;
    ptimer_state *timer;
    uint32_t count, counthigh, reached;
    /* processor only */
    uint32_t running;
    uint64_t limit;
} CPUTimerState;

typedef struct SLAVIO_TIMERState {
    SysBusDevice busdev;
    uint32_t num_cpus;
    uint32_t cputimer_mode;
    CPUTimerState cputimer[MAX_CPUS + 1];
} SLAVIO_TIMERState;

typedef struct TimerContext {
    MemoryRegion iomem;
    SLAVIO_TIMERState *s;
    unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
} TimerContext;

#define SYS_TIMER_SIZE 0x14
#define CPU_TIMER_SIZE 0x10

#define TIMER_LIMIT         0
#define TIMER_COUNTER       1
#define TIMER_COUNTER_NORST 2
#define TIMER_STATUS        3
#define TIMER_MODE          4

#define TIMER_COUNT_MASK32 0xfffffe00
#define TIMER_LIMIT_MASK32 0x7fffffff
#define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
#define TIMER_MAX_COUNT32  0x7ffffe00ULL
#define TIMER_REACHED      0x80000000
#define TIMER_PERIOD       500ULL // 500ns
#define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
#define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)

static int slavio_timer_is_user(TimerContext *tc)
{
    SLAVIO_TIMERState *s = tc->s;
    unsigned int timer_index = tc->timer_index;

    return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
}

// Update count, set irq, update expire_time
// Convert from ptimer countdown units
static void slavio_timer_get_out(CPUTimerState *t)
{
    uint64_t count, limit;

    if (t->limit == 0) { /* free-run system or processor counter */
        limit = TIMER_MAX_COUNT32;
    } else {
        limit = t->limit;
    }
    count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));

    trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
    t->count = count & TIMER_COUNT_MASK32;
    t->counthigh = count >> 32;
}

// timer callback
static void slavio_timer_irq(void *opaque)
{
    TimerContext *tc = opaque;
    SLAVIO_TIMERState *s = tc->s;
    CPUTimerState *t = &s->cputimer[tc->timer_index];

    slavio_timer_get_out(t);
    trace_slavio_timer_irq(t->counthigh, t->count);
    /* if limit is 0 (free-run), there will be no match */
    if (t->limit != 0) {
        t->reached = TIMER_REACHED;
    }
    /* there is no interrupt if user timer or free-run */
    if (!slavio_timer_is_user(tc) && t->limit != 0) {
        qemu_irq_raise(t->irq);
    }
}

static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
                                       unsigned size)
{
    TimerContext *tc = opaque;
    SLAVIO_TIMERState *s = tc->s;
    uint32_t saddr, ret;
    unsigned int timer_index = tc->timer_index;
    CPUTimerState *t = &s->cputimer[timer_index];

    saddr = addr >> 2;
    switch (saddr) {
    case TIMER_LIMIT:
        // read limit (system counter mode) or read most signifying
        // part of counter (user mode)
        if (slavio_timer_is_user(tc)) {
            // read user timer MSW
            slavio_timer_get_out(t);
            ret = t->counthigh | t->reached;
        } else {
            // read limit
            // clear irq
            qemu_irq_lower(t->irq);
            t->reached = 0;
            ret = t->limit & TIMER_LIMIT_MASK32;
        }
        break;
    case TIMER_COUNTER:
        // read counter and reached bit (system mode) or read lsbits
        // of counter (user mode)
        slavio_timer_get_out(t);
        if (slavio_timer_is_user(tc)) { // read user timer LSW
            ret = t->count & TIMER_MAX_COUNT64;
        } else { // read limit
            ret = (t->count & TIMER_MAX_COUNT32) |
                t->reached;
        }
        break;
    case TIMER_STATUS:
        // only available in processor counter/timer
        // read start/stop status
        if (timer_index > 0) {
            ret = t->running;
        } else {
            ret = 0;
        }
        break;
    case TIMER_MODE:
        // only available in system counter
        // read user/system mode
        ret = s->cputimer_mode;
        break;
    default:
        trace_slavio_timer_mem_readl_invalid(addr);
        ret = 0;
        break;
    }
    trace_slavio_timer_mem_readl(addr, ret);
    return ret;
}

static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
                                    uint64_t val, unsigned size)
{
    TimerContext *tc = opaque;
    SLAVIO_TIMERState *s = tc->s;
    uint32_t saddr;
    unsigned int timer_index = tc->timer_index;
    CPUTimerState *t = &s->cputimer[timer_index];

    trace_slavio_timer_mem_writel(addr, val);
    saddr = addr >> 2;
    switch (saddr) {
    case TIMER_LIMIT:
        if (slavio_timer_is_user(tc)) {
            uint64_t count;

            // set user counter MSW, reset counter
            t->limit = TIMER_MAX_COUNT64;
            t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
            t->reached = 0;
            count = ((uint64_t)t->counthigh << 32) | t->count;
            trace_slavio_timer_mem_writel_limit(timer_index, count);
            ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
        } else {
            // set limit, reset counter
            qemu_irq_lower(t->irq);
            t->limit = val & TIMER_MAX_COUNT32;
            if (t->timer) {
                if (t->limit == 0) { /* free-run */
                    ptimer_set_limit(t->timer,
                                     LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
                } else {
                    ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
                }
            }
        }
        break;
    case TIMER_COUNTER:
        if (slavio_timer_is_user(tc)) {
            uint64_t count;

            // set user counter LSW, reset counter
            t->limit = TIMER_MAX_COUNT64;
            t->count = val & TIMER_MAX_COUNT64;
            t->reached = 0;
            count = ((uint64_t)t->counthigh) << 32 | t->count;
            trace_slavio_timer_mem_writel_limit(timer_index, count);
            ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
        } else {
            trace_slavio_timer_mem_writel_counter_invalid();
        }
        break;
    case TIMER_COUNTER_NORST:
        // set limit without resetting counter
        t->limit = val & TIMER_MAX_COUNT32;
        if (t->limit == 0) { /* free-run */
            ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
        } else {
            ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
        }
        break;
    case TIMER_STATUS:
        if (slavio_timer_is_user(tc)) {
            // start/stop user counter
            if ((val & 1) && !t->running) {
                trace_slavio_timer_mem_writel_status_start(timer_index);
                ptimer_run(t->timer, 0);
                t->running = 1;
            } else if (!(val & 1) && t->running) {
                trace_slavio_timer_mem_writel_status_stop(timer_index);
                ptimer_stop(t->timer);
                t->running = 0;
            }
        }
        break;
    case TIMER_MODE:
        if (timer_index == 0) {
            unsigned int i;

            for (i = 0; i < s->num_cpus; i++) {
                unsigned int processor = 1 << i;
                CPUTimerState *curr_timer = &s->cputimer[i + 1];

                // check for a change in timer mode for this processor
                if ((val & processor) != (s->cputimer_mode & processor)) {
                    if (val & processor) { // counter -> user timer
                        qemu_irq_lower(curr_timer->irq);
                        // counters are always running
                        ptimer_stop(curr_timer->timer);
                        curr_timer->running = 0;
                        // user timer limit is always the same
                        curr_timer->limit = TIMER_MAX_COUNT64;
                        ptimer_set_limit(curr_timer->timer,
                                         LIMIT_TO_PERIODS(curr_timer->limit),
                                         1);
                        // set this processors user timer bit in config
                        // register
                        s->cputimer_mode |= processor;
                        trace_slavio_timer_mem_writel_mode_user(timer_index);
                    } else { // user timer -> counter
                        // stop the user timer if it is running
                        if (curr_timer->running) {
                            ptimer_stop(curr_timer->timer);
                        }
                        // start the counter
                        ptimer_run(curr_timer->timer, 0);
                        curr_timer->running = 1;
                        // clear this processors user timer bit in config
                        // register
                        s->cputimer_mode &= ~processor;
                        trace_slavio_timer_mem_writel_mode_counter(timer_index);
                    }
                }
            }
        } else {
            trace_slavio_timer_mem_writel_mode_invalid();
        }
        break;
    default:
        trace_slavio_timer_mem_writel_invalid(addr);
        break;
    }
}

static const MemoryRegionOps slavio_timer_mem_ops = {
    .read = slavio_timer_mem_readl,
    .write = slavio_timer_mem_writel,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static const VMStateDescription vmstate_timer = {
    .name ="timer",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(limit, CPUTimerState),
        VMSTATE_UINT32(count, CPUTimerState),
        VMSTATE_UINT32(counthigh, CPUTimerState),
        VMSTATE_UINT32(reached, CPUTimerState),
        VMSTATE_UINT32(running, CPUTimerState),
        VMSTATE_PTIMER(timer, CPUTimerState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_slavio_timer = {
    .name ="slavio_timer",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .fields      = (VMStateField []) {
        VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
                             vmstate_timer, CPUTimerState),
        VMSTATE_END_OF_LIST()
    }
};

static void slavio_timer_reset(DeviceState *d)
{
    SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev);
    unsigned int i;
    CPUTimerState *curr_timer;

    for (i = 0; i <= MAX_CPUS; i++) {
        curr_timer = &s->cputimer[i];
        curr_timer->limit = 0;
        curr_timer->count = 0;
        curr_timer->reached = 0;
        if (i <= s->num_cpus) {
            ptimer_set_limit(curr_timer->timer,
                             LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
            ptimer_run(curr_timer->timer, 0);
            curr_timer->running = 1;
        }
    }
    s->cputimer_mode = 0;
}

static int slavio_timer_init1(SysBusDevice *dev)
{
    SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
    QEMUBH *bh;
    unsigned int i;
    TimerContext *tc;

    for (i = 0; i <= MAX_CPUS; i++) {
        uint64_t size;
        char timer_name[20];

        tc = g_malloc0(sizeof(TimerContext));
        tc->s = s;
        tc->timer_index = i;

        bh = qemu_bh_new(slavio_timer_irq, tc);
        s->cputimer[i].timer = ptimer_init(bh);
        ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);

        size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
        snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
        memory_region_init_io(&tc->iomem, &slavio_timer_mem_ops, tc,
                              timer_name, size);
        sysbus_init_mmio(dev, &tc->iomem);

        sysbus_init_irq(dev, &s->cputimer[i].irq);
    }

    return 0;
}

static Property slavio_timer_properties[] = {
    DEFINE_PROP_UINT32("num_cpus",  SLAVIO_TIMERState, num_cpus,  0),
    DEFINE_PROP_END_OF_LIST(),
};

static void slavio_timer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = slavio_timer_init1;
    dc->reset = slavio_timer_reset;
    dc->vmsd = &vmstate_slavio_timer;
    dc->props = slavio_timer_properties;
}

static const TypeInfo slavio_timer_info = {
    .name          = "slavio_timer",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(SLAVIO_TIMERState),
    .class_init    = slavio_timer_class_init,
};

static void slavio_timer_register_types(void)
{
    type_register_static(&slavio_timer_info);
}

type_init(slavio_timer_register_types)
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO timer controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
e80cfcfc FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
c70c59ee	24
87ecb68b	25	#include "sun4m.h"
1de7afc9	26	#include "qemu/timer.h"
49d4d9b6	27	#include "ptimer.h"
c70c59ee	28	#include "sysbus.h"
97bf4851	29	#include "trace.h"
66321a11	30
e80cfcfc FB	31	/*
	32	* Registers of hardware timer in sun4m.
	33	*
	34	* This is the timer/counter part of chip STP2001 (Slave I/O), also
	35	* produced as NCR89C105. See
	36	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
5fafdf24	37	*
e80cfcfc FB	38	* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
	39	* are zero. Bit 31 is 1 when count has been reached.
	40	*
ba3c64fb FB	41	* Per-CPU timers interrupt local CPU, system timer uses normal
	42	* interrupt routing.
	43	*
e80cfcfc FB	44	*/
e80cfcfc FB	45
81732d19 BS	46	#define MAX_CPUS 16
81732d19 BS	47
7204ff9c	48	typedef struct CPUTimerState {
d7edfd27	49	qemu_irq irq;
8d05ea8a BS	50	ptimer_state *timer;
8d05ea8a BS	51	uint32_t count, counthigh, reached;
f90074f4	52	/* processor only */
22548760	53	uint32_t running;
f90074f4	54	uint64_t limit;
7204ff9c BS	55	} CPUTimerState;
	56
	57	typedef struct SLAVIO_TIMERState {
	58	SysBusDevice busdev;
	59	uint32_t num_cpus;
7204ff9c	60	uint32_t cputimer_mode;
f90074f4	61	CPUTimerState cputimer[MAX_CPUS + 1];
e80cfcfc FB	62	} SLAVIO_TIMERState;
e80cfcfc FB	63
7204ff9c	64	typedef struct TimerContext {
a3d12d07	65	MemoryRegion iomem;
7204ff9c BS	66	SLAVIO_TIMERState *s;
	67	unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
	68	} TimerContext;
	69
115646b6	70	#define SYS_TIMER_SIZE 0x14
81732d19	71	#define CPU_TIMER_SIZE 0x10
e80cfcfc	72
d2c38b24 BS	73	#define TIMER_LIMIT 0
	74	#define TIMER_COUNTER 1
	75	#define TIMER_COUNTER_NORST 2
	76	#define TIMER_STATUS 3
	77	#define TIMER_MODE 4
	78
	79	#define TIMER_COUNT_MASK32 0xfffffe00
	80	#define TIMER_LIMIT_MASK32 0x7fffffff
	81	#define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
	82	#define TIMER_MAX_COUNT32 0x7ffffe00ULL
	83	#define TIMER_REACHED 0x80000000
	84	#define TIMER_PERIOD 500ULL // 500ns
68fb89a2 BS	85	#define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
68fb89a2 BS	86	#define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
d2c38b24	87
7204ff9c	88	static int slavio_timer_is_user(TimerContext *tc)
115646b6	89	{
7204ff9c BS	90	SLAVIO_TIMERState *s = tc->s;
	91	unsigned int timer_index = tc->timer_index;
	92
	93	return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
115646b6 BS	94	}
115646b6 BS	95
e80cfcfc	96	// Update count, set irq, update expire_time
8d05ea8a	97	// Convert from ptimer countdown units
7204ff9c	98	static void slavio_timer_get_out(CPUTimerState *t)
e80cfcfc	99	{
bd7e2875	100	uint64_t count, limit;
e80cfcfc	101
7204ff9c	102	if (t->limit == 0) { /* free-run system or processor counter */
bd7e2875	103	limit = TIMER_MAX_COUNT32;
7204ff9c BS	104	} else {
	105	limit = t->limit;
	106	}
9ebec28b BS	107	count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
9ebec28b BS	108
97bf4851	109	trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
7204ff9c BS	110	t->count = count & TIMER_COUNT_MASK32;
7204ff9c BS	111	t->counthigh = count >> 32;
e80cfcfc FB	112	}
	113
	114	// timer callback
	115	static void slavio_timer_irq(void *opaque)
	116	{
7204ff9c BS	117	TimerContext *tc = opaque;
	118	SLAVIO_TIMERState *s = tc->s;
	119	CPUTimerState *t = &s->cputimer[tc->timer_index];
	120
	121	slavio_timer_get_out(t);
97bf4851	122	trace_slavio_timer_irq(t->counthigh, t->count);
68fb89a2 BS	123	/* if limit is 0 (free-run), there will be no match */
	124	if (t->limit != 0) {
	125	t->reached = TIMER_REACHED;
	126	}
452efba6 BS	127	/* there is no interrupt if user timer or free-run */
452efba6 BS	128	if (!slavio_timer_is_user(tc) && t->limit != 0) {
7204ff9c BS	129	qemu_irq_raise(t->irq);
7204ff9c BS	130	}
e80cfcfc FB	131	}
e80cfcfc FB	132
a8170e5e	133	static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
a3d12d07	134	unsigned size)
e80cfcfc	135	{
7204ff9c BS	136	TimerContext *tc = opaque;
7204ff9c BS	137	SLAVIO_TIMERState *s = tc->s;
8d05ea8a	138	uint32_t saddr, ret;
7204ff9c BS	139	unsigned int timer_index = tc->timer_index;
7204ff9c BS	140	CPUTimerState *t = &s->cputimer[timer_index];
e80cfcfc	141
e64d7d59	142	saddr = addr >> 2;
e80cfcfc	143	switch (saddr) {
d2c38b24	144	case TIMER_LIMIT:
f930d07e BS	145	// read limit (system counter mode) or read most signifying
f930d07e BS	146	// part of counter (user mode)
7204ff9c	147	if (slavio_timer_is_user(tc)) {
115646b6	148	// read user timer MSW
7204ff9c BS	149	slavio_timer_get_out(t);
7204ff9c BS	150	ret = t->counthigh \| t->reached;
115646b6 BS	151	} else {
115646b6 BS	152	// read limit
f930d07e	153	// clear irq
7204ff9c BS	154	qemu_irq_lower(t->irq);
	155	t->reached = 0;
	156	ret = t->limit & TIMER_LIMIT_MASK32;
f930d07e	157	}
8d05ea8a	158	break;
d2c38b24	159	case TIMER_COUNTER:
f930d07e BS	160	// read counter and reached bit (system mode) or read lsbits
f930d07e BS	161	// of counter (user mode)
7204ff9c BS	162	slavio_timer_get_out(t);
	163	if (slavio_timer_is_user(tc)) { // read user timer LSW
	164	ret = t->count & TIMER_MAX_COUNT64;
	165	} else { // read limit
	166	ret = (t->count & TIMER_MAX_COUNT32) \|
	167	t->reached;
	168	}
8d05ea8a	169	break;
d2c38b24	170	case TIMER_STATUS:
115646b6	171	// only available in processor counter/timer
f930d07e	172	// read start/stop status
7204ff9c BS	173	if (timer_index > 0) {
	174	ret = t->running;
	175	} else {
	176	ret = 0;
	177	}
8d05ea8a	178	break;
d2c38b24	179	case TIMER_MODE:
115646b6	180	// only available in system counter
f930d07e	181	// read user/system mode
7204ff9c	182	ret = s->cputimer_mode;
8d05ea8a	183	break;
e80cfcfc	184	default:
97bf4851	185	trace_slavio_timer_mem_readl_invalid(addr);
8d05ea8a BS	186	ret = 0;
8d05ea8a BS	187	break;
e80cfcfc	188	}
97bf4851	189	trace_slavio_timer_mem_readl(addr, ret);
8d05ea8a	190	return ret;
e80cfcfc FB	191	}
e80cfcfc FB	192
a8170e5e	193	static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
a3d12d07	194	uint64_t val, unsigned size)
e80cfcfc	195	{
7204ff9c BS	196	TimerContext *tc = opaque;
7204ff9c BS	197	SLAVIO_TIMERState *s = tc->s;
e80cfcfc	198	uint32_t saddr;
7204ff9c BS	199	unsigned int timer_index = tc->timer_index;
7204ff9c BS	200	CPUTimerState *t = &s->cputimer[timer_index];
e80cfcfc	201
97bf4851	202	trace_slavio_timer_mem_writel(addr, val);
e64d7d59	203	saddr = addr >> 2;
e80cfcfc	204	switch (saddr) {
d2c38b24	205	case TIMER_LIMIT:
7204ff9c	206	if (slavio_timer_is_user(tc)) {
e1cb9502 BS	207	uint64_t count;
e1cb9502 BS	208
115646b6	209	// set user counter MSW, reset counter
7204ff9c BS	210	t->limit = TIMER_MAX_COUNT64;
	211	t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
	212	t->reached = 0;
	213	count = ((uint64_t)t->counthigh << 32) \| t->count;
97bf4851	214	trace_slavio_timer_mem_writel_limit(timer_index, count);
9ebec28b	215	ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
115646b6 BS	216	} else {
115646b6 BS	217	// set limit, reset counter
7204ff9c BS	218	qemu_irq_lower(t->irq);
	219	t->limit = val & TIMER_MAX_COUNT32;
	220	if (t->timer) {
	221	if (t->limit == 0) { /* free-run */
	222	ptimer_set_limit(t->timer,
77f193da	223	LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
7204ff9c BS	224	} else {
	225	ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
	226	}
85e3023e	227	}
81732d19	228	}
115646b6	229	break;
d2c38b24	230	case TIMER_COUNTER:
7204ff9c	231	if (slavio_timer_is_user(tc)) {
e1cb9502 BS	232	uint64_t count;
e1cb9502 BS	233
115646b6	234	// set user counter LSW, reset counter
7204ff9c BS	235	t->limit = TIMER_MAX_COUNT64;
	236	t->count = val & TIMER_MAX_COUNT64;
	237	t->reached = 0;
	238	count = ((uint64_t)t->counthigh) << 32 \| t->count;
97bf4851	239	trace_slavio_timer_mem_writel_limit(timer_index, count);
9ebec28b	240	ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
97bf4851 BS	241	} else {
	242	trace_slavio_timer_mem_writel_counter_invalid();
	243	}
115646b6	244	break;
d2c38b24	245	case TIMER_COUNTER_NORST:
f930d07e	246	// set limit without resetting counter
7204ff9c	247	t->limit = val & TIMER_MAX_COUNT32;
9ebec28b BS	248	if (t->limit == 0) { /* free-run */
	249	ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
	250	} else {
	251	ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
85e3023e	252	}
f930d07e	253	break;
d2c38b24	254	case TIMER_STATUS:
7204ff9c	255	if (slavio_timer_is_user(tc)) {
115646b6	256	// start/stop user counter
7204ff9c	257	if ((val & 1) && !t->running) {
97bf4851	258	trace_slavio_timer_mem_writel_status_start(timer_index);
9ebec28b	259	ptimer_run(t->timer, 0);
7204ff9c BS	260	t->running = 1;
7204ff9c BS	261	} else if (!(val & 1) && t->running) {
97bf4851	262	trace_slavio_timer_mem_writel_status_stop(timer_index);
9ebec28b	263	ptimer_stop(t->timer);
7204ff9c	264	t->running = 0;
f930d07e BS	265	}
	266	}
	267	break;
d2c38b24	268	case TIMER_MODE:
7204ff9c	269	if (timer_index == 0) {
81732d19 BS	270	unsigned int i;
81732d19 BS	271
7204ff9c	272	for (i = 0; i < s->num_cpus; i++) {
67e42751	273	unsigned int processor = 1 << i;
7204ff9c	274	CPUTimerState *curr_timer = &s->cputimer[i + 1];
67e42751 BS	275
67e42751 BS	276	// check for a change in timer mode for this processor
7204ff9c	277	if ((val & processor) != (s->cputimer_mode & processor)) {
67e42751	278	if (val & processor) { // counter -> user timer
7204ff9c	279	qemu_irq_lower(curr_timer->irq);
67e42751	280	// counters are always running
7204ff9c BS	281	ptimer_stop(curr_timer->timer);
7204ff9c BS	282	curr_timer->running = 0;
67e42751	283	// user timer limit is always the same
7204ff9c BS	284	curr_timer->limit = TIMER_MAX_COUNT64;
	285	ptimer_set_limit(curr_timer->timer,
	286	LIMIT_TO_PERIODS(curr_timer->limit),
77f193da	287	1);
67e42751 BS	288	// set this processors user timer bit in config
67e42751 BS	289	// register
7204ff9c	290	s->cputimer_mode \|= processor;
97bf4851	291	trace_slavio_timer_mem_writel_mode_user(timer_index);
67e42751 BS	292	} else { // user timer -> counter
67e42751 BS	293	// stop the user timer if it is running
7204ff9c BS	294	if (curr_timer->running) {
	295	ptimer_stop(curr_timer->timer);
	296	}
67e42751	297	// start the counter
7204ff9c BS	298	ptimer_run(curr_timer->timer, 0);
7204ff9c BS	299	curr_timer->running = 1;
67e42751 BS	300	// clear this processors user timer bit in config
67e42751 BS	301	// register
7204ff9c	302	s->cputimer_mode &= ~processor;
97bf4851	303	trace_slavio_timer_mem_writel_mode_counter(timer_index);
67e42751	304	}
115646b6	305	}
81732d19	306	}
7204ff9c	307	} else {
97bf4851	308	trace_slavio_timer_mem_writel_mode_invalid();
7204ff9c	309	}
f930d07e	310	break;
e80cfcfc	311	default:
97bf4851	312	trace_slavio_timer_mem_writel_invalid(addr);
f930d07e	313	break;
e80cfcfc FB	314	}
	315	}
	316
a3d12d07 BC	317	static const MemoryRegionOps slavio_timer_mem_ops = {
	318	.read = slavio_timer_mem_readl,
	319	.write = slavio_timer_mem_writel,
	320	.endianness = DEVICE_NATIVE_ENDIAN,
	321	.valid = {
	322	.min_access_size = 4,
	323	.max_access_size = 4,
	324	},
e80cfcfc FB	325	};
e80cfcfc FB	326
f4b19cd0 BS	327	static const VMStateDescription vmstate_timer = {
	328	.name ="timer",
	329	.version_id = 3,
	330	.minimum_version_id = 3,
	331	.minimum_version_id_old = 3,
	332	.fields = (VMStateField []) {
	333	VMSTATE_UINT64(limit, CPUTimerState),
	334	VMSTATE_UINT32(count, CPUTimerState),
	335	VMSTATE_UINT32(counthigh, CPUTimerState),
	336	VMSTATE_UINT32(reached, CPUTimerState),
	337	VMSTATE_UINT32(running, CPUTimerState),
	338	VMSTATE_PTIMER(timer, CPUTimerState),
	339	VMSTATE_END_OF_LIST()
7204ff9c	340	}
f4b19cd0	341	};
e80cfcfc	342
f4b19cd0 BS	343	static const VMStateDescription vmstate_slavio_timer = {
	344	.name ="slavio_timer",
	345	.version_id = 3,
	346	.minimum_version_id = 3,
	347	.minimum_version_id_old = 3,
	348	.fields = (VMStateField []) {
	349	VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
	350	vmstate_timer, CPUTimerState),
	351	VMSTATE_END_OF_LIST()
7204ff9c	352	}
f4b19cd0	353	};
e80cfcfc	354
0e0bfeea	355	static void slavio_timer_reset(DeviceState *d)
e80cfcfc	356	{
0e0bfeea	357	SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev);
7204ff9c BS	358	unsigned int i;
	359	CPUTimerState *curr_timer;
	360
	361	for (i = 0; i <= MAX_CPUS; i++) {
	362	curr_timer = &s->cputimer[i];
	363	curr_timer->limit = 0;
	364	curr_timer->count = 0;
	365	curr_timer->reached = 0;
5933e8a9	366	if (i <= s->num_cpus) {
7204ff9c BS	367	ptimer_set_limit(curr_timer->timer,
	368	LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
	369	ptimer_run(curr_timer->timer, 0);
5933e8a9	370	curr_timer->running = 1;
7204ff9c	371	}
85e3023e	372	}
7204ff9c	373	s->cputimer_mode = 0;
e80cfcfc FB	374	}
e80cfcfc FB	375
81a322d4	376	static int slavio_timer_init1(SysBusDevice *dev)
c70c59ee	377	{
c70c59ee	378	SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
8d05ea8a	379	QEMUBH *bh;
7204ff9c BS	380	unsigned int i;
7204ff9c BS	381	TimerContext *tc;
e80cfcfc	382
7204ff9c	383	for (i = 0; i <= MAX_CPUS; i++) {
a3d12d07 BC	384	uint64_t size;
	385	char timer_name[20];
	386
7267c094	387	tc = g_malloc0(sizeof(TimerContext));
7204ff9c BS	388	tc->s = s;
7204ff9c BS	389	tc->timer_index = i;
c70c59ee	390
7204ff9c BS	391	bh = qemu_bh_new(slavio_timer_irq, tc);
	392	s->cputimer[i].timer = ptimer_init(bh);
	393	ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
e80cfcfc	394
a3d12d07 BC	395	size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
	396	snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
	397	memory_region_init_io(&tc->iomem, &slavio_timer_mem_ops, tc,
	398	timer_name, size);
750ecd44	399	sysbus_init_mmio(dev, &tc->iomem);
7204ff9c BS	400
7204ff9c BS	401	sysbus_init_irq(dev, &s->cputimer[i].irq);
c70c59ee BS	402	}
c70c59ee BS	403
81a322d4	404	return 0;
81732d19 BS	405	}
81732d19 BS	406
999e12bb AL	407	static Property slavio_timer_properties[] = {
	408	DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0),
	409	DEFINE_PROP_END_OF_LIST(),
	410	};
	411
	412	static void slavio_timer_class_init(ObjectClass klass, void data)
	413	{
39bffca2	414	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	415	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	416
	417	k->init = slavio_timer_init1;
39bffca2 AL	418	dc->reset = slavio_timer_reset;
	419	dc->vmsd = &vmstate_slavio_timer;
	420	dc->props = slavio_timer_properties;
999e12bb AL	421	}
999e12bb AL	422
8c43a6f0	423	static const TypeInfo slavio_timer_info = {
39bffca2 AL	424	.name = "slavio_timer",
	425	.parent = TYPE_SYS_BUS_DEVICE,
	426	.instance_size = sizeof(SLAVIO_TIMERState),
	427	.class_init = slavio_timer_class_init,
c70c59ee BS	428	};
c70c59ee BS	429
83f7d43a	430	static void slavio_timer_register_types(void)
c70c59ee	431	{
39bffca2	432	type_register_static(&slavio_timer_info);
c70c59ee BS	433	}
c70c59ee BS	434
83f7d43a	435	type_init(slavio_timer_register_types)