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e80cfcfc FB |
1 | /* |
2 | * QEMU Sparc SLAVIO timer controller emulation | |
3 | * | |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
e80cfcfc FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
c70c59ee | 24 | |
87ecb68b PB |
25 | #include "sun4m.h" |
26 | #include "qemu-timer.h" | |
c70c59ee | 27 | #include "sysbus.h" |
e80cfcfc FB |
28 | |
29 | //#define DEBUG_TIMER | |
30 | ||
66321a11 | 31 | #ifdef DEBUG_TIMER |
001faf32 BS |
32 | #define DPRINTF(fmt, ...) \ |
33 | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) | |
66321a11 | 34 | #else |
001faf32 | 35 | #define DPRINTF(fmt, ...) do {} while (0) |
66321a11 FB |
36 | #endif |
37 | ||
e80cfcfc FB |
38 | /* |
39 | * Registers of hardware timer in sun4m. | |
40 | * | |
41 | * This is the timer/counter part of chip STP2001 (Slave I/O), also | |
42 | * produced as NCR89C105. See | |
43 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt | |
5fafdf24 | 44 | * |
e80cfcfc FB |
45 | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0 |
46 | * are zero. Bit 31 is 1 when count has been reached. | |
47 | * | |
ba3c64fb FB |
48 | * Per-CPU timers interrupt local CPU, system timer uses normal |
49 | * interrupt routing. | |
50 | * | |
e80cfcfc FB |
51 | */ |
52 | ||
81732d19 BS |
53 | #define MAX_CPUS 16 |
54 | ||
7204ff9c | 55 | typedef struct CPUTimerState { |
d7edfd27 | 56 | qemu_irq irq; |
8d05ea8a BS |
57 | ptimer_state *timer; |
58 | uint32_t count, counthigh, reached; | |
59 | uint64_t limit; | |
115646b6 | 60 | // processor only |
22548760 | 61 | uint32_t running; |
7204ff9c BS |
62 | } CPUTimerState; |
63 | ||
64 | typedef struct SLAVIO_TIMERState { | |
65 | SysBusDevice busdev; | |
66 | uint32_t num_cpus; | |
67 | CPUTimerState cputimer[MAX_CPUS + 1]; | |
68 | uint32_t cputimer_mode; | |
e80cfcfc FB |
69 | } SLAVIO_TIMERState; |
70 | ||
7204ff9c BS |
71 | typedef struct TimerContext { |
72 | SLAVIO_TIMERState *s; | |
73 | unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ | |
74 | } TimerContext; | |
75 | ||
115646b6 | 76 | #define SYS_TIMER_SIZE 0x14 |
81732d19 | 77 | #define CPU_TIMER_SIZE 0x10 |
e80cfcfc | 78 | |
d2c38b24 BS |
79 | #define TIMER_LIMIT 0 |
80 | #define TIMER_COUNTER 1 | |
81 | #define TIMER_COUNTER_NORST 2 | |
82 | #define TIMER_STATUS 3 | |
83 | #define TIMER_MODE 4 | |
84 | ||
85 | #define TIMER_COUNT_MASK32 0xfffffe00 | |
86 | #define TIMER_LIMIT_MASK32 0x7fffffff | |
87 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL | |
88 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL | |
89 | #define TIMER_REACHED 0x80000000 | |
90 | #define TIMER_PERIOD 500ULL // 500ns | |
91 | #define LIMIT_TO_PERIODS(l) ((l) >> 9) | |
92 | #define PERIODS_TO_LIMIT(l) ((l) << 9) | |
93 | ||
7204ff9c | 94 | static int slavio_timer_is_user(TimerContext *tc) |
115646b6 | 95 | { |
7204ff9c BS |
96 | SLAVIO_TIMERState *s = tc->s; |
97 | unsigned int timer_index = tc->timer_index; | |
98 | ||
99 | return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); | |
115646b6 BS |
100 | } |
101 | ||
e80cfcfc | 102 | // Update count, set irq, update expire_time |
8d05ea8a | 103 | // Convert from ptimer countdown units |
7204ff9c | 104 | static void slavio_timer_get_out(CPUTimerState *t) |
e80cfcfc | 105 | { |
bd7e2875 | 106 | uint64_t count, limit; |
e80cfcfc | 107 | |
7204ff9c | 108 | if (t->limit == 0) { /* free-run system or processor counter */ |
bd7e2875 | 109 | limit = TIMER_MAX_COUNT32; |
7204ff9c BS |
110 | } else { |
111 | limit = t->limit; | |
112 | } | |
9ebec28b BS |
113 | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
114 | ||
7204ff9c BS |
115 | DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh, |
116 | t->count); | |
117 | t->count = count & TIMER_COUNT_MASK32; | |
118 | t->counthigh = count >> 32; | |
e80cfcfc FB |
119 | } |
120 | ||
121 | // timer callback | |
122 | static void slavio_timer_irq(void *opaque) | |
123 | { | |
7204ff9c BS |
124 | TimerContext *tc = opaque; |
125 | SLAVIO_TIMERState *s = tc->s; | |
126 | CPUTimerState *t = &s->cputimer[tc->timer_index]; | |
127 | ||
128 | slavio_timer_get_out(t); | |
129 | DPRINTF("callback: count %x%08x\n", t->counthigh, t->count); | |
130 | t->reached = TIMER_REACHED; | |
452efba6 BS |
131 | /* there is no interrupt if user timer or free-run */ |
132 | if (!slavio_timer_is_user(tc) && t->limit != 0) { | |
7204ff9c BS |
133 | qemu_irq_raise(t->irq); |
134 | } | |
e80cfcfc FB |
135 | } |
136 | ||
c227f099 | 137 | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
e80cfcfc | 138 | { |
7204ff9c BS |
139 | TimerContext *tc = opaque; |
140 | SLAVIO_TIMERState *s = tc->s; | |
8d05ea8a | 141 | uint32_t saddr, ret; |
7204ff9c BS |
142 | unsigned int timer_index = tc->timer_index; |
143 | CPUTimerState *t = &s->cputimer[timer_index]; | |
e80cfcfc | 144 | |
e64d7d59 | 145 | saddr = addr >> 2; |
e80cfcfc | 146 | switch (saddr) { |
d2c38b24 | 147 | case TIMER_LIMIT: |
f930d07e BS |
148 | // read limit (system counter mode) or read most signifying |
149 | // part of counter (user mode) | |
7204ff9c | 150 | if (slavio_timer_is_user(tc)) { |
115646b6 | 151 | // read user timer MSW |
7204ff9c BS |
152 | slavio_timer_get_out(t); |
153 | ret = t->counthigh | t->reached; | |
115646b6 BS |
154 | } else { |
155 | // read limit | |
f930d07e | 156 | // clear irq |
7204ff9c BS |
157 | qemu_irq_lower(t->irq); |
158 | t->reached = 0; | |
159 | ret = t->limit & TIMER_LIMIT_MASK32; | |
f930d07e | 160 | } |
8d05ea8a | 161 | break; |
d2c38b24 | 162 | case TIMER_COUNTER: |
f930d07e BS |
163 | // read counter and reached bit (system mode) or read lsbits |
164 | // of counter (user mode) | |
7204ff9c BS |
165 | slavio_timer_get_out(t); |
166 | if (slavio_timer_is_user(tc)) { // read user timer LSW | |
167 | ret = t->count & TIMER_MAX_COUNT64; | |
168 | } else { // read limit | |
169 | ret = (t->count & TIMER_MAX_COUNT32) | | |
170 | t->reached; | |
171 | } | |
8d05ea8a | 172 | break; |
d2c38b24 | 173 | case TIMER_STATUS: |
115646b6 | 174 | // only available in processor counter/timer |
f930d07e | 175 | // read start/stop status |
7204ff9c BS |
176 | if (timer_index > 0) { |
177 | ret = t->running; | |
178 | } else { | |
179 | ret = 0; | |
180 | } | |
8d05ea8a | 181 | break; |
d2c38b24 | 182 | case TIMER_MODE: |
115646b6 | 183 | // only available in system counter |
f930d07e | 184 | // read user/system mode |
7204ff9c | 185 | ret = s->cputimer_mode; |
8d05ea8a | 186 | break; |
e80cfcfc | 187 | default: |
115646b6 | 188 | DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr); |
8d05ea8a BS |
189 | ret = 0; |
190 | break; | |
e80cfcfc | 191 | } |
8d05ea8a BS |
192 | DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret); |
193 | ||
194 | return ret; | |
e80cfcfc FB |
195 | } |
196 | ||
c227f099 | 197 | static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, |
d2c38b24 | 198 | uint32_t val) |
e80cfcfc | 199 | { |
7204ff9c BS |
200 | TimerContext *tc = opaque; |
201 | SLAVIO_TIMERState *s = tc->s; | |
e80cfcfc | 202 | uint32_t saddr; |
7204ff9c BS |
203 | unsigned int timer_index = tc->timer_index; |
204 | CPUTimerState *t = &s->cputimer[timer_index]; | |
e80cfcfc | 205 | |
8d05ea8a | 206 | DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); |
e64d7d59 | 207 | saddr = addr >> 2; |
e80cfcfc | 208 | switch (saddr) { |
d2c38b24 | 209 | case TIMER_LIMIT: |
7204ff9c | 210 | if (slavio_timer_is_user(tc)) { |
e1cb9502 BS |
211 | uint64_t count; |
212 | ||
115646b6 | 213 | // set user counter MSW, reset counter |
7204ff9c BS |
214 | t->limit = TIMER_MAX_COUNT64; |
215 | t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); | |
216 | t->reached = 0; | |
217 | count = ((uint64_t)t->counthigh << 32) | t->count; | |
0bf9e31a | 218 | DPRINTF("processor %d user timer set to %016" PRIx64 "\n", |
7204ff9c | 219 | timer_index, count); |
9ebec28b | 220 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
115646b6 BS |
221 | } else { |
222 | // set limit, reset counter | |
7204ff9c BS |
223 | qemu_irq_lower(t->irq); |
224 | t->limit = val & TIMER_MAX_COUNT32; | |
225 | if (t->timer) { | |
226 | if (t->limit == 0) { /* free-run */ | |
227 | ptimer_set_limit(t->timer, | |
77f193da | 228 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); |
7204ff9c BS |
229 | } else { |
230 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1); | |
231 | } | |
85e3023e | 232 | } |
81732d19 | 233 | } |
115646b6 | 234 | break; |
d2c38b24 | 235 | case TIMER_COUNTER: |
7204ff9c | 236 | if (slavio_timer_is_user(tc)) { |
e1cb9502 BS |
237 | uint64_t count; |
238 | ||
115646b6 | 239 | // set user counter LSW, reset counter |
7204ff9c BS |
240 | t->limit = TIMER_MAX_COUNT64; |
241 | t->count = val & TIMER_MAX_COUNT64; | |
242 | t->reached = 0; | |
243 | count = ((uint64_t)t->counthigh) << 32 | t->count; | |
0bf9e31a | 244 | DPRINTF("processor %d user timer set to %016" PRIx64 "\n", |
7204ff9c | 245 | timer_index, count); |
9ebec28b | 246 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
115646b6 BS |
247 | } else |
248 | DPRINTF("not user timer\n"); | |
249 | break; | |
d2c38b24 | 250 | case TIMER_COUNTER_NORST: |
f930d07e | 251 | // set limit without resetting counter |
7204ff9c | 252 | t->limit = val & TIMER_MAX_COUNT32; |
9ebec28b BS |
253 | if (t->limit == 0) { /* free-run */ |
254 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); | |
255 | } else { | |
256 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0); | |
85e3023e | 257 | } |
f930d07e | 258 | break; |
d2c38b24 | 259 | case TIMER_STATUS: |
7204ff9c | 260 | if (slavio_timer_is_user(tc)) { |
115646b6 | 261 | // start/stop user counter |
7204ff9c BS |
262 | if ((val & 1) && !t->running) { |
263 | DPRINTF("processor %d user timer started\n", | |
264 | timer_index); | |
9ebec28b | 265 | ptimer_run(t->timer, 0); |
7204ff9c BS |
266 | t->running = 1; |
267 | } else if (!(val & 1) && t->running) { | |
268 | DPRINTF("processor %d user timer stopped\n", | |
269 | timer_index); | |
9ebec28b | 270 | ptimer_stop(t->timer); |
7204ff9c | 271 | t->running = 0; |
f930d07e BS |
272 | } |
273 | } | |
274 | break; | |
d2c38b24 | 275 | case TIMER_MODE: |
7204ff9c | 276 | if (timer_index == 0) { |
81732d19 BS |
277 | unsigned int i; |
278 | ||
7204ff9c | 279 | for (i = 0; i < s->num_cpus; i++) { |
67e42751 | 280 | unsigned int processor = 1 << i; |
7204ff9c | 281 | CPUTimerState *curr_timer = &s->cputimer[i + 1]; |
67e42751 BS |
282 | |
283 | // check for a change in timer mode for this processor | |
7204ff9c | 284 | if ((val & processor) != (s->cputimer_mode & processor)) { |
67e42751 | 285 | if (val & processor) { // counter -> user timer |
7204ff9c | 286 | qemu_irq_lower(curr_timer->irq); |
67e42751 | 287 | // counters are always running |
7204ff9c BS |
288 | ptimer_stop(curr_timer->timer); |
289 | curr_timer->running = 0; | |
67e42751 | 290 | // user timer limit is always the same |
7204ff9c BS |
291 | curr_timer->limit = TIMER_MAX_COUNT64; |
292 | ptimer_set_limit(curr_timer->timer, | |
293 | LIMIT_TO_PERIODS(curr_timer->limit), | |
77f193da | 294 | 1); |
67e42751 BS |
295 | // set this processors user timer bit in config |
296 | // register | |
7204ff9c | 297 | s->cputimer_mode |= processor; |
67e42751 | 298 | DPRINTF("processor %d changed from counter to user " |
7204ff9c | 299 | "timer\n", timer_index); |
67e42751 BS |
300 | } else { // user timer -> counter |
301 | // stop the user timer if it is running | |
7204ff9c BS |
302 | if (curr_timer->running) { |
303 | ptimer_stop(curr_timer->timer); | |
304 | } | |
67e42751 | 305 | // start the counter |
7204ff9c BS |
306 | ptimer_run(curr_timer->timer, 0); |
307 | curr_timer->running = 1; | |
67e42751 BS |
308 | // clear this processors user timer bit in config |
309 | // register | |
7204ff9c | 310 | s->cputimer_mode &= ~processor; |
67e42751 | 311 | DPRINTF("processor %d changed from user timer to " |
7204ff9c | 312 | "counter\n", timer_index); |
67e42751 | 313 | } |
115646b6 | 314 | } |
81732d19 | 315 | } |
7204ff9c | 316 | } else { |
115646b6 | 317 | DPRINTF("not system timer\n"); |
7204ff9c | 318 | } |
f930d07e | 319 | break; |
e80cfcfc | 320 | default: |
115646b6 | 321 | DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr); |
f930d07e | 322 | break; |
e80cfcfc FB |
323 | } |
324 | } | |
325 | ||
d60efc6b | 326 | static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = { |
7c560456 BS |
327 | NULL, |
328 | NULL, | |
e80cfcfc FB |
329 | slavio_timer_mem_readl, |
330 | }; | |
331 | ||
d60efc6b | 332 | static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = { |
7c560456 BS |
333 | NULL, |
334 | NULL, | |
e80cfcfc FB |
335 | slavio_timer_mem_writel, |
336 | }; | |
337 | ||
f4b19cd0 BS |
338 | static const VMStateDescription vmstate_timer = { |
339 | .name ="timer", | |
340 | .version_id = 3, | |
341 | .minimum_version_id = 3, | |
342 | .minimum_version_id_old = 3, | |
343 | .fields = (VMStateField []) { | |
344 | VMSTATE_UINT64(limit, CPUTimerState), | |
345 | VMSTATE_UINT32(count, CPUTimerState), | |
346 | VMSTATE_UINT32(counthigh, CPUTimerState), | |
347 | VMSTATE_UINT32(reached, CPUTimerState), | |
348 | VMSTATE_UINT32(running, CPUTimerState), | |
349 | VMSTATE_PTIMER(timer, CPUTimerState), | |
350 | VMSTATE_END_OF_LIST() | |
7204ff9c | 351 | } |
f4b19cd0 | 352 | }; |
e80cfcfc | 353 | |
f4b19cd0 BS |
354 | static const VMStateDescription vmstate_slavio_timer = { |
355 | .name ="slavio_timer", | |
356 | .version_id = 3, | |
357 | .minimum_version_id = 3, | |
358 | .minimum_version_id_old = 3, | |
359 | .fields = (VMStateField []) { | |
360 | VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, | |
361 | vmstate_timer, CPUTimerState), | |
362 | VMSTATE_END_OF_LIST() | |
7204ff9c | 363 | } |
f4b19cd0 | 364 | }; |
e80cfcfc | 365 | |
0e0bfeea | 366 | static void slavio_timer_reset(DeviceState *d) |
e80cfcfc | 367 | { |
0e0bfeea | 368 | SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev); |
7204ff9c BS |
369 | unsigned int i; |
370 | CPUTimerState *curr_timer; | |
371 | ||
372 | for (i = 0; i <= MAX_CPUS; i++) { | |
373 | curr_timer = &s->cputimer[i]; | |
374 | curr_timer->limit = 0; | |
375 | curr_timer->count = 0; | |
376 | curr_timer->reached = 0; | |
377 | if (i < s->num_cpus) { | |
378 | ptimer_set_limit(curr_timer->timer, | |
379 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); | |
380 | ptimer_run(curr_timer->timer, 0); | |
381 | } | |
382 | curr_timer->running = 1; | |
85e3023e | 383 | } |
7204ff9c | 384 | s->cputimer_mode = 0; |
e80cfcfc FB |
385 | } |
386 | ||
81a322d4 | 387 | static int slavio_timer_init1(SysBusDevice *dev) |
c70c59ee BS |
388 | { |
389 | int io; | |
390 | SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev); | |
8d05ea8a | 391 | QEMUBH *bh; |
7204ff9c BS |
392 | unsigned int i; |
393 | TimerContext *tc; | |
e80cfcfc | 394 | |
7204ff9c BS |
395 | for (i = 0; i <= MAX_CPUS; i++) { |
396 | tc = qemu_mallocz(sizeof(TimerContext)); | |
397 | tc->s = s; | |
398 | tc->timer_index = i; | |
c70c59ee | 399 | |
7204ff9c BS |
400 | bh = qemu_bh_new(slavio_timer_irq, tc); |
401 | s->cputimer[i].timer = ptimer_init(bh); | |
402 | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); | |
e80cfcfc | 403 | |
7204ff9c BS |
404 | io = cpu_register_io_memory(slavio_timer_mem_read, |
405 | slavio_timer_mem_write, tc); | |
406 | if (i == 0) { | |
407 | sysbus_init_mmio(dev, SYS_TIMER_SIZE, io); | |
408 | } else { | |
409 | sysbus_init_mmio(dev, CPU_TIMER_SIZE, io); | |
410 | } | |
411 | ||
412 | sysbus_init_irq(dev, &s->cputimer[i].irq); | |
c70c59ee BS |
413 | } |
414 | ||
81a322d4 | 415 | return 0; |
81732d19 BS |
416 | } |
417 | ||
c70c59ee BS |
418 | static SysBusDeviceInfo slavio_timer_info = { |
419 | .init = slavio_timer_init1, | |
420 | .qdev.name = "slavio_timer", | |
421 | .qdev.size = sizeof(SLAVIO_TIMERState), | |
0e0bfeea BS |
422 | .qdev.vmsd = &vmstate_slavio_timer, |
423 | .qdev.reset = slavio_timer_reset, | |
ee6847d1 | 424 | .qdev.props = (Property[]) { |
18c637dc GH |
425 | DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), |
426 | DEFINE_PROP_END_OF_LIST(), | |
c70c59ee BS |
427 | } |
428 | }; | |
429 | ||
430 | static void slavio_timer_register_devices(void) | |
431 | { | |
432 | sysbus_register_withprop(&slavio_timer_info); | |
433 | } | |
434 | ||
435 | device_init(slavio_timer_register_devices) |