[qemu.git] / hw / slavio_timer.c

/*
 * QEMU Sparc SLAVIO timer controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_TIMER

#ifdef DEBUG_TIMER
#define DPRINTF(fmt, args...) \
do { printf("TIMER: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

/*
 * Registers of hardware timer in sun4m.
 *
 * This is the timer/counter part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 * 
 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
 * are zero. Bit 31 is 1 when count has been reached.
 *
 * Per-CPU timers interrupt local CPU, system timer uses normal
 * interrupt routing.
 *
 */

typedef struct SLAVIO_TIMERState {
    uint32_t limit, count, counthigh;
    int64_t count_load_time;
    int64_t expire_time;
    int64_t stop_time, tick_offset;
    QEMUTimer *irq_timer;
    int irq;
    int reached, stopped;
    int mode; // 0 = processor, 1 = user, 2 = system
    unsigned int cpu;
    void *intctl;
} SLAVIO_TIMERState;

#define TIMER_MAXADDR 0x1f
#define CNT_FREQ 2000000

// Update count, set irq, update expire_time
static void slavio_timer_get_out(SLAVIO_TIMERState *s)
{
    int out;
    int64_t diff, ticks, count;
    uint32_t limit;

    // There are three clock tick units: CPU ticks, register units
    // (nanoseconds), and counter ticks (500 ns).
    if (s->mode == 1 && s->stopped)
	ticks = s->stop_time;
    else
	ticks = qemu_get_clock(vm_clock) - s->tick_offset;

    out = (ticks > s->expire_time);
    if (out)
	s->reached = 0x80000000;
    // Convert register units to counter ticks
    limit = s->limit >> 9;

    if (!limit)
	limit = 0x7fffffff >> 9;

    // Convert cpu ticks to counter ticks
    diff = muldiv64(ticks - s->count_load_time, CNT_FREQ, ticks_per_sec);

    // Calculate what the counter should be, convert to register
    // units
    count = diff % limit;
    s->count = count << 9;
    s->counthigh = count >> 22;

    // Expire time: CPU ticks left to next interrupt
    // Convert remaining counter ticks to CPU ticks
    s->expire_time = ticks + muldiv64(limit - count, ticks_per_sec, CNT_FREQ);

    DPRINTF("irq %d limit %d reached %d d %" PRId64 " count %d s->c %x diff %" PRId64 " stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);

    if (s->mode != 1)
	pic_set_irq_cpu(s->intctl, s->irq, out, s->cpu);
}

// timer callback
static void slavio_timer_irq(void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    if (!s->irq_timer)
        return;
    slavio_timer_get_out(s);
    if (s->mode != 1)
	qemu_mod_timer(s->irq_timer, s->expire_time);
}

static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_TIMERState *s = opaque;
    uint32_t saddr;

    saddr = (addr & TIMER_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	// read limit (system counter mode) or read most signifying
	// part of counter (user mode)
	if (s->mode != 1) {
	    // clear irq
	    pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
	    s->reached = 0;
	    return s->limit;
	}
	else {
	    slavio_timer_get_out(s);
	    return s->counthigh & 0x7fffffff;
	}
    case 1:
	// read counter and reached bit (system mode) or read lsbits
	// of counter (user mode)
	slavio_timer_get_out(s);
	if (s->mode != 1)
	    return (s->count & 0x7fffffff) | s->reached;
	else
	    return s->count;
    case 3:
	// read start/stop status
	return s->stopped;
    case 4:
	// read user/system mode
	return s->mode & 1;
    default:
	return 0;
    }
}

static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_TIMERState *s = opaque;
    uint32_t saddr;

    saddr = (addr & TIMER_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	// set limit, reset counter
	s->count_load_time = qemu_get_clock(vm_clock);
	// fall through
    case 2:
	// set limit without resetting counter
	if (!val)
	    s->limit = 0x7fffffff;
	else
	    s->limit = val & 0x7fffffff;
	slavio_timer_irq(s);
	break;
    case 3:
	// start/stop user counter
	if (s->mode == 1) {
	    if (val & 1) {
		s->stop_time = qemu_get_clock(vm_clock);
		s->stopped = 1;
	    }
	    else {
		if (s->stopped)
		    s->tick_offset += qemu_get_clock(vm_clock) - s->stop_time;
		s->stopped = 0;
	    }
	}
	break;
    case 4:
	// bit 0: user (1) or system (0) counter mode
	if (s->mode == 0 || s->mode == 1)
	    s->mode = val & 1;
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
    slavio_timer_mem_readl,
    slavio_timer_mem_readl,
    slavio_timer_mem_readl,
};

static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
    slavio_timer_mem_writel,
    slavio_timer_mem_writel,
    slavio_timer_mem_writel,
};

static void slavio_timer_save(QEMUFile *f, void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    qemu_put_be32s(f, &s->limit);
    qemu_put_be32s(f, &s->count);
    qemu_put_be32s(f, &s->counthigh);
    qemu_put_be64s(f, &s->count_load_time);
    qemu_put_be64s(f, &s->expire_time);
    qemu_put_be64s(f, &s->stop_time);
    qemu_put_be64s(f, &s->tick_offset);
    qemu_put_be32s(f, &s->irq);
    qemu_put_be32s(f, &s->reached);
    qemu_put_be32s(f, &s->stopped);
    qemu_put_be32s(f, &s->mode);
}

static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_TIMERState *s = opaque;
    
    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, &s->limit);
    qemu_get_be32s(f, &s->count);
    qemu_get_be32s(f, &s->counthigh);
    qemu_get_be64s(f, &s->count_load_time);
    qemu_get_be64s(f, &s->expire_time);
    qemu_get_be64s(f, &s->stop_time);
    qemu_get_be64s(f, &s->tick_offset);
    qemu_get_be32s(f, &s->irq);
    qemu_get_be32s(f, &s->reached);
    qemu_get_be32s(f, &s->stopped);
    qemu_get_be32s(f, &s->mode);
    return 0;
}

static void slavio_timer_reset(void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    s->limit = 0;
    s->count = 0;
    s->count_load_time = qemu_get_clock(vm_clock);;
    s->stop_time = s->count_load_time;
    s->tick_offset = 0;
    s->reached = 0;
    s->mode &= 2;
    s->stopped = 1;
    slavio_timer_irq(s);
}

void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
                       unsigned int cpu, void *intctl)
{
    int slavio_timer_io_memory;
    SLAVIO_TIMERState *s;

    s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
    if (!s)
        return;
    s->irq = irq;
    s->mode = mode;
    s->cpu = cpu;
    s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s);
    s->intctl = intctl;

    slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
						    slavio_timer_mem_write, s);
    cpu_register_physical_memory(addr, TIMER_MAXADDR, slavio_timer_io_memory);
    register_savevm("slavio_timer", addr, 1, slavio_timer_save, slavio_timer_load, s);
    qemu_register_reset(slavio_timer_reset, s);
    slavio_timer_reset(s);
}
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO timer controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
e80cfcfc FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	//#define DEBUG_TIMER
	27
66321a11 FB	28	#ifdef DEBUG_TIMER
	29	#define DPRINTF(fmt, args...) \
	30	do { printf("TIMER: " fmt , ##args); } while (0)
	31	#else
	32	#define DPRINTF(fmt, args...)
	33	#endif
	34
e80cfcfc FB	35	/*
	36	* Registers of hardware timer in sun4m.
	37	*
	38	* This is the timer/counter part of chip STP2001 (Slave I/O), also
	39	* produced as NCR89C105. See
	40	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	41	*
	42	* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
	43	* are zero. Bit 31 is 1 when count has been reached.
	44	*
ba3c64fb FB	45	* Per-CPU timers interrupt local CPU, system timer uses normal
	46	* interrupt routing.
	47	*
e80cfcfc FB	48	*/
	49
	50	typedef struct SLAVIO_TIMERState {
	51	uint32_t limit, count, counthigh;
	52	int64_t count_load_time;
	53	int64_t expire_time;
	54	int64_t stop_time, tick_offset;
	55	QEMUTimer *irq_timer;
	56	int irq;
	57	int reached, stopped;
	58	int mode; // 0 = processor, 1 = user, 2 = system
ba3c64fb	59	unsigned int cpu;
52cc07d0	60	void *intctl;
e80cfcfc FB	61	} SLAVIO_TIMERState;
	62
	63	#define TIMER_MAXADDR 0x1f
	64	#define CNT_FREQ 2000000
e80cfcfc FB	65
	66	// Update count, set irq, update expire_time
	67	static void slavio_timer_get_out(SLAVIO_TIMERState *s)
	68	{
	69	int out;
	70	int64_t diff, ticks, count;
	71	uint32_t limit;
	72
	73	// There are three clock tick units: CPU ticks, register units
	74	// (nanoseconds), and counter ticks (500 ns).
	75	if (s->mode == 1 && s->stopped)
	76	ticks = s->stop_time;
	77	else
	78	ticks = qemu_get_clock(vm_clock) - s->tick_offset;
	79
ba3c64fb	80	out = (ticks > s->expire_time);
e80cfcfc FB	81	if (out)
e80cfcfc FB	82	s->reached = 0x80000000;
e80cfcfc	83	// Convert register units to counter ticks
31ade715 BS	84	limit = s->limit >> 9;
	85
	86	if (!limit)
	87	limit = 0x7fffffff >> 9;
e80cfcfc FB	88
	89	// Convert cpu ticks to counter ticks
	90	diff = muldiv64(ticks - s->count_load_time, CNT_FREQ, ticks_per_sec);
	91
	92	// Calculate what the counter should be, convert to register
	93	// units
	94	count = diff % limit;
	95	s->count = count << 9;
	96	s->counthigh = count >> 22;
	97
	98	// Expire time: CPU ticks left to next interrupt
	99	// Convert remaining counter ticks to CPU ticks
	100	s->expire_time = ticks + muldiv64(limit - count, ticks_per_sec, CNT_FREQ);
	101
26a76461	102	DPRINTF("irq %d limit %d reached %d d %" PRId64 " count %d s->c %x diff %" PRId64 " stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);
66321a11	103
e80cfcfc	104	if (s->mode != 1)
52cc07d0	105	pic_set_irq_cpu(s->intctl, s->irq, out, s->cpu);
e80cfcfc FB	106	}
	107
	108	// timer callback
	109	static void slavio_timer_irq(void *opaque)
	110	{
	111	SLAVIO_TIMERState *s = opaque;
	112
	113	if (!s->irq_timer)
	114	return;
	115	slavio_timer_get_out(s);
	116	if (s->mode != 1)
	117	qemu_mod_timer(s->irq_timer, s->expire_time);
	118	}
	119
	120	static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
	121	{
	122	SLAVIO_TIMERState *s = opaque;
	123	uint32_t saddr;
	124
	125	saddr = (addr & TIMER_MAXADDR) >> 2;
	126	switch (saddr) {
	127	case 0:
	128	// read limit (system counter mode) or read most signifying
	129	// part of counter (user mode)
	130	if (s->mode != 1) {
	131	// clear irq
52cc07d0	132	pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
e80cfcfc FB	133	s->reached = 0;
	134	return s->limit;
	135	}
	136	else {
	137	slavio_timer_get_out(s);
	138	return s->counthigh & 0x7fffffff;
	139	}
	140	case 1:
	141	// read counter and reached bit (system mode) or read lsbits
	142	// of counter (user mode)
	143	slavio_timer_get_out(s);
	144	if (s->mode != 1)
	145	return (s->count & 0x7fffffff) \| s->reached;
	146	else
	147	return s->count;
	148	case 3:
	149	// read start/stop status
	150	return s->stopped;
	151	case 4:
	152	// read user/system mode
	153	return s->mode & 1;
	154	default:
	155	return 0;
	156	}
	157	}
	158
	159	static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	160	{
	161	SLAVIO_TIMERState *s = opaque;
	162	uint32_t saddr;
	163
	164	saddr = (addr & TIMER_MAXADDR) >> 2;
	165	switch (saddr) {
	166	case 0:
	167	// set limit, reset counter
	168	s->count_load_time = qemu_get_clock(vm_clock);
	169	// fall through
	170	case 2:
	171	// set limit without resetting counter
	172	if (!val)
	173	s->limit = 0x7fffffff;
	174	else
	175	s->limit = val & 0x7fffffff;
	176	slavio_timer_irq(s);
	177	break;
	178	case 3:
	179	// start/stop user counter
	180	if (s->mode == 1) {
	181	if (val & 1) {
	182	s->stop_time = qemu_get_clock(vm_clock);
	183	s->stopped = 1;
	184	}
	185	else {
	186	if (s->stopped)
	187	s->tick_offset += qemu_get_clock(vm_clock) - s->stop_time;
	188	s->stopped = 0;
	189	}
	190	}
	191	break;
	192	case 4:
	193	// bit 0: user (1) or system (0) counter mode
	194	if (s->mode == 0 \|\| s->mode == 1)
	195	s->mode = val & 1;
	196	break;
197	default:
198	break;
199	}
200	}
201
202	static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
203	slavio_timer_mem_readl,
204	slavio_timer_mem_readl,
205	slavio_timer_mem_readl,
206	};
207
208	static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
209	slavio_timer_mem_writel,
210	slavio_timer_mem_writel,
211	slavio_timer_mem_writel,
212	};
213
214	static void slavio_timer_save(QEMUFile f, void opaque)
215	{
216	SLAVIO_TIMERState *s = opaque;
217
218	qemu_put_be32s(f, &s->limit);
219	qemu_put_be32s(f, &s->count);
220	qemu_put_be32s(f, &s->counthigh);
221	qemu_put_be64s(f, &s->count_load_time);
222	qemu_put_be64s(f, &s->expire_time);
223	qemu_put_be64s(f, &s->stop_time);
224	qemu_put_be64s(f, &s->tick_offset);
225	qemu_put_be32s(f, &s->irq);
226	qemu_put_be32s(f, &s->reached);
227	qemu_put_be32s(f, &s->stopped);
228	qemu_put_be32s(f, &s->mode);
229	}
230
231	static int slavio_timer_load(QEMUFile f, void opaque, int version_id)
232	{
233	SLAVIO_TIMERState *s = opaque;
234
235	if (version_id != 1)
236	return -EINVAL;
237
238	qemu_get_be32s(f, &s->limit);
239	qemu_get_be32s(f, &s->count);
240	qemu_get_be32s(f, &s->counthigh);
241	qemu_get_be64s(f, &s->count_load_time);
242	qemu_get_be64s(f, &s->expire_time);
243	qemu_get_be64s(f, &s->stop_time);
244	qemu_get_be64s(f, &s->tick_offset);
245	qemu_get_be32s(f, &s->irq);
246	qemu_get_be32s(f, &s->reached);
247	qemu_get_be32s(f, &s->stopped);
248	qemu_get_be32s(f, &s->mode);
249	return 0;
250	}
251
252	static void slavio_timer_reset(void *opaque)
253	{
254	SLAVIO_TIMERState *s = opaque;
255
256	s->limit = 0;
257	s->count = 0;
258	s->count_load_time = qemu_get_clock(vm_clock);;
259	s->stop_time = s->count_load_time;
260	s->tick_offset = 0;
261	s->reached = 0;
262	s->mode &= 2;
263	s->stopped = 1;
3d29fbef	264	slavio_timer_irq(s);
e80cfcfc FB	265	}
e80cfcfc FB	266
5dcb6b91 BS	267	void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
5dcb6b91 BS	268	unsigned int cpu, void *intctl)
e80cfcfc FB	269	{
	270	int slavio_timer_io_memory;
	271	SLAVIO_TIMERState *s;
	272
	273	s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
	274	if (!s)
	275	return;
	276	s->irq = irq;
	277	s->mode = mode;
ba3c64fb	278	s->cpu = cpu;
e80cfcfc	279	s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s);
52cc07d0	280	s->intctl = intctl;
e80cfcfc FB	281
	282	slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
	283	slavio_timer_mem_write, s);
	284	cpu_register_physical_memory(addr, TIMER_MAXADDR, slavio_timer_io_memory);
	285	register_savevm("slavio_timer", addr, 1, slavio_timer_save, slavio_timer_load, s);
	286	qemu_register_reset(slavio_timer_reset, s);
	287	slavio_timer_reset(s);
	288	}