[qemu.git] / hw / slavio_timer.c

/*
 * QEMU Sparc SLAVIO timer controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"
#include "qemu-timer.h"

//#define DEBUG_TIMER

#ifdef DEBUG_TIMER
#define DPRINTF(fmt, args...) \
do { printf("TIMER: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

/*
 * Registers of hardware timer in sun4m.
 *
 * This is the timer/counter part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
 * are zero. Bit 31 is 1 when count has been reached.
 *
 * Per-CPU timers interrupt local CPU, system timer uses normal
 * interrupt routing.
 *
 */

#define MAX_CPUS 16

typedef struct SLAVIO_TIMERState {
    qemu_irq irq;
    ptimer_state *timer;
    uint32_t count, counthigh, reached;
    uint64_t limit;
    // processor only
    int running;
    struct SLAVIO_TIMERState *master;
    int slave_index;
    // system only
    unsigned int num_slaves;
    struct SLAVIO_TIMERState *slave[MAX_CPUS];
    uint32_t slave_mode;
} SLAVIO_TIMERState;

#define TIMER_MAXADDR 0x1f
#define SYS_TIMER_SIZE 0x14
#define CPU_TIMER_SIZE 0x10

#define SYS_TIMER_OFFSET      0x10000ULL
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)

#define TIMER_LIMIT         0
#define TIMER_COUNTER       1
#define TIMER_COUNTER_NORST 2
#define TIMER_STATUS        3
#define TIMER_MODE          4

#define TIMER_COUNT_MASK32 0xfffffe00
#define TIMER_LIMIT_MASK32 0x7fffffff
#define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
#define TIMER_MAX_COUNT32  0x7ffffe00ULL
#define TIMER_REACHED      0x80000000
#define TIMER_PERIOD       500ULL // 500ns
#define LIMIT_TO_PERIODS(l) ((l) >> 9)
#define PERIODS_TO_LIMIT(l) ((l) << 9)

static int slavio_timer_is_user(SLAVIO_TIMERState *s)
{
    return s->master && (s->master->slave_mode & (1 << s->slave_index));
}

// Update count, set irq, update expire_time
// Convert from ptimer countdown units
static void slavio_timer_get_out(SLAVIO_TIMERState *s)
{
    uint64_t count, limit;

    if (s->limit == 0) /* free-run processor or system counter */
        limit = TIMER_MAX_COUNT32;
    else
        limit = s->limit;

    if (s->timer)
        count = limit - PERIODS_TO_LIMIT(ptimer_get_count(s->timer));
    else
        count = 0;

    DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit,
            s->counthigh, s->count);
    s->count = count & TIMER_COUNT_MASK32;
    s->counthigh = count >> 32;
}

// timer callback
static void slavio_timer_irq(void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    slavio_timer_get_out(s);
    DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
    if (!slavio_timer_is_user(s)) {
        s->reached = TIMER_REACHED;
        qemu_irq_raise(s->irq);
    }
}

static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_TIMERState *s = opaque;
    uint32_t saddr, ret;

    saddr = (addr & TIMER_MAXADDR) >> 2;
    switch (saddr) {
    case TIMER_LIMIT:
        // read limit (system counter mode) or read most signifying
        // part of counter (user mode)
        if (slavio_timer_is_user(s)) {
            // read user timer MSW
            slavio_timer_get_out(s);
            ret = s->counthigh;
        } else {
            // read limit
            // clear irq
            qemu_irq_lower(s->irq);
            s->reached = 0;
            ret = s->limit & TIMER_LIMIT_MASK32;
        }
        break;
    case TIMER_COUNTER:
        // read counter and reached bit (system mode) or read lsbits
        // of counter (user mode)
        slavio_timer_get_out(s);
        if (slavio_timer_is_user(s)) // read user timer LSW
            ret = s->count & TIMER_COUNT_MASK32;
        else // read limit
            ret = (s->count & TIMER_MAX_COUNT32) | s->reached;
        break;
    case TIMER_STATUS:
        // only available in processor counter/timer
        // read start/stop status
        ret = s->running;
        break;
    case TIMER_MODE:
        // only available in system counter
        // read user/system mode
        ret = s->slave_mode;
        break;
    default:
        DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
        ret = 0;
        break;
    }
    DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);

    return ret;
}

static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
                                    uint32_t val)
{
    SLAVIO_TIMERState *s = opaque;
    uint32_t saddr;

    DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
    saddr = (addr & TIMER_MAXADDR) >> 2;
    switch (saddr) {
    case TIMER_LIMIT:
        if (slavio_timer_is_user(s)) {
            // set user counter MSW, reset counter
            qemu_irq_lower(s->irq);
            s->limit = TIMER_MAX_COUNT64;
            DPRINTF("processor %d user timer reset\n", s->slave_index);
            if (s->timer)
                ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
        } else {
            // set limit, reset counter
            qemu_irq_lower(s->irq);
            s->limit = val & TIMER_MAX_COUNT32;
            if (s->timer) {
                if (s->limit == 0) /* free-run */
                    ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
                else
                    ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
            }
        }
        break;
    case TIMER_COUNTER:
        if (slavio_timer_is_user(s)) {
            // set user counter LSW, reset counter
            qemu_irq_lower(s->irq);
            s->limit = TIMER_MAX_COUNT64;
            DPRINTF("processor %d user timer reset\n", s->slave_index);
            if (s->timer)
                ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
        } else
            DPRINTF("not user timer\n");
        break;
    case TIMER_COUNTER_NORST:
        // set limit without resetting counter
        s->limit = val & TIMER_MAX_COUNT32;
        if (s->timer) {
            if (s->limit == 0)	/* free-run */
                ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
            else
                ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
        }
        break;
    case TIMER_STATUS:
        if (slavio_timer_is_user(s)) {
            // start/stop user counter
            if ((val & 1) && !s->running) {
                DPRINTF("processor %d user timer started\n", s->slave_index);
                if (s->timer)
                    ptimer_run(s->timer, 0);
                s->running = 1;
            } else if (!(val & 1) && s->running) {
                DPRINTF("processor %d user timer stopped\n", s->slave_index);
                if (s->timer)
                    ptimer_stop(s->timer);
                s->running = 0;
            }
        }
        break;
    case TIMER_MODE:
        if (s->master == NULL) {
            unsigned int i;

            for (i = 0; i < s->num_slaves; i++) {
                if (val & (1 << i)) {
                    qemu_irq_lower(s->slave[i]->irq);
                    s->slave[i]->limit = -1ULL;
                } else {
                    ptimer_stop(s->slave[i]->timer);
                }
                if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
                    ptimer_stop(s->slave[i]->timer);
                    ptimer_set_limit(s->slave[i]->timer,
                                     LIMIT_TO_PERIODS(s->slave[i]->limit), 1);
                    DPRINTF("processor %d timer changed\n",
                            s->slave[i]->slave_index);
                    ptimer_run(s->slave[i]->timer, 0);
                }
            }
            s->slave_mode = val & ((1 << s->num_slaves) - 1);
        } else
            DPRINTF("not system timer\n");
        break;
    default:
        DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
        break;
    }
}

static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
    slavio_timer_mem_readl,
    slavio_timer_mem_readl,
    slavio_timer_mem_readl,
};

static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
    slavio_timer_mem_writel,
    slavio_timer_mem_writel,
    slavio_timer_mem_writel,
};

static void slavio_timer_save(QEMUFile *f, void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    qemu_put_be64s(f, &s->limit);
    qemu_put_be32s(f, &s->count);
    qemu_put_be32s(f, &s->counthigh);
    qemu_put_be32s(f, &s->reached);
    qemu_put_be32s(f, &s->running);
    if (s->timer)
        qemu_put_ptimer(f, s->timer);
}

static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_TIMERState *s = opaque;

    if (version_id != 3)
        return -EINVAL;

    qemu_get_be64s(f, &s->limit);
    qemu_get_be32s(f, &s->count);
    qemu_get_be32s(f, &s->counthigh);
    qemu_get_be32s(f, &s->reached);
    qemu_get_be32s(f, &s->running);
    if (s->timer)
        qemu_get_ptimer(f, s->timer);

    return 0;
}

static void slavio_timer_reset(void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    s->limit = 0;
    s->count = 0;
    s->reached = 0;
    s->slave_mode = 0;
    if (!s->master || s->slave_index < s->master->num_slaves) {
        ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
        ptimer_run(s->timer, 0);
    }
    s->running = 1;
    qemu_irq_lower(s->irq);
}

static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
                                            qemu_irq irq,
                                            SLAVIO_TIMERState *master,
                                            int slave_index)
{
    int slavio_timer_io_memory;
    SLAVIO_TIMERState *s;
    QEMUBH *bh;

    s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
    if (!s)
        return s;
    s->irq = irq;
    s->master = master;
    s->slave_index = slave_index;
    if (!master || slave_index < master->num_slaves) {
        bh = qemu_bh_new(slavio_timer_irq, s);
        s->timer = ptimer_init(bh);
        ptimer_set_period(s->timer, TIMER_PERIOD);
    }

    slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
                                                    slavio_timer_mem_write, s);
    if (master)
        cpu_register_physical_memory(addr, CPU_TIMER_SIZE,
                                     slavio_timer_io_memory);
    else
        cpu_register_physical_memory(addr, SYS_TIMER_SIZE,
                                     slavio_timer_io_memory);
    register_savevm("slavio_timer", addr, 3, slavio_timer_save,
                    slavio_timer_load, s);
    qemu_register_reset(slavio_timer_reset, s);
    slavio_timer_reset(s);

    return s;
}

void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
                           qemu_irq *cpu_irqs, unsigned int num_cpus)
{
    SLAVIO_TIMERState *master;
    unsigned int i;

    master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0);

    master->num_slaves = num_cpus;

    for (i = 0; i < MAX_CPUS; i++) {
        master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
                                             CPU_TIMER_OFFSET(i),
                                             cpu_irqs[i], master, i);
    }
}
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO timer controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
e80cfcfc FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "sun4m.h"
	26	#include "qemu-timer.h"
e80cfcfc FB	27
	28	//#define DEBUG_TIMER
	29
66321a11 FB	30	#ifdef DEBUG_TIMER
	31	#define DPRINTF(fmt, args...) \
	32	do { printf("TIMER: " fmt , ##args); } while (0)
	33	#else
	34	#define DPRINTF(fmt, args...)
	35	#endif
	36
e80cfcfc FB	37	/*
	38	* Registers of hardware timer in sun4m.
	39	*
	40	* This is the timer/counter part of chip STP2001 (Slave I/O), also
	41	* produced as NCR89C105. See
	42	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
5fafdf24	43	*
e80cfcfc FB	44	* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
	45	* are zero. Bit 31 is 1 when count has been reached.
	46	*
ba3c64fb FB	47	* Per-CPU timers interrupt local CPU, system timer uses normal
	48	* interrupt routing.
	49	*
e80cfcfc FB	50	*/
e80cfcfc FB	51
81732d19 BS	52	#define MAX_CPUS 16
81732d19 BS	53
e80cfcfc	54	typedef struct SLAVIO_TIMERState {
d7edfd27	55	qemu_irq irq;
8d05ea8a BS	56	ptimer_state *timer;
	57	uint32_t count, counthigh, reached;
	58	uint64_t limit;
115646b6 BS	59	// processor only
	60	int running;
	61	struct SLAVIO_TIMERState *master;
	62	int slave_index;
	63	// system only
19f8e5dd	64	unsigned int num_slaves;
81732d19 BS	65	struct SLAVIO_TIMERState *slave[MAX_CPUS];
81732d19 BS	66	uint32_t slave_mode;
e80cfcfc FB	67	} SLAVIO_TIMERState;
	68
	69	#define TIMER_MAXADDR 0x1f
115646b6	70	#define SYS_TIMER_SIZE 0x14
81732d19	71	#define CPU_TIMER_SIZE 0x10
e80cfcfc	72
d2c38b24 BS	73	#define SYS_TIMER_OFFSET 0x10000ULL
	74	#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
	75
	76	#define TIMER_LIMIT 0
	77	#define TIMER_COUNTER 1
	78	#define TIMER_COUNTER_NORST 2
	79	#define TIMER_STATUS 3
	80	#define TIMER_MODE 4
	81
	82	#define TIMER_COUNT_MASK32 0xfffffe00
	83	#define TIMER_LIMIT_MASK32 0x7fffffff
	84	#define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
	85	#define TIMER_MAX_COUNT32 0x7ffffe00ULL
	86	#define TIMER_REACHED 0x80000000
	87	#define TIMER_PERIOD 500ULL // 500ns
	88	#define LIMIT_TO_PERIODS(l) ((l) >> 9)
	89	#define PERIODS_TO_LIMIT(l) ((l) << 9)
	90
115646b6 BS	91	static int slavio_timer_is_user(SLAVIO_TIMERState *s)
	92	{
	93	return s->master && (s->master->slave_mode & (1 << s->slave_index));
	94	}
	95
e80cfcfc	96	// Update count, set irq, update expire_time
8d05ea8a	97	// Convert from ptimer countdown units
e80cfcfc FB	98	static void slavio_timer_get_out(SLAVIO_TIMERState *s)
e80cfcfc FB	99	{
bd7e2875	100	uint64_t count, limit;
e80cfcfc	101
bd7e2875 BS	102	if (s->limit == 0) /* free-run processor or system counter */
	103	limit = TIMER_MAX_COUNT32;
	104	else
	105	limit = s->limit;
	106
85e3023e BS	107	if (s->timer)
	108	count = limit - PERIODS_TO_LIMIT(ptimer_get_count(s->timer));
	109	else
	110	count = 0;
	111
d2c38b24 BS	112	DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit,
	113	s->counthigh, s->count);
	114	s->count = count & TIMER_COUNT_MASK32;
8d05ea8a	115	s->counthigh = count >> 32;
e80cfcfc FB	116	}
	117
	118	// timer callback
	119	static void slavio_timer_irq(void *opaque)
	120	{
	121	SLAVIO_TIMERState *s = opaque;
	122
e80cfcfc	123	slavio_timer_get_out(s);
8d05ea8a	124	DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
115646b6	125	if (!slavio_timer_is_user(s)) {
d2c38b24	126	s->reached = TIMER_REACHED;
f930d07e	127	qemu_irq_raise(s->irq);
115646b6	128	}
e80cfcfc FB	129	}
	130
	131	static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
	132	{
	133	SLAVIO_TIMERState *s = opaque;
8d05ea8a	134	uint32_t saddr, ret;
e80cfcfc FB	135
	136	saddr = (addr & TIMER_MAXADDR) >> 2;
	137	switch (saddr) {
d2c38b24	138	case TIMER_LIMIT:
f930d07e BS	139	// read limit (system counter mode) or read most signifying
f930d07e BS	140	// part of counter (user mode)
115646b6 BS	141	if (slavio_timer_is_user(s)) {
	142	// read user timer MSW
	143	slavio_timer_get_out(s);
	144	ret = s->counthigh;
	145	} else {
	146	// read limit
f930d07e	147	// clear irq
d7edfd27	148	qemu_irq_lower(s->irq);
f930d07e	149	s->reached = 0;
d2c38b24	150	ret = s->limit & TIMER_LIMIT_MASK32;
f930d07e	151	}
8d05ea8a	152	break;
d2c38b24	153	case TIMER_COUNTER:
f930d07e BS	154	// read counter and reached bit (system mode) or read lsbits
	155	// of counter (user mode)
	156	slavio_timer_get_out(s);
115646b6	157	if (slavio_timer_is_user(s)) // read user timer LSW
d2c38b24	158	ret = s->count & TIMER_COUNT_MASK32;
115646b6	159	else // read limit
d2c38b24	160	ret = (s->count & TIMER_MAX_COUNT32) \| s->reached;
8d05ea8a	161	break;
d2c38b24	162	case TIMER_STATUS:
115646b6	163	// only available in processor counter/timer
f930d07e	164	// read start/stop status
115646b6	165	ret = s->running;
8d05ea8a	166	break;
d2c38b24	167	case TIMER_MODE:
115646b6	168	// only available in system counter
f930d07e	169	// read user/system mode
81732d19	170	ret = s->slave_mode;
8d05ea8a	171	break;
e80cfcfc	172	default:
115646b6	173	DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
8d05ea8a BS	174	ret = 0;
8d05ea8a BS	175	break;
e80cfcfc	176	}
8d05ea8a BS	177	DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
	178
	179	return ret;
e80cfcfc FB	180	}
e80cfcfc FB	181
d2c38b24 BS	182	static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
d2c38b24 BS	183	uint32_t val)
e80cfcfc FB	184	{
	185	SLAVIO_TIMERState *s = opaque;
	186	uint32_t saddr;
	187
8d05ea8a	188	DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
e80cfcfc FB	189	saddr = (addr & TIMER_MAXADDR) >> 2;
e80cfcfc FB	190	switch (saddr) {
d2c38b24	191	case TIMER_LIMIT:
115646b6 BS	192	if (slavio_timer_is_user(s)) {
115646b6 BS	193	// set user counter MSW, reset counter
81732d19	194	qemu_irq_lower(s->irq);
d2c38b24	195	s->limit = TIMER_MAX_COUNT64;
115646b6	196	DPRINTF("processor %d user timer reset\n", s->slave_index);
85e3023e BS	197	if (s->timer)
85e3023e BS	198	ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
115646b6 BS	199	} else {
	200	// set limit, reset counter
	201	qemu_irq_lower(s->irq);
d2c38b24	202	s->limit = val & TIMER_MAX_COUNT32;
85e3023e BS	203	if (s->timer) {
	204	if (s->limit == 0) /* free-run */
	205	ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
	206	else
	207	ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
	208	}
81732d19	209	}
115646b6	210	break;
d2c38b24	211	case TIMER_COUNTER:
115646b6 BS	212	if (slavio_timer_is_user(s)) {
	213	// set user counter LSW, reset counter
	214	qemu_irq_lower(s->irq);
d2c38b24	215	s->limit = TIMER_MAX_COUNT64;
115646b6	216	DPRINTF("processor %d user timer reset\n", s->slave_index);
85e3023e BS	217	if (s->timer)
85e3023e BS	218	ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
115646b6 BS	219	} else
	220	DPRINTF("not user timer\n");
	221	break;
d2c38b24	222	case TIMER_COUNTER_NORST:
f930d07e	223	// set limit without resetting counter
d2c38b24	224	s->limit = val & TIMER_MAX_COUNT32;
85e3023e BS	225	if (s->timer) {
	226	if (s->limit == 0) /* free-run */
	227	ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
	228	else
	229	ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
	230	}
f930d07e	231	break;
d2c38b24	232	case TIMER_STATUS:
115646b6 BS	233	if (slavio_timer_is_user(s)) {
	234	// start/stop user counter
	235	if ((val & 1) && !s->running) {
	236	DPRINTF("processor %d user timer started\n", s->slave_index);
85e3023e BS	237	if (s->timer)
85e3023e BS	238	ptimer_run(s->timer, 0);
115646b6 BS	239	s->running = 1;
	240	} else if (!(val & 1) && s->running) {
	241	DPRINTF("processor %d user timer stopped\n", s->slave_index);
85e3023e BS	242	if (s->timer)
85e3023e BS	243	ptimer_stop(s->timer);
115646b6	244	s->running = 0;
f930d07e BS	245	}
	246	}
	247	break;
d2c38b24	248	case TIMER_MODE:
115646b6	249	if (s->master == NULL) {
81732d19 BS	250	unsigned int i;
81732d19 BS	251
19f8e5dd	252	for (i = 0; i < s->num_slaves; i++) {
81732d19 BS	253	if (val & (1 << i)) {
	254	qemu_irq_lower(s->slave[i]->irq);
	255	s->slave[i]->limit = -1ULL;
6341fdcb BS	256	} else {
6341fdcb BS	257	ptimer_stop(s->slave[i]->timer);
81732d19	258	}
115646b6 BS	259	if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
115646b6 BS	260	ptimer_stop(s->slave[i]->timer);
d2c38b24 BS	261	ptimer_set_limit(s->slave[i]->timer,
	262	LIMIT_TO_PERIODS(s->slave[i]->limit), 1);
	263	DPRINTF("processor %d timer changed\n",
	264	s->slave[i]->slave_index);
115646b6 BS	265	ptimer_run(s->slave[i]->timer, 0);
115646b6 BS	266	}
81732d19	267	}
19f8e5dd	268	s->slave_mode = val & ((1 << s->num_slaves) - 1);
115646b6 BS	269	} else
115646b6 BS	270	DPRINTF("not system timer\n");
f930d07e	271	break;
e80cfcfc	272	default:
115646b6	273	DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
f930d07e	274	break;
e80cfcfc FB	275	}
	276	}
	277
	278	static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
	279	slavio_timer_mem_readl,
	280	slavio_timer_mem_readl,
	281	slavio_timer_mem_readl,
	282	};
	283
	284	static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
	285	slavio_timer_mem_writel,
	286	slavio_timer_mem_writel,
	287	slavio_timer_mem_writel,
	288	};
	289
	290	static void slavio_timer_save(QEMUFile f, void opaque)
	291	{
	292	SLAVIO_TIMERState *s = opaque;
	293
8d05ea8a	294	qemu_put_be64s(f, &s->limit);
e80cfcfc FB	295	qemu_put_be32s(f, &s->count);
e80cfcfc FB	296	qemu_put_be32s(f, &s->counthigh);
e80cfcfc	297	qemu_put_be32s(f, &s->reached);
115646b6	298	qemu_put_be32s(f, &s->running);
85e3023e BS	299	if (s->timer)
85e3023e BS	300	qemu_put_ptimer(f, s->timer);
e80cfcfc FB	301	}
	302
	303	static int slavio_timer_load(QEMUFile f, void opaque, int version_id)
	304	{
	305	SLAVIO_TIMERState *s = opaque;
3b46e624	306
85e3023e	307	if (version_id != 3)
e80cfcfc FB	308	return -EINVAL;
e80cfcfc FB	309
8d05ea8a	310	qemu_get_be64s(f, &s->limit);
e80cfcfc FB	311	qemu_get_be32s(f, &s->count);
e80cfcfc FB	312	qemu_get_be32s(f, &s->counthigh);
e80cfcfc	313	qemu_get_be32s(f, &s->reached);
115646b6	314	qemu_get_be32s(f, &s->running);
85e3023e BS	315	if (s->timer)
85e3023e BS	316	qemu_get_ptimer(f, s->timer);
8d05ea8a	317
e80cfcfc FB	318	return 0;
	319	}
	320
	321	static void slavio_timer_reset(void *opaque)
	322	{
	323	SLAVIO_TIMERState *s = opaque;
	324
3b4aa426	325	s->limit = 0;
e80cfcfc	326	s->count = 0;
e80cfcfc	327	s->reached = 0;
3b4aa426	328	s->slave_mode = 0;
85e3023e BS	329	if (!s->master \|\| s->slave_index < s->master->num_slaves) {
	330	ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
	331	ptimer_run(s->timer, 0);
	332	}
115646b6	333	s->running = 1;
d7edfd27	334	qemu_irq_lower(s->irq);
e80cfcfc FB	335	}
e80cfcfc FB	336
81732d19	337	static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
115646b6 BS	338	qemu_irq irq,
	339	SLAVIO_TIMERState *master,
	340	int slave_index)
e80cfcfc FB	341	{
	342	int slavio_timer_io_memory;
	343	SLAVIO_TIMERState *s;
8d05ea8a	344	QEMUBH *bh;
e80cfcfc FB	345
	346	s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
	347	if (!s)
81732d19	348	return s;
e80cfcfc	349	s->irq = irq;
115646b6 BS	350	s->master = master;
115646b6 BS	351	s->slave_index = slave_index;
85e3023e BS	352	if (!master \|\| slave_index < master->num_slaves) {
	353	bh = qemu_bh_new(slavio_timer_irq, s);
	354	s->timer = ptimer_init(bh);
	355	ptimer_set_period(s->timer, TIMER_PERIOD);
	356	}
e80cfcfc FB	357
e80cfcfc FB	358	slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
f930d07e	359	slavio_timer_mem_write, s);
115646b6	360	if (master)
d2c38b24 BS	361	cpu_register_physical_memory(addr, CPU_TIMER_SIZE,
d2c38b24 BS	362	slavio_timer_io_memory);
81732d19	363	else
d2c38b24 BS	364	cpu_register_physical_memory(addr, SYS_TIMER_SIZE,
d2c38b24 BS	365	slavio_timer_io_memory);
85e3023e	366	register_savevm("slavio_timer", addr, 3, slavio_timer_save,
d2c38b24	367	slavio_timer_load, s);
e80cfcfc FB	368	qemu_register_reset(slavio_timer_reset, s);
e80cfcfc FB	369	slavio_timer_reset(s);
81732d19 BS	370
	371	return s;
	372	}
	373
	374	void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
19f8e5dd	375	qemu_irq *cpu_irqs, unsigned int num_cpus)
81732d19 BS	376	{
	377	SLAVIO_TIMERState *master;
	378	unsigned int i;
	379
d2c38b24	380	master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0);
81732d19	381
19f8e5dd BS	382	master->num_slaves = num_cpus;
19f8e5dd BS	383
81732d19 BS	384	for (i = 0; i < MAX_CPUS; i++) {
81732d19 BS	385	master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
d2c38b24	386	CPU_TIMER_OFFSET(i),
115646b6	387	cpu_irqs[i], master, i);
81732d19	388	}
e80cfcfc	389	}