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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | #include "sysemu.h" | |
9fdf0c29 DG |
28 | #include "hw.h" |
29 | #include "elf.h" | |
30 | ||
31 | #include "hw/boards.h" | |
32 | #include "hw/ppc.h" | |
33 | #include "hw/loader.h" | |
34 | ||
35 | #include "hw/spapr.h" | |
4040ab72 | 36 | #include "hw/spapr_vio.h" |
b5cec4c5 | 37 | #include "hw/xics.h" |
9fdf0c29 DG |
38 | |
39 | #include <libfdt.h> | |
40 | ||
41 | #define KERNEL_LOAD_ADDR 0x00000000 | |
42 | #define INITRD_LOAD_ADDR 0x02800000 | |
43 | #define FDT_MAX_SIZE 0x10000 | |
39ac8455 | 44 | #define RTAS_MAX_SIZE 0x10000 |
9fdf0c29 DG |
45 | |
46 | #define TIMEBASE_FREQ 512000000ULL | |
47 | ||
48 | #define MAX_CPUS 32 | |
b5cec4c5 | 49 | #define XICS_IRQS 1024 |
9fdf0c29 DG |
50 | |
51 | sPAPREnvironment *spapr; | |
52 | ||
53 | static void *spapr_create_fdt(int *fdt_size, ram_addr_t ramsize, | |
54 | const char *cpu_model, CPUState *envs[], | |
55 | sPAPREnvironment *spapr, | |
56 | target_phys_addr_t initrd_base, | |
57 | target_phys_addr_t initrd_size, | |
f43e3525 | 58 | const char *kernel_cmdline, |
39ac8455 DG |
59 | target_phys_addr_t rtas_addr, |
60 | target_phys_addr_t rtas_size, | |
f43e3525 | 61 | long hash_shift) |
9fdf0c29 DG |
62 | { |
63 | void *fdt; | |
64 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) }; | |
65 | uint32_t start_prop = cpu_to_be32(initrd_base); | |
66 | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); | |
f43e3525 | 67 | uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)}; |
00dc738d | 68 | char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"; |
b5cec4c5 | 69 | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; |
9fdf0c29 DG |
70 | int i; |
71 | char *modelname; | |
4040ab72 | 72 | int ret; |
9fdf0c29 DG |
73 | |
74 | #define _FDT(exp) \ | |
75 | do { \ | |
76 | int ret = (exp); \ | |
77 | if (ret < 0) { \ | |
78 | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ | |
79 | #exp, fdt_strerror(ret)); \ | |
80 | exit(1); \ | |
81 | } \ | |
82 | } while (0) | |
83 | ||
84 | fdt = qemu_mallocz(FDT_MAX_SIZE); | |
85 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); | |
86 | ||
87 | _FDT((fdt_finish_reservemap(fdt))); | |
88 | ||
89 | /* Root node */ | |
90 | _FDT((fdt_begin_node(fdt, ""))); | |
91 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
92 | _FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR"))); | |
93 | ||
94 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); | |
95 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
96 | ||
97 | /* /chosen */ | |
98 | _FDT((fdt_begin_node(fdt, "chosen"))); | |
99 | ||
100 | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); | |
101 | _FDT((fdt_property(fdt, "linux,initrd-start", | |
102 | &start_prop, sizeof(start_prop)))); | |
103 | _FDT((fdt_property(fdt, "linux,initrd-end", | |
104 | &end_prop, sizeof(end_prop)))); | |
105 | ||
106 | _FDT((fdt_end_node(fdt))); | |
107 | ||
108 | /* memory node */ | |
109 | _FDT((fdt_begin_node(fdt, "memory@0"))); | |
110 | ||
111 | _FDT((fdt_property_string(fdt, "device_type", "memory"))); | |
112 | _FDT((fdt_property(fdt, "reg", | |
113 | mem_reg_property, sizeof(mem_reg_property)))); | |
114 | ||
115 | _FDT((fdt_end_node(fdt))); | |
116 | ||
117 | /* cpus */ | |
118 | _FDT((fdt_begin_node(fdt, "cpus"))); | |
119 | ||
120 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
121 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
122 | ||
123 | modelname = qemu_strdup(cpu_model); | |
124 | ||
125 | for (i = 0; i < strlen(modelname); i++) { | |
126 | modelname[i] = toupper(modelname[i]); | |
127 | } | |
128 | ||
129 | for (i = 0; i < smp_cpus; i++) { | |
130 | CPUState *env = envs[i]; | |
b5cec4c5 | 131 | uint32_t gserver_prop[] = {cpu_to_be32(i), 0}; /* HACK! */ |
9fdf0c29 DG |
132 | char *nodename; |
133 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
134 | 0xffffffff, 0xffffffff}; | |
135 | ||
136 | if (asprintf(&nodename, "%s@%x", modelname, i) < 0) { | |
137 | fprintf(stderr, "Allocation failure\n"); | |
138 | exit(1); | |
139 | } | |
140 | ||
141 | _FDT((fdt_begin_node(fdt, nodename))); | |
142 | ||
143 | free(nodename); | |
144 | ||
145 | _FDT((fdt_property_cell(fdt, "reg", i))); | |
146 | _FDT((fdt_property_string(fdt, "device_type", "cpu"))); | |
147 | ||
148 | _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); | |
149 | _FDT((fdt_property_cell(fdt, "dcache-block-size", | |
150 | env->dcache_line_size))); | |
151 | _FDT((fdt_property_cell(fdt, "icache-block-size", | |
152 | env->icache_line_size))); | |
153 | _FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ))); | |
154 | /* Hardcode CPU frequency for now. It's kind of arbitrary on | |
155 | * full emu, for kvm we should copy it from the host */ | |
156 | _FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000))); | |
157 | _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); | |
f43e3525 DG |
158 | _FDT((fdt_property(fdt, "ibm,pft-size", |
159 | pft_size_prop, sizeof(pft_size_prop)))); | |
9fdf0c29 DG |
160 | _FDT((fdt_property_string(fdt, "status", "okay"))); |
161 | _FDT((fdt_property(fdt, "64-bit", NULL, 0))); | |
b5cec4c5 DG |
162 | _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", i))); |
163 | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", | |
164 | gserver_prop, sizeof(gserver_prop)))); | |
9fdf0c29 DG |
165 | |
166 | if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) { | |
167 | _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", | |
168 | segs, sizeof(segs)))); | |
169 | } | |
170 | ||
171 | _FDT((fdt_end_node(fdt))); | |
172 | } | |
173 | ||
174 | qemu_free(modelname); | |
175 | ||
176 | _FDT((fdt_end_node(fdt))); | |
177 | ||
f43e3525 DG |
178 | /* RTAS */ |
179 | _FDT((fdt_begin_node(fdt, "rtas"))); | |
180 | ||
181 | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, | |
182 | sizeof(hypertas_prop)))); | |
183 | ||
184 | _FDT((fdt_end_node(fdt))); | |
185 | ||
b5cec4c5 DG |
186 | /* interrupt controller */ |
187 | _FDT((fdt_begin_node(fdt, "interrupt-controller@0"))); | |
188 | ||
189 | _FDT((fdt_property_string(fdt, "device_type", | |
190 | "PowerPC-External-Interrupt-Presentation"))); | |
191 | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); | |
192 | _FDT((fdt_property_cell(fdt, "reg", 0))); | |
193 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
194 | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", | |
195 | interrupt_server_ranges_prop, | |
196 | sizeof(interrupt_server_ranges_prop)))); | |
197 | ||
198 | _FDT((fdt_end_node(fdt))); | |
199 | ||
4040ab72 DG |
200 | /* vdevice */ |
201 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
202 | ||
203 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
204 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
205 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
206 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
b5cec4c5 DG |
207 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
208 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
4040ab72 DG |
209 | |
210 | _FDT((fdt_end_node(fdt))); | |
211 | ||
9fdf0c29 DG |
212 | _FDT((fdt_end_node(fdt))); /* close root node */ |
213 | _FDT((fdt_finish(fdt))); | |
214 | ||
4040ab72 DG |
215 | /* re-expand to allow for further tweaks */ |
216 | _FDT((fdt_open_into(fdt, fdt, FDT_MAX_SIZE))); | |
217 | ||
218 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); | |
219 | if (ret < 0) { | |
220 | fprintf(stderr, "couldn't setup vio devices in fdt\n"); | |
221 | exit(1); | |
222 | } | |
223 | ||
39ac8455 DG |
224 | /* RTAS */ |
225 | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); | |
226 | if (ret < 0) { | |
227 | fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); | |
228 | } | |
229 | ||
4040ab72 DG |
230 | _FDT((fdt_pack(fdt))); |
231 | ||
9fdf0c29 DG |
232 | *fdt_size = fdt_totalsize(fdt); |
233 | ||
234 | return fdt; | |
235 | } | |
236 | ||
237 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
238 | { | |
239 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
240 | } | |
241 | ||
242 | static void emulate_spapr_hypercall(CPUState *env) | |
243 | { | |
244 | env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); | |
245 | } | |
246 | ||
9fdf0c29 DG |
247 | /* pSeries LPAR / sPAPR hardware init */ |
248 | static void ppc_spapr_init(ram_addr_t ram_size, | |
249 | const char *boot_device, | |
250 | const char *kernel_filename, | |
251 | const char *kernel_cmdline, | |
252 | const char *initrd_filename, | |
253 | const char *cpu_model) | |
254 | { | |
255 | CPUState *envs[MAX_CPUS]; | |
f43e3525 | 256 | void *fdt, *htab; |
9fdf0c29 DG |
257 | int i; |
258 | ram_addr_t ram_offset; | |
39ac8455 | 259 | target_phys_addr_t fdt_addr, rtas_addr; |
9fdf0c29 | 260 | uint32_t kernel_base, initrd_base; |
39ac8455 | 261 | long kernel_size, initrd_size, htab_size, rtas_size; |
f43e3525 | 262 | long pteg_shift = 17; |
9fdf0c29 | 263 | int fdt_size; |
39ac8455 | 264 | char *filename; |
9fdf0c29 DG |
265 | |
266 | spapr = qemu_malloc(sizeof(*spapr)); | |
267 | cpu_ppc_hypercall = emulate_spapr_hypercall; | |
268 | ||
269 | /* We place the device tree just below either the top of RAM, or | |
270 | * 2GB, so that it can be processed with 32-bit code if | |
271 | * necessary */ | |
272 | fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE; | |
39ac8455 DG |
273 | /* RTAS goes just below that */ |
274 | rtas_addr = fdt_addr - RTAS_MAX_SIZE; | |
9fdf0c29 DG |
275 | |
276 | /* init CPUs */ | |
277 | if (cpu_model == NULL) { | |
278 | cpu_model = "POWER7"; | |
279 | } | |
280 | for (i = 0; i < smp_cpus; i++) { | |
281 | CPUState *env = cpu_init(cpu_model); | |
282 | ||
283 | if (!env) { | |
284 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
285 | exit(1); | |
286 | } | |
287 | /* Set time-base frequency to 512 MHz */ | |
288 | cpu_ppc_tb_init(env, TIMEBASE_FREQ); | |
289 | qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); | |
290 | ||
291 | env->hreset_vector = 0x60; | |
292 | env->hreset_excp_prefix = 0; | |
293 | env->gpr[3] = i; | |
294 | ||
295 | envs[i] = env; | |
296 | } | |
297 | ||
298 | /* allocate RAM */ | |
299 | ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size); | |
300 | cpu_register_physical_memory(0, ram_size, ram_offset); | |
301 | ||
f43e3525 DG |
302 | /* allocate hash page table. For now we always make this 16mb, |
303 | * later we should probably make it scale to the size of guest | |
304 | * RAM */ | |
305 | htab_size = 1ULL << (pteg_shift + 7); | |
306 | htab = qemu_mallocz(htab_size); | |
307 | ||
308 | for (i = 0; i < smp_cpus; i++) { | |
309 | envs[i]->external_htab = htab; | |
310 | envs[i]->htab_base = -1; | |
311 | envs[i]->htab_mask = htab_size - 1; | |
312 | } | |
313 | ||
39ac8455 DG |
314 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
315 | rtas_size = load_image_targphys(filename, rtas_addr, ram_size - rtas_addr); | |
316 | if (rtas_size < 0) { | |
317 | hw_error("qemu: could not load LPAR rtas '%s'\n", filename); | |
318 | exit(1); | |
319 | } | |
320 | qemu_free(filename); | |
321 | ||
b5cec4c5 DG |
322 | /* Set up Interrupt Controller */ |
323 | spapr->icp = xics_system_init(smp_cpus, envs, XICS_IRQS); | |
324 | ||
325 | /* Set up VIO bus */ | |
4040ab72 DG |
326 | spapr->vio_bus = spapr_vio_bus_init(); |
327 | ||
328 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { | |
329 | if (serial_hds[i]) { | |
330 | spapr_vty_create(spapr->vio_bus, i, serial_hds[i]); | |
331 | } | |
332 | } | |
9fdf0c29 DG |
333 | |
334 | if (kernel_filename) { | |
335 | uint64_t lowaddr = 0; | |
336 | ||
337 | kernel_base = KERNEL_LOAD_ADDR; | |
338 | ||
339 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, | |
340 | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); | |
341 | if (kernel_size < 0) { | |
342 | kernel_size = load_image_targphys(kernel_filename, kernel_base, | |
343 | ram_size - kernel_base); | |
344 | } | |
345 | if (kernel_size < 0) { | |
346 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
347 | kernel_filename); | |
348 | exit(1); | |
349 | } | |
350 | ||
351 | /* load initrd */ | |
352 | if (initrd_filename) { | |
353 | initrd_base = INITRD_LOAD_ADDR; | |
354 | initrd_size = load_image_targphys(initrd_filename, initrd_base, | |
355 | ram_size - initrd_base); | |
356 | if (initrd_size < 0) { | |
357 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
358 | initrd_filename); | |
359 | exit(1); | |
360 | } | |
361 | } else { | |
362 | initrd_base = 0; | |
363 | initrd_size = 0; | |
364 | } | |
9fdf0c29 DG |
365 | } else { |
366 | fprintf(stderr, "pSeries machine needs -kernel for now"); | |
367 | exit(1); | |
368 | } | |
369 | ||
370 | /* Prepare the device tree */ | |
371 | fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr, | |
f43e3525 | 372 | initrd_base, initrd_size, kernel_cmdline, |
39ac8455 | 373 | rtas_addr, rtas_size, pteg_shift + 7); |
9fdf0c29 DG |
374 | assert(fdt != NULL); |
375 | ||
376 | cpu_physical_memory_write(fdt_addr, fdt, fdt_size); | |
377 | ||
378 | qemu_free(fdt); | |
379 | ||
380 | envs[0]->gpr[3] = fdt_addr; | |
381 | envs[0]->gpr[5] = 0; | |
382 | envs[0]->hreset_vector = kernel_base; | |
383 | } | |
384 | ||
385 | static QEMUMachine spapr_machine = { | |
386 | .name = "pseries", | |
387 | .desc = "pSeries Logical Partition (PAPR compliant)", | |
388 | .init = ppc_spapr_init, | |
389 | .max_cpus = MAX_CPUS, | |
390 | .no_vga = 1, | |
391 | .no_parallel = 1, | |
392 | }; | |
393 | ||
394 | static void spapr_machine_init(void) | |
395 | { | |
396 | qemu_register_machine(&spapr_machine); | |
397 | } | |
398 | ||
399 | machine_init(spapr_machine_init); |