[qemu.git] / hw / spapr_pci.c

/*
 * QEMU sPAPR PCI host originated from Uninorth PCI host
 *
 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
 * Copyright (C) 2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pci.h"
#include "pci_host.h"
#include "hw/spapr.h"
#include "hw/spapr_pci.h"
#include "exec-memory.h"
#include <libfdt.h>

#include "hw/pci_internals.h"

static PCIDevice *find_dev(sPAPREnvironment *spapr,
                           uint64_t buid, uint32_t config_addr)
{
    DeviceState *qdev;
    int devfn = (config_addr >> 8) & 0xFF;
    sPAPRPHBState *phb;

    QLIST_FOREACH(phb, &spapr->phbs, list) {
        if (phb->buid != buid) {
            continue;
        }

        QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
            PCIDevice *dev = (PCIDevice *)qdev;
            if (dev->devfn == devfn) {
                return dev;
            }
        }
    }

    return NULL;
}

static uint32_t rtas_pci_cfgaddr(uint32_t arg)
{
    /* This handles the encoding of extended config space addresses */
    return ((arg >> 20) & 0xf00) | (arg & 0xff);
}

static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
                                   uint32_t addr, uint32_t size,
                                   target_ulong rets)
{
    PCIDevice *pci_dev;
    uint32_t val;

    if ((size != 1) && (size != 2) && (size != 4)) {
        /* access must be 1, 2 or 4 bytes */
        rtas_st(rets, 0, -1);
        return;
    }

    pci_dev = find_dev(spapr, buid, addr);
    addr = rtas_pci_cfgaddr(addr);

    if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
        /* Access must be to a valid device, within bounds and
         * naturally aligned */
        rtas_st(rets, 0, -1);
        return;
    }

    val = pci_host_config_read_common(pci_dev, addr,
                                      pci_config_size(pci_dev), size);

    rtas_st(rets, 0, 0);
    rtas_st(rets, 1, val);
}

static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
                                     uint32_t token, uint32_t nargs,
                                     target_ulong args,
                                     uint32_t nret, target_ulong rets)
{
    uint64_t buid;
    uint32_t size, addr;

    if ((nargs != 4) || (nret != 2)) {
        rtas_st(rets, 0, -1);
        return;
    }

    buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
    size = rtas_ld(args, 3);
    addr = rtas_ld(args, 0);

    finish_read_pci_config(spapr, buid, addr, size, rets);
}

static void rtas_read_pci_config(sPAPREnvironment *spapr,
                                 uint32_t token, uint32_t nargs,
                                 target_ulong args,
                                 uint32_t nret, target_ulong rets)
{
    uint32_t size, addr;

    if ((nargs != 2) || (nret != 2)) {
        rtas_st(rets, 0, -1);
        return;
    }

    size = rtas_ld(args, 1);
    addr = rtas_ld(args, 0);

    finish_read_pci_config(spapr, 0, addr, size, rets);
}

static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
                                    uint32_t addr, uint32_t size,
                                    uint32_t val, target_ulong rets)
{
    PCIDevice *pci_dev;

    if ((size != 1) && (size != 2) && (size != 4)) {
        /* access must be 1, 2 or 4 bytes */
        rtas_st(rets, 0, -1);
        return;
    }

    pci_dev = find_dev(spapr, buid, addr);
    addr = rtas_pci_cfgaddr(addr);

    if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
        /* Access must be to a valid device, within bounds and
         * naturally aligned */
        rtas_st(rets, 0, -1);
        return;
    }

    pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
                                 val, size);

    rtas_st(rets, 0, 0);
}

static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
                                      uint32_t token, uint32_t nargs,
                                      target_ulong args,
                                      uint32_t nret, target_ulong rets)
{
    uint64_t buid;
    uint32_t val, size, addr;

    if ((nargs != 5) || (nret != 1)) {
        rtas_st(rets, 0, -1);
        return;
    }

    buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
    val = rtas_ld(args, 4);
    size = rtas_ld(args, 3);
    addr = rtas_ld(args, 0);

    finish_write_pci_config(spapr, buid, addr, size, val, rets);
}

static void rtas_write_pci_config(sPAPREnvironment *spapr,
                                  uint32_t token, uint32_t nargs,
                                  target_ulong args,
                                  uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, -1);
        return;
    }


    val = rtas_ld(args, 2);
    size = rtas_ld(args, 1);
    addr = rtas_ld(args, 0);

    finish_write_pci_config(spapr, 0, addr, size, val, rets);
}

static int pci_spapr_swizzle(int slot, int pin)
{
    return (slot + pin) % PCI_NUM_PINS;
}

static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
{
    /*
     * Here we need to convert pci_dev + irq_num to some unique value
     * which is less than number of IRQs on the specific bus (4).  We
     * use standard PCI swizzling, that is (slot number + pin number)
     * % 4.
     */
    return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
}

static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
{
    /*
     * Here we use the number returned by pci_spapr_map_irq to find a
     * corresponding qemu_irq.
     */
    sPAPRPHBState *phb = opaque;

    qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
}

static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
                              unsigned size)
{
    switch (size) {
    case 1:
        return cpu_inb(addr);
    case 2:
        return cpu_inw(addr);
    case 4:
        return cpu_inl(addr);
    }
    assert(0);
}

static void spapr_io_write(void *opaque, target_phys_addr_t addr,
                           uint64_t data, unsigned size)
{
    switch (size) {
    case 1:
        cpu_outb(addr, data);
        return;
    case 2:
        cpu_outw(addr, data);
        return;
    case 4:
        cpu_outl(addr, data);
        return;
    }
    assert(0);
}

static const MemoryRegionOps spapr_io_ops = {
    .endianness = DEVICE_LITTLE_ENDIAN,
    .read = spapr_io_read,
    .write = spapr_io_write
};

/*
 * PHB PCI device
 */
static int spapr_phb_init(SysBusDevice *s)
{
    sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
    char *namebuf;
    int i;
    PCIBus *bus;

    phb->dtbusname = g_strdup_printf("pci@%" PRIx64, phb->buid);
    namebuf = alloca(strlen(phb->dtbusname) + 32);

    /* Initialize memory regions */
    sprintf(namebuf, "%s.mmio", phb->dtbusname);
    memory_region_init(&phb->memspace, namebuf, INT64_MAX);

    sprintf(namebuf, "%s.mmio-alias", phb->dtbusname);
    memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
                             SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size);
    memory_region_add_subregion(get_system_memory(), phb->mem_win_addr,
                                &phb->memwindow);

    /* On ppc, we only have MMIO no specific IO space from the CPU
     * perspective.  In theory we ought to be able to embed the PCI IO
     * memory region direction in the system memory space.  However,
     * if any of the IO BAR subregions use the old_portio mechanism,
     * that won't be processed properly unless accessed from the
     * system io address space.  This hack to bounce things via
     * system_io works around the problem until all the users of
     * old_portion are updated */
    sprintf(namebuf, "%s.io", phb->dtbusname);
    memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
    /* FIXME: fix to support multiple PHBs */
    memory_region_add_subregion(get_system_io(), 0, &phb->iospace);

    sprintf(namebuf, "%s.io-alias", phb->dtbusname);
    memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
                          namebuf, SPAPR_PCI_IO_WIN_SIZE);
    memory_region_add_subregion(get_system_memory(), phb->io_win_addr,
                                &phb->iowindow);

    bus = pci_register_bus(&phb->busdev.qdev,
                           phb->busname ? phb->busname : phb->dtbusname,
                           pci_spapr_set_irq, pci_spapr_map_irq, phb,
                           &phb->memspace, &phb->iospace,
                           PCI_DEVFN(0, 0), PCI_NUM_PINS);
    phb->host_state.bus = bus;

    QLIST_INSERT_HEAD(&spapr->phbs, phb, list);

    /* Initialize the LSI table */
    for (i = 0; i < PCI_NUM_PINS; i++) {
        qemu_irq qirq;
        uint32_t num;

        qirq = spapr_allocate_lsi(0, &num);
        if (!qirq) {
            return -1;
        }

        phb->lsi_table[i].dt_irq = num;
        phb->lsi_table[i].qirq = qirq;
    }

    return 0;
}

static Property spapr_phb_properties[] = {
    DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0),
    DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
    DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0),
    DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000),
    DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0),
    DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000),
    DEFINE_PROP_END_OF_LIST(),
};

static void spapr_phb_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sdc->init = spapr_phb_init;
    dc->props = spapr_phb_properties;

    spapr_rtas_register("read-pci-config", rtas_read_pci_config);
    spapr_rtas_register("write-pci-config", rtas_write_pci_config);
    spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
    spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
}

static TypeInfo spapr_phb_info = {
    .name          = "spapr-pci-host-bridge",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(sPAPRPHBState),
    .class_init    = spapr_phb_class_init,
};

void spapr_create_phb(sPAPREnvironment *spapr,
                      const char *busname, uint64_t buid,
                      uint64_t mem_win_addr, uint64_t mem_win_size,
                      uint64_t io_win_addr)
{
    DeviceState *dev;

    dev = qdev_create(NULL, spapr_phb_info.name);

    if (busname) {
        qdev_prop_set_string(dev, "busname", g_strdup(busname));
    }
    qdev_prop_set_uint64(dev, "buid", buid);
    qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr);
    qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size);
    qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr);

    qdev_init_nofail(dev);
}

/* Macros to operate with address in OF binding to PCI */
#define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
#define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
#define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
#define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
#define b_ss(x)         b_x((x), 24, 2) /* the space code */
#define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
#define b_ddddd(x)      b_x((x), 11, 5) /* device number */
#define b_fff(x)        b_x((x), 8, 3)  /* function number */
#define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */

int spapr_populate_pci_devices(sPAPRPHBState *phb,
                               uint32_t xics_phandle,
                               void *fdt)
{
    int bus_off, i, j;
    char nodename[256];
    uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
    struct {
        uint32_t hi;
        uint64_t child;
        uint64_t parent;
        uint64_t size;
    } __attribute__((packed)) ranges[] = {
        {
            cpu_to_be32(b_ss(1)), cpu_to_be64(0),
            cpu_to_be64(phb->io_win_addr),
            cpu_to_be64(memory_region_size(&phb->iospace)),
        },
        {
            cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
            cpu_to_be64(phb->mem_win_addr),
            cpu_to_be64(memory_region_size(&phb->memwindow)),
        },
    };
    uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
    uint32_t interrupt_map_mask[] = {
        cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
    uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];

    /* Start populating the FDT */
    sprintf(nodename, "pci@%" PRIx64, phb->buid);
    bus_off = fdt_add_subnode(fdt, 0, nodename);
    if (bus_off < 0) {
        return bus_off;
    }

#define _FDT(exp) \
    do { \
        int ret = (exp);                                           \
        if (ret < 0) {                                             \
            return ret;                                            \
        }                                                          \
    } while (0)

    /* Write PHB properties */
    _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
    _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
    _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
    _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
    _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
    _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
    _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));

    /* Build the interrupt-map, this must matches what is done
     * in pci_spapr_map_irq
     */
    _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
                     &interrupt_map_mask, sizeof(interrupt_map_mask)));
    for (i = 0; i < PCI_SLOT_MAX; i++) {
        for (j = 0; j < PCI_NUM_PINS; j++) {
            uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
            int lsi_num = pci_spapr_swizzle(i, j);

            irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
            irqmap[1] = 0;
            irqmap[2] = 0;
            irqmap[3] = cpu_to_be32(j+1);
            irqmap[4] = cpu_to_be32(xics_phandle);
            irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].dt_irq);
            irqmap[6] = cpu_to_be32(0x8);
        }
    }
    /* Write interrupt map */
    _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
                     sizeof(interrupt_map)));

    return 0;
}

static void register_types(void)
{
    type_register_static(&spapr_phb_info);
}
type_init(register_types)
Commit	Line	Data
3384f95c DG	1	/*
	2	* QEMU sPAPR PCI host originated from Uninorth PCI host
	3	*
	4	* Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
	5	* Copyright (C) 2011 David Gibson, IBM Corporation.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "hw.h"
	26	#include "pci.h"
	27	#include "pci_host.h"
	28	#include "hw/spapr.h"
	29	#include "hw/spapr_pci.h"
	30	#include "exec-memory.h"
	31	#include <libfdt.h>
	32
	33	#include "hw/pci_internals.h"
	34
3384f95c DG	35	static PCIDevice find_dev(sPAPREnvironment spapr,
	36	uint64_t buid, uint32_t config_addr)
	37	{
	38	DeviceState *qdev;
	39	int devfn = (config_addr >> 8) & 0xFF;
	40	sPAPRPHBState *phb;
	41
	42	QLIST_FOREACH(phb, &spapr->phbs, list) {
	43	if (phb->buid != buid) {
	44	continue;
	45	}
	46
3a26360d	47	QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
3384f95c DG	48	PCIDevice dev = (PCIDevice )qdev;
	49	if (dev->devfn == devfn) {
	50	return dev;
	51	}
	52	}
	53	}
	54
	55	return NULL;
	56	}
	57
3f7565c9 BH	58	static uint32_t rtas_pci_cfgaddr(uint32_t arg)
3f7565c9 BH	59	{
92615a5a	60	/* This handles the encoding of extended config space addresses */
3f7565c9 BH	61	return ((arg >> 20) & 0xf00) \| (arg & 0xff);
	62	}
	63
92615a5a DG	64	static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
	65	uint32_t addr, uint32_t size,
	66	target_ulong rets)
88045ac5	67	{
92615a5a DG	68	PCIDevice *pci_dev;
	69	uint32_t val;
	70
	71	if ((size != 1) && (size != 2) && (size != 4)) {
	72	/* access must be 1, 2 or 4 bytes */
	73	rtas_st(rets, 0, -1);
	74	return;
88045ac5	75	}
88045ac5	76
92615a5a DG	77	pci_dev = find_dev(spapr, buid, addr);
	78	addr = rtas_pci_cfgaddr(addr);
	79
	80	if (!pci_dev \|\| (addr % size) \|\| (addr >= pci_config_size(pci_dev))) {
	81	/* Access must be to a valid device, within bounds and
	82	* naturally aligned */
	83	rtas_st(rets, 0, -1);
	84	return;
88045ac5	85	}
92615a5a DG	86
	87	val = pci_host_config_read_common(pci_dev, addr,
	88	pci_config_size(pci_dev), size);
	89
	90	rtas_st(rets, 0, 0);
	91	rtas_st(rets, 1, val);
88045ac5 AG	92	}
88045ac5 AG	93
3384f95c DG	94	static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
	95	uint32_t token, uint32_t nargs,
	96	target_ulong args,
	97	uint32_t nret, target_ulong rets)
	98	{
92615a5a DG	99	uint64_t buid;
92615a5a DG	100	uint32_t size, addr;
3384f95c	101
92615a5a	102	if ((nargs != 4) \|\| (nret != 2)) {
3384f95c DG	103	rtas_st(rets, 0, -1);
	104	return;
	105	}
92615a5a DG	106
92615a5a DG	107	buid = ((uint64_t)rtas_ld(args, 1) << 32) \| rtas_ld(args, 2);
3384f95c	108	size = rtas_ld(args, 3);
92615a5a DG	109	addr = rtas_ld(args, 0);
	110
	111	finish_read_pci_config(spapr, buid, addr, size, rets);
3384f95c DG	112	}
	113
	114	static void rtas_read_pci_config(sPAPREnvironment *spapr,
	115	uint32_t token, uint32_t nargs,
	116	target_ulong args,
	117	uint32_t nret, target_ulong rets)
	118	{
92615a5a	119	uint32_t size, addr;
3384f95c	120
92615a5a	121	if ((nargs != 2) \|\| (nret != 2)) {
3384f95c DG	122	rtas_st(rets, 0, -1);
	123	return;
	124	}
92615a5a	125
3384f95c	126	size = rtas_ld(args, 1);
92615a5a DG	127	addr = rtas_ld(args, 0);
	128
	129	finish_read_pci_config(spapr, 0, addr, size, rets);
	130	}
	131
	132	static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
	133	uint32_t addr, uint32_t size,
	134	uint32_t val, target_ulong rets)
	135	{
	136	PCIDevice *pci_dev;
	137
	138	if ((size != 1) && (size != 2) && (size != 4)) {
	139	/* access must be 1, 2 or 4 bytes */
	140	rtas_st(rets, 0, -1);
	141	return;
	142	}
	143
	144	pci_dev = find_dev(spapr, buid, addr);
	145	addr = rtas_pci_cfgaddr(addr);
	146
	147	if (!pci_dev \|\| (addr % size) \|\| (addr >= pci_config_size(pci_dev))) {
	148	/* Access must be to a valid device, within bounds and
	149	* naturally aligned */
	150	rtas_st(rets, 0, -1);
	151	return;
	152	}
	153
	154	pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
	155	val, size);
	156
3384f95c	157	rtas_st(rets, 0, 0);
3384f95c DG	158	}
	159
	160	static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
	161	uint32_t token, uint32_t nargs,
	162	target_ulong args,
	163	uint32_t nret, target_ulong rets)
	164	{
92615a5a	165	uint64_t buid;
3384f95c	166	uint32_t val, size, addr;
3384f95c	167
92615a5a	168	if ((nargs != 5) \|\| (nret != 1)) {
3384f95c DG	169	rtas_st(rets, 0, -1);
	170	return;
	171	}
92615a5a DG	172
92615a5a DG	173	buid = ((uint64_t)rtas_ld(args, 1) << 32) \| rtas_ld(args, 2);
3384f95c DG	174	val = rtas_ld(args, 4);
3384f95c DG	175	size = rtas_ld(args, 3);
92615a5a DG	176	addr = rtas_ld(args, 0);
	177
	178	finish_write_pci_config(spapr, buid, addr, size, val, rets);
3384f95c DG	179	}
	180
	181	static void rtas_write_pci_config(sPAPREnvironment *spapr,
	182	uint32_t token, uint32_t nargs,
	183	target_ulong args,
	184	uint32_t nret, target_ulong rets)
	185	{
	186	uint32_t val, size, addr;
3384f95c	187
92615a5a	188	if ((nargs != 3) \|\| (nret != 1)) {
3384f95c DG	189	rtas_st(rets, 0, -1);
	190	return;
	191	}
92615a5a DG	192
92615a5a DG	193
3384f95c DG	194	val = rtas_ld(args, 2);
3384f95c DG	195	size = rtas_ld(args, 1);
92615a5a DG	196	addr = rtas_ld(args, 0);
	197
	198	finish_write_pci_config(spapr, 0, addr, size, val, rets);
3384f95c DG	199	}
3384f95c DG	200
7fb0bd34 DG	201	static int pci_spapr_swizzle(int slot, int pin)
	202	{
	203	return (slot + pin) % PCI_NUM_PINS;
	204	}
	205
3384f95c DG	206	static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
	207	{
	208	/*
	209	* Here we need to convert pci_dev + irq_num to some unique value
7fb0bd34 DG	210	* which is less than number of IRQs on the specific bus (4). We
	211	* use standard PCI swizzling, that is (slot number + pin number)
	212	* % 4.
3384f95c	213	*/
7fb0bd34	214	return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
3384f95c DG	215	}
	216
	217	static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
	218	{
	219	/*
	220	* Here we use the number returned by pci_spapr_map_irq to find a
	221	* corresponding qemu_irq.
	222	*/
	223	sPAPRPHBState *phb = opaque;
	224
	225	qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
	226	}
	227
3384f95c DG	228	static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
	229	unsigned size)
	230	{
	231	switch (size) {
	232	case 1:
	233	return cpu_inb(addr);
	234	case 2:
	235	return cpu_inw(addr);
	236	case 4:
	237	return cpu_inl(addr);
	238	}
	239	assert(0);
	240	}
	241
	242	static void spapr_io_write(void *opaque, target_phys_addr_t addr,
	243	uint64_t data, unsigned size)
	244	{
	245	switch (size) {
	246	case 1:
	247	cpu_outb(addr, data);
	248	return;
	249	case 2:
	250	cpu_outw(addr, data);
	251	return;
	252	case 4:
	253	cpu_outl(addr, data);
	254	return;
	255	}
	256	assert(0);
	257	}
	258
a348f108	259	static const MemoryRegionOps spapr_io_ops = {
3384f95c DG	260	.endianness = DEVICE_LITTLE_ENDIAN,
	261	.read = spapr_io_read,
	262	.write = spapr_io_write
	263	};
	264
298a9710 DG	265	/*
	266	* PHB PCI device
	267	*/
	268	static int spapr_phb_init(SysBusDevice *s)
3384f95c	269	{
298a9710 DG	270	sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
	271	char *namebuf;
	272	int i;
3384f95c	273	PCIBus *bus;
3384f95c	274
298a9710 DG	275	phb->dtbusname = g_strdup_printf("pci@%" PRIx64, phb->buid);
298a9710 DG	276	namebuf = alloca(strlen(phb->dtbusname) + 32);
3384f95c	277
298a9710 DG	278	/* Initialize memory regions */
298a9710 DG	279	sprintf(namebuf, "%s.mmio", phb->dtbusname);
3384f95c DG	280	memory_region_init(&phb->memspace, namebuf, INT64_MAX);
3384f95c DG	281
298a9710	282	sprintf(namebuf, "%s.mmio-alias", phb->dtbusname);
3384f95c	283	memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
298a9710 DG	284	SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size);
298a9710 DG	285	memory_region_add_subregion(get_system_memory(), phb->mem_win_addr,
3384f95c DG	286	&phb->memwindow);
3384f95c DG	287
3384f95c DG	288	/* On ppc, we only have MMIO no specific IO space from the CPU
	289	* perspective. In theory we ought to be able to embed the PCI IO
	290	* memory region direction in the system memory space. However,
	291	* if any of the IO BAR subregions use the old_portio mechanism,
	292	* that won't be processed properly unless accessed from the
	293	* system io address space. This hack to bounce things via
	294	* system_io works around the problem until all the users of
	295	* old_portion are updated */
298a9710	296	sprintf(namebuf, "%s.io", phb->dtbusname);
3384f95c DG	297	memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
	298	/* FIXME: fix to support multiple PHBs */
	299	memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
	300
298a9710	301	sprintf(namebuf, "%s.io-alias", phb->dtbusname);
3384f95c DG	302	memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
3384f95c DG	303	namebuf, SPAPR_PCI_IO_WIN_SIZE);
298a9710	304	memory_region_add_subregion(get_system_memory(), phb->io_win_addr,
3384f95c DG	305	&phb->iowindow);
3384f95c DG	306
298a9710 DG	307	bus = pci_register_bus(&phb->busdev.qdev,
	308	phb->busname ? phb->busname : phb->dtbusname,
	309	pci_spapr_set_irq, pci_spapr_map_irq, phb,
	310	&phb->memspace, &phb->iospace,
7fb0bd34	311	PCI_DEVFN(0, 0), PCI_NUM_PINS);
298a9710 DG	312	phb->host_state.bus = bus;
	313
	314	QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
	315
	316	/* Initialize the LSI table */
7fb0bd34	317	for (i = 0; i < PCI_NUM_PINS; i++) {
298a9710 DG	318	qemu_irq qirq;
	319	uint32_t num;
	320
	321	qirq = spapr_allocate_lsi(0, &num);
	322	if (!qirq) {
	323	return -1;
	324	}
	325
	326	phb->lsi_table[i].dt_irq = num;
	327	phb->lsi_table[i].qirq = qirq;
	328	}
	329
	330	return 0;
	331	}
	332
	333	static Property spapr_phb_properties[] = {
	334	DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0),
	335	DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
	336	DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0),
	337	DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000),
	338	DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0),
	339	DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000),
	340	DEFINE_PROP_END_OF_LIST(),
	341	};
	342
	343	static void spapr_phb_class_init(ObjectClass klass, void data)
	344	{
	345	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
	346	DeviceClass *dc = DEVICE_CLASS(klass);
	347
	348	sdc->init = spapr_phb_init;
	349	dc->props = spapr_phb_properties;
3384f95c DG	350
	351	spapr_rtas_register("read-pci-config", rtas_read_pci_config);
	352	spapr_rtas_register("write-pci-config", rtas_write_pci_config);
	353	spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
	354	spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
298a9710	355	}
3384f95c	356
298a9710 DG	357	static TypeInfo spapr_phb_info = {
	358	.name = "spapr-pci-host-bridge",
	359	.parent = TYPE_SYS_BUS_DEVICE,
	360	.instance_size = sizeof(sPAPRPHBState),
	361	.class_init = spapr_phb_class_init,
	362	};
	363
	364	void spapr_create_phb(sPAPREnvironment *spapr,
	365	const char *busname, uint64_t buid,
	366	uint64_t mem_win_addr, uint64_t mem_win_size,
	367	uint64_t io_win_addr)
	368	{
	369	DeviceState *dev;
	370
	371	dev = qdev_create(NULL, spapr_phb_info.name);
3384f95c	372
298a9710 DG	373	if (busname) {
	374	qdev_prop_set_string(dev, "busname", g_strdup(busname));
	375	}
	376	qdev_prop_set_uint64(dev, "buid", buid);
	377	qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr);
	378	qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size);
	379	qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr);
	380
	381	qdev_init_nofail(dev);
3384f95c DG	382	}
	383
	384	/* Macros to operate with address in OF binding to PCI */
	385	#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
	386	#define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
	387	#define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
	388	#define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
	389	#define b_ss(x) b_x((x), 24, 2) /* the space code */
	390	#define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
	391	#define b_ddddd(x) b_x((x), 11, 5) /* device number */
	392	#define b_fff(x) b_x((x), 8, 3) /* function number */
	393	#define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
	394
3384f95c DG	395	int spapr_populate_pci_devices(sPAPRPHBState *phb,
	396	uint32_t xics_phandle,
	397	void *fdt)
	398	{
7fb0bd34	399	int bus_off, i, j;
3384f95c	400	char nodename[256];
3384f95c DG	401	uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
	402	struct {
	403	uint32_t hi;
	404	uint64_t child;
	405	uint64_t parent;
	406	uint64_t size;
	407	} __attribute__((packed)) ranges[] = {
	408	{
	409	cpu_to_be32(b_ss(1)), cpu_to_be64(0),
	410	cpu_to_be64(phb->io_win_addr),
	411	cpu_to_be64(memory_region_size(&phb->iospace)),
	412	},
	413	{
	414	cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
	415	cpu_to_be64(phb->mem_win_addr),
	416	cpu_to_be64(memory_region_size(&phb->memwindow)),
	417	},
	418	};
	419	uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
	420	uint32_t interrupt_map_mask[] = {
7fb0bd34 DG	421	cpu_to_be32(b_ddddd(-1)\|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
7fb0bd34 DG	422	uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
3384f95c DG	423
	424	/* Start populating the FDT */
	425	sprintf(nodename, "pci@%" PRIx64, phb->buid);
	426	bus_off = fdt_add_subnode(fdt, 0, nodename);
	427	if (bus_off < 0) {
	428	return bus_off;
	429	}
	430
	431	#define _FDT(exp) \
	432	do { \
	433	int ret = (exp); \
	434	if (ret < 0) { \
	435	return ret; \
	436	} \
	437	} while (0)
	438
	439	/* Write PHB properties */
	440	_FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
	441	_FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
	442	_FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
	443	_FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
	444	_FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
	445	_FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
	446	_FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
	447	_FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
	448	_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
3f7565c9	449	_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
3384f95c	450
4d8d5467 BH	451	/* Build the interrupt-map, this must matches what is done
	452	* in pci_spapr_map_irq
	453	*/
	454	_FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
	455	&interrupt_map_mask, sizeof(interrupt_map_mask)));
7fb0bd34 DG	456	for (i = 0; i < PCI_SLOT_MAX; i++) {
	457	for (j = 0; j < PCI_NUM_PINS; j++) {
	458	uint32_t irqmap = interrupt_map[iPCI_NUM_PINS + j];
	459	int lsi_num = pci_spapr_swizzle(i, j);
	460
	461	irqmap[0] = cpu_to_be32(b_ddddd(i)\|b_fff(0));
	462	irqmap[1] = 0;
	463	irqmap[2] = 0;
	464	irqmap[3] = cpu_to_be32(j+1);
	465	irqmap[4] = cpu_to_be32(xics_phandle);
	466	irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].dt_irq);
	467	irqmap[6] = cpu_to_be32(0x8);
	468	}
3384f95c	469	}
3384f95c DG	470	/* Write interrupt map */
3384f95c DG	471	_FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
7fb0bd34	472	sizeof(interrupt_map)));
3384f95c DG	473
	474	return 0;
	475	}
298a9710 DG	476
	477	static void register_types(void)
	478	{
	479	type_register_static(&spapr_phb_info);
	480	}
	481	type_init(register_types)