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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | #include "hw.h" | |
26 | #include "pci.h" | |
0ee2c058 AK |
27 | #include "msi.h" |
28 | #include "msix.h" | |
3384f95c DG |
29 | #include "pci_host.h" |
30 | #include "hw/spapr.h" | |
31 | #include "hw/spapr_pci.h" | |
32 | #include "exec-memory.h" | |
33 | #include <libfdt.h> | |
a2950fb6 | 34 | #include "trace.h" |
3384f95c DG |
35 | |
36 | #include "hw/pci_internals.h" | |
37 | ||
0ee2c058 AK |
38 | /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ |
39 | #define RTAS_QUERY_FN 0 | |
40 | #define RTAS_CHANGE_FN 1 | |
41 | #define RTAS_RESET_FN 2 | |
42 | #define RTAS_CHANGE_MSI_FN 3 | |
43 | #define RTAS_CHANGE_MSIX_FN 4 | |
44 | ||
45 | /* Interrupt types to return on RTAS_CHANGE_* */ | |
46 | #define RTAS_TYPE_MSI 1 | |
47 | #define RTAS_TYPE_MSIX 2 | |
48 | ||
9894c5d4 | 49 | static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid) |
3384f95c | 50 | { |
3384f95c DG |
51 | sPAPRPHBState *phb; |
52 | ||
53 | QLIST_FOREACH(phb, &spapr->phbs, list) { | |
54 | if (phb->buid != buid) { | |
55 | continue; | |
56 | } | |
9894c5d4 AK |
57 | return phb; |
58 | } | |
59 | ||
60 | return NULL; | |
61 | } | |
62 | ||
63 | static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid, | |
64 | uint32_t config_addr) | |
65 | { | |
66 | sPAPRPHBState *phb = find_phb(spapr, buid); | |
67 | BusChild *kid; | |
68 | int devfn = (config_addr >> 8) & 0xFF; | |
69 | ||
70 | if (!phb) { | |
71 | return NULL; | |
72 | } | |
3384f95c | 73 | |
9894c5d4 AK |
74 | QTAILQ_FOREACH(kid, &phb->host_state.bus->qbus.children, sibling) { |
75 | PCIDevice *dev = (PCIDevice *)kid->child; | |
76 | if (dev->devfn == devfn) { | |
77 | return dev; | |
3384f95c DG |
78 | } |
79 | } | |
80 | ||
81 | return NULL; | |
82 | } | |
83 | ||
3f7565c9 BH |
84 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
85 | { | |
92615a5a | 86 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
87 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
88 | } | |
89 | ||
92615a5a DG |
90 | static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, |
91 | uint32_t addr, uint32_t size, | |
92 | target_ulong rets) | |
88045ac5 | 93 | { |
92615a5a DG |
94 | PCIDevice *pci_dev; |
95 | uint32_t val; | |
96 | ||
97 | if ((size != 1) && (size != 2) && (size != 4)) { | |
98 | /* access must be 1, 2 or 4 bytes */ | |
99 | rtas_st(rets, 0, -1); | |
100 | return; | |
88045ac5 | 101 | } |
88045ac5 | 102 | |
92615a5a DG |
103 | pci_dev = find_dev(spapr, buid, addr); |
104 | addr = rtas_pci_cfgaddr(addr); | |
105 | ||
106 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
107 | /* Access must be to a valid device, within bounds and | |
108 | * naturally aligned */ | |
109 | rtas_st(rets, 0, -1); | |
110 | return; | |
88045ac5 | 111 | } |
92615a5a DG |
112 | |
113 | val = pci_host_config_read_common(pci_dev, addr, | |
114 | pci_config_size(pci_dev), size); | |
115 | ||
116 | rtas_st(rets, 0, 0); | |
117 | rtas_st(rets, 1, val); | |
88045ac5 AG |
118 | } |
119 | ||
3384f95c DG |
120 | static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr, |
121 | uint32_t token, uint32_t nargs, | |
122 | target_ulong args, | |
123 | uint32_t nret, target_ulong rets) | |
124 | { | |
92615a5a DG |
125 | uint64_t buid; |
126 | uint32_t size, addr; | |
3384f95c | 127 | |
92615a5a | 128 | if ((nargs != 4) || (nret != 2)) { |
3384f95c DG |
129 | rtas_st(rets, 0, -1); |
130 | return; | |
131 | } | |
92615a5a DG |
132 | |
133 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c | 134 | size = rtas_ld(args, 3); |
92615a5a DG |
135 | addr = rtas_ld(args, 0); |
136 | ||
137 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
138 | } |
139 | ||
140 | static void rtas_read_pci_config(sPAPREnvironment *spapr, | |
141 | uint32_t token, uint32_t nargs, | |
142 | target_ulong args, | |
143 | uint32_t nret, target_ulong rets) | |
144 | { | |
92615a5a | 145 | uint32_t size, addr; |
3384f95c | 146 | |
92615a5a | 147 | if ((nargs != 2) || (nret != 2)) { |
3384f95c DG |
148 | rtas_st(rets, 0, -1); |
149 | return; | |
150 | } | |
92615a5a | 151 | |
3384f95c | 152 | size = rtas_ld(args, 1); |
92615a5a DG |
153 | addr = rtas_ld(args, 0); |
154 | ||
155 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
156 | } | |
157 | ||
158 | static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid, | |
159 | uint32_t addr, uint32_t size, | |
160 | uint32_t val, target_ulong rets) | |
161 | { | |
162 | PCIDevice *pci_dev; | |
163 | ||
164 | if ((size != 1) && (size != 2) && (size != 4)) { | |
165 | /* access must be 1, 2 or 4 bytes */ | |
166 | rtas_st(rets, 0, -1); | |
167 | return; | |
168 | } | |
169 | ||
170 | pci_dev = find_dev(spapr, buid, addr); | |
171 | addr = rtas_pci_cfgaddr(addr); | |
172 | ||
173 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
174 | /* Access must be to a valid device, within bounds and | |
175 | * naturally aligned */ | |
176 | rtas_st(rets, 0, -1); | |
177 | return; | |
178 | } | |
179 | ||
180 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
181 | val, size); | |
182 | ||
3384f95c | 183 | rtas_st(rets, 0, 0); |
3384f95c DG |
184 | } |
185 | ||
186 | static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr, | |
187 | uint32_t token, uint32_t nargs, | |
188 | target_ulong args, | |
189 | uint32_t nret, target_ulong rets) | |
190 | { | |
92615a5a | 191 | uint64_t buid; |
3384f95c | 192 | uint32_t val, size, addr; |
3384f95c | 193 | |
92615a5a | 194 | if ((nargs != 5) || (nret != 1)) { |
3384f95c DG |
195 | rtas_st(rets, 0, -1); |
196 | return; | |
197 | } | |
92615a5a DG |
198 | |
199 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c DG |
200 | val = rtas_ld(args, 4); |
201 | size = rtas_ld(args, 3); | |
92615a5a DG |
202 | addr = rtas_ld(args, 0); |
203 | ||
204 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
205 | } |
206 | ||
207 | static void rtas_write_pci_config(sPAPREnvironment *spapr, | |
208 | uint32_t token, uint32_t nargs, | |
209 | target_ulong args, | |
210 | uint32_t nret, target_ulong rets) | |
211 | { | |
212 | uint32_t val, size, addr; | |
3384f95c | 213 | |
92615a5a | 214 | if ((nargs != 3) || (nret != 1)) { |
3384f95c DG |
215 | rtas_st(rets, 0, -1); |
216 | return; | |
217 | } | |
92615a5a DG |
218 | |
219 | ||
3384f95c DG |
220 | val = rtas_ld(args, 2); |
221 | size = rtas_ld(args, 1); | |
92615a5a DG |
222 | addr = rtas_ld(args, 0); |
223 | ||
224 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
225 | } |
226 | ||
0ee2c058 AK |
227 | /* |
228 | * Find an entry with config_addr or returns the empty one if not found AND | |
229 | * alloc_new is set. | |
230 | * At the moment the msi_table entries are never released so there is | |
231 | * no point to look till the end of the list if we need to find the free entry. | |
232 | */ | |
233 | static int spapr_msicfg_find(sPAPRPHBState *phb, uint32_t config_addr, | |
234 | bool alloc_new) | |
235 | { | |
236 | int i; | |
237 | ||
238 | for (i = 0; i < SPAPR_MSIX_MAX_DEVS; ++i) { | |
239 | if (!phb->msi_table[i].nvec) { | |
240 | break; | |
241 | } | |
242 | if (phb->msi_table[i].config_addr == config_addr) { | |
243 | return i; | |
244 | } | |
245 | } | |
246 | if ((i < SPAPR_MSIX_MAX_DEVS) && alloc_new) { | |
247 | trace_spapr_pci_msi("Allocating new MSI config", i, config_addr); | |
248 | return i; | |
249 | } | |
250 | ||
251 | return -1; | |
252 | } | |
253 | ||
254 | /* | |
255 | * Set MSI/MSIX message data. | |
256 | * This is required for msi_notify()/msix_notify() which | |
257 | * will write at the addresses via spapr_msi_write(). | |
258 | */ | |
259 | static void spapr_msi_setmsg(PCIDevice *pdev, target_phys_addr_t addr, | |
260 | bool msix, unsigned req_num) | |
261 | { | |
262 | unsigned i; | |
263 | MSIMessage msg = { .address = addr, .data = 0 }; | |
264 | ||
265 | if (!msix) { | |
266 | msi_set_message(pdev, msg); | |
267 | trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); | |
268 | return; | |
269 | } | |
270 | ||
271 | for (i = 0; i < req_num; ++i) { | |
272 | msg.address = addr | (i << 2); | |
273 | msix_set_message(pdev, i, msg); | |
274 | trace_spapr_pci_msi_setup(pdev->name, i, msg.address); | |
275 | } | |
276 | } | |
277 | ||
278 | static void rtas_ibm_change_msi(sPAPREnvironment *spapr, | |
279 | uint32_t token, uint32_t nargs, | |
280 | target_ulong args, uint32_t nret, | |
281 | target_ulong rets) | |
282 | { | |
283 | uint32_t config_addr = rtas_ld(args, 0); | |
284 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
285 | unsigned int func = rtas_ld(args, 3); | |
286 | unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ | |
287 | unsigned int seq_num = rtas_ld(args, 5); | |
288 | unsigned int ret_intr_type; | |
289 | int ndev, irq; | |
290 | sPAPRPHBState *phb = NULL; | |
291 | PCIDevice *pdev = NULL; | |
292 | ||
293 | switch (func) { | |
294 | case RTAS_CHANGE_MSI_FN: | |
295 | case RTAS_CHANGE_FN: | |
296 | ret_intr_type = RTAS_TYPE_MSI; | |
297 | break; | |
298 | case RTAS_CHANGE_MSIX_FN: | |
299 | ret_intr_type = RTAS_TYPE_MSIX; | |
300 | break; | |
301 | default: | |
302 | fprintf(stderr, "rtas_ibm_change_msi(%u) is not implemented\n", func); | |
303 | rtas_st(rets, 0, -3); /* Parameter error */ | |
304 | return; | |
305 | } | |
306 | ||
307 | /* Fins sPAPRPHBState */ | |
308 | phb = find_phb(spapr, buid); | |
309 | if (phb) { | |
310 | pdev = find_dev(spapr, buid, config_addr); | |
311 | } | |
312 | if (!phb || !pdev) { | |
313 | rtas_st(rets, 0, -3); /* Parameter error */ | |
314 | return; | |
315 | } | |
316 | ||
317 | /* Releasing MSIs */ | |
318 | if (!req_num) { | |
319 | ndev = spapr_msicfg_find(phb, config_addr, false); | |
320 | if (ndev < 0) { | |
321 | trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr); | |
322 | rtas_st(rets, 0, -1); /* Hardware error */ | |
323 | return; | |
324 | } | |
325 | trace_spapr_pci_msi("Released MSIs", ndev, config_addr); | |
326 | rtas_st(rets, 0, 0); | |
327 | rtas_st(rets, 1, 0); | |
328 | return; | |
329 | } | |
330 | ||
331 | /* Enabling MSI */ | |
332 | ||
333 | /* Find a device number in the map to add or reuse the existing one */ | |
334 | ndev = spapr_msicfg_find(phb, config_addr, true); | |
335 | if (ndev >= SPAPR_MSIX_MAX_DEVS || ndev < 0) { | |
336 | fprintf(stderr, "No free entry for a new MSI device\n"); | |
337 | rtas_st(rets, 0, -1); /* Hardware error */ | |
338 | return; | |
339 | } | |
340 | trace_spapr_pci_msi("Configuring MSI", ndev, config_addr); | |
341 | ||
342 | /* Check if there is an old config and MSI number has not changed */ | |
343 | if (phb->msi_table[ndev].nvec && (req_num != phb->msi_table[ndev].nvec)) { | |
344 | /* Unexpected behaviour */ | |
345 | fprintf(stderr, "Cannot reuse MSI config for device#%d", ndev); | |
346 | rtas_st(rets, 0, -1); /* Hardware error */ | |
347 | return; | |
348 | } | |
349 | ||
350 | /* There is no cached config, allocate MSIs */ | |
351 | if (!phb->msi_table[ndev].nvec) { | |
352 | irq = spapr_allocate_irq_block(req_num, XICS_MSI); | |
353 | if (irq < 0) { | |
354 | fprintf(stderr, "Cannot allocate MSIs for device#%d", ndev); | |
355 | rtas_st(rets, 0, -1); /* Hardware error */ | |
356 | return; | |
357 | } | |
358 | phb->msi_table[ndev].irq = irq; | |
359 | phb->msi_table[ndev].nvec = req_num; | |
360 | phb->msi_table[ndev].config_addr = config_addr; | |
361 | } | |
362 | ||
363 | /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ | |
364 | spapr_msi_setmsg(pdev, phb->msi_win_addr | (ndev << 16), | |
365 | ret_intr_type == RTAS_TYPE_MSIX, req_num); | |
366 | ||
367 | rtas_st(rets, 0, 0); | |
368 | rtas_st(rets, 1, req_num); | |
369 | rtas_st(rets, 2, ++seq_num); | |
370 | rtas_st(rets, 3, ret_intr_type); | |
371 | ||
372 | trace_spapr_pci_rtas_ibm_change_msi(func, req_num); | |
373 | } | |
374 | ||
375 | static void rtas_ibm_query_interrupt_source_number(sPAPREnvironment *spapr, | |
376 | uint32_t token, | |
377 | uint32_t nargs, | |
378 | target_ulong args, | |
379 | uint32_t nret, | |
380 | target_ulong rets) | |
381 | { | |
382 | uint32_t config_addr = rtas_ld(args, 0); | |
383 | uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
384 | unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); | |
385 | int ndev; | |
386 | sPAPRPHBState *phb = NULL; | |
387 | ||
388 | /* Fins sPAPRPHBState */ | |
389 | phb = find_phb(spapr, buid); | |
390 | if (!phb) { | |
391 | rtas_st(rets, 0, -3); /* Parameter error */ | |
392 | return; | |
393 | } | |
394 | ||
395 | /* Find device descriptor and start IRQ */ | |
396 | ndev = spapr_msicfg_find(phb, config_addr, false); | |
397 | if (ndev < 0) { | |
398 | trace_spapr_pci_msi("MSI has not been enabled", -1, config_addr); | |
399 | rtas_st(rets, 0, -1); /* Hardware error */ | |
400 | return; | |
401 | } | |
402 | ||
403 | intr_src_num = phb->msi_table[ndev].irq + ioa_intr_num; | |
404 | trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, | |
405 | intr_src_num); | |
406 | ||
407 | rtas_st(rets, 0, 0); | |
408 | rtas_st(rets, 1, intr_src_num); | |
409 | rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ | |
410 | } | |
411 | ||
7fb0bd34 DG |
412 | static int pci_spapr_swizzle(int slot, int pin) |
413 | { | |
414 | return (slot + pin) % PCI_NUM_PINS; | |
415 | } | |
416 | ||
3384f95c DG |
417 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) |
418 | { | |
419 | /* | |
420 | * Here we need to convert pci_dev + irq_num to some unique value | |
7fb0bd34 DG |
421 | * which is less than number of IRQs on the specific bus (4). We |
422 | * use standard PCI swizzling, that is (slot number + pin number) | |
423 | * % 4. | |
3384f95c | 424 | */ |
7fb0bd34 | 425 | return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); |
3384f95c DG |
426 | } |
427 | ||
428 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
429 | { | |
430 | /* | |
431 | * Here we use the number returned by pci_spapr_map_irq to find a | |
432 | * corresponding qemu_irq. | |
433 | */ | |
434 | sPAPRPHBState *phb = opaque; | |
435 | ||
a2950fb6 | 436 | trace_spapr_pci_lsi_set(phb->busname, irq_num, phb->lsi_table[irq_num].irq); |
a307d594 | 437 | qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); |
3384f95c DG |
438 | } |
439 | ||
3384f95c DG |
440 | static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr, |
441 | unsigned size) | |
442 | { | |
443 | switch (size) { | |
444 | case 1: | |
445 | return cpu_inb(addr); | |
446 | case 2: | |
447 | return cpu_inw(addr); | |
448 | case 4: | |
449 | return cpu_inl(addr); | |
450 | } | |
451 | assert(0); | |
452 | } | |
453 | ||
454 | static void spapr_io_write(void *opaque, target_phys_addr_t addr, | |
455 | uint64_t data, unsigned size) | |
456 | { | |
457 | switch (size) { | |
458 | case 1: | |
459 | cpu_outb(addr, data); | |
460 | return; | |
461 | case 2: | |
462 | cpu_outw(addr, data); | |
463 | return; | |
464 | case 4: | |
465 | cpu_outl(addr, data); | |
466 | return; | |
467 | } | |
468 | assert(0); | |
469 | } | |
470 | ||
a348f108 | 471 | static const MemoryRegionOps spapr_io_ops = { |
3384f95c DG |
472 | .endianness = DEVICE_LITTLE_ENDIAN, |
473 | .read = spapr_io_read, | |
474 | .write = spapr_io_write | |
475 | }; | |
476 | ||
0ee2c058 AK |
477 | /* |
478 | * MSI/MSIX memory region implementation. | |
479 | * The handler handles both MSI and MSIX. | |
480 | * For MSI-X, the vector number is encoded as a part of the address, | |
481 | * data is set to 0. | |
482 | * For MSI, the vector number is encoded in least bits in data. | |
483 | */ | |
484 | static void spapr_msi_write(void *opaque, target_phys_addr_t addr, | |
485 | uint64_t data, unsigned size) | |
486 | { | |
487 | sPAPRPHBState *phb = opaque; | |
488 | int ndev = addr >> 16; | |
489 | int vec = ((addr & 0xFFFF) >> 2) | data; | |
490 | uint32_t irq = phb->msi_table[ndev].irq + vec; | |
491 | ||
492 | trace_spapr_pci_msi_write(addr, data, irq); | |
493 | ||
494 | qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); | |
495 | } | |
496 | ||
497 | static const MemoryRegionOps spapr_msi_ops = { | |
498 | /* There is no .read as the read result is undefined by PCI spec */ | |
499 | .read = NULL, | |
500 | .write = spapr_msi_write, | |
501 | .endianness = DEVICE_LITTLE_ENDIAN | |
502 | }; | |
503 | ||
298a9710 DG |
504 | /* |
505 | * PHB PCI device | |
506 | */ | |
edded454 DG |
507 | static DMAContext *spapr_pci_dma_context_fn(PCIBus *bus, void *opaque, |
508 | int devfn) | |
509 | { | |
510 | sPAPRPHBState *phb = opaque; | |
511 | ||
512 | return phb->dma; | |
513 | } | |
514 | ||
298a9710 | 515 | static int spapr_phb_init(SysBusDevice *s) |
3384f95c | 516 | { |
231903bf | 517 | sPAPRPHBState *phb = DO_UPCAST(sPAPRPHBState, host_state.busdev, s); |
298a9710 DG |
518 | char *namebuf; |
519 | int i; | |
3384f95c | 520 | PCIBus *bus; |
3384f95c | 521 | |
298a9710 DG |
522 | phb->dtbusname = g_strdup_printf("pci@%" PRIx64, phb->buid); |
523 | namebuf = alloca(strlen(phb->dtbusname) + 32); | |
3384f95c | 524 | |
298a9710 DG |
525 | /* Initialize memory regions */ |
526 | sprintf(namebuf, "%s.mmio", phb->dtbusname); | |
3384f95c DG |
527 | memory_region_init(&phb->memspace, namebuf, INT64_MAX); |
528 | ||
298a9710 | 529 | sprintf(namebuf, "%s.mmio-alias", phb->dtbusname); |
3384f95c | 530 | memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace, |
298a9710 DG |
531 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size); |
532 | memory_region_add_subregion(get_system_memory(), phb->mem_win_addr, | |
3384f95c DG |
533 | &phb->memwindow); |
534 | ||
3384f95c DG |
535 | /* On ppc, we only have MMIO no specific IO space from the CPU |
536 | * perspective. In theory we ought to be able to embed the PCI IO | |
537 | * memory region direction in the system memory space. However, | |
538 | * if any of the IO BAR subregions use the old_portio mechanism, | |
539 | * that won't be processed properly unless accessed from the | |
540 | * system io address space. This hack to bounce things via | |
541 | * system_io works around the problem until all the users of | |
542 | * old_portion are updated */ | |
298a9710 | 543 | sprintf(namebuf, "%s.io", phb->dtbusname); |
3384f95c DG |
544 | memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE); |
545 | /* FIXME: fix to support multiple PHBs */ | |
546 | memory_region_add_subregion(get_system_io(), 0, &phb->iospace); | |
547 | ||
298a9710 | 548 | sprintf(namebuf, "%s.io-alias", phb->dtbusname); |
3384f95c DG |
549 | memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb, |
550 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
298a9710 | 551 | memory_region_add_subregion(get_system_memory(), phb->io_win_addr, |
3384f95c DG |
552 | &phb->iowindow); |
553 | ||
0ee2c058 AK |
554 | /* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, |
555 | * we need to allocate some memory to catch those writes coming | |
556 | * from msi_notify()/msix_notify() */ | |
557 | if (msi_supported) { | |
558 | sprintf(namebuf, "%s.msi", phb->dtbusname); | |
559 | memory_region_init_io(&phb->msiwindow, &spapr_msi_ops, phb, | |
560 | namebuf, SPAPR_MSIX_MAX_DEVS * 0x10000); | |
561 | memory_region_add_subregion(get_system_memory(), phb->msi_win_addr, | |
562 | &phb->msiwindow); | |
563 | } | |
564 | ||
231903bf | 565 | bus = pci_register_bus(&phb->host_state.busdev.qdev, |
298a9710 DG |
566 | phb->busname ? phb->busname : phb->dtbusname, |
567 | pci_spapr_set_irq, pci_spapr_map_irq, phb, | |
568 | &phb->memspace, &phb->iospace, | |
7fb0bd34 | 569 | PCI_DEVFN(0, 0), PCI_NUM_PINS); |
298a9710 DG |
570 | phb->host_state.bus = bus; |
571 | ||
5c4cbcf2 AK |
572 | phb->dma_liobn = SPAPR_PCI_BASE_LIOBN | (pci_find_domain(bus) << 16); |
573 | phb->dma_window_start = 0; | |
574 | phb->dma_window_size = 0x40000000; | |
575 | phb->dma = spapr_tce_new_dma_context(phb->dma_liobn, phb->dma_window_size); | |
edded454 DG |
576 | pci_setup_iommu(bus, spapr_pci_dma_context_fn, phb); |
577 | ||
298a9710 DG |
578 | QLIST_INSERT_HEAD(&spapr->phbs, phb, list); |
579 | ||
580 | /* Initialize the LSI table */ | |
7fb0bd34 | 581 | for (i = 0; i < PCI_NUM_PINS; i++) { |
a307d594 | 582 | uint32_t irq; |
298a9710 | 583 | |
a307d594 AK |
584 | irq = spapr_allocate_lsi(0); |
585 | if (!irq) { | |
298a9710 DG |
586 | return -1; |
587 | } | |
588 | ||
a307d594 | 589 | phb->lsi_table[i].irq = irq; |
298a9710 DG |
590 | } |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
595 | static Property spapr_phb_properties[] = { | |
596 | DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0), | |
597 | DEFINE_PROP_STRING("busname", sPAPRPHBState, busname), | |
598 | DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0), | |
599 | DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000), | |
600 | DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0), | |
601 | DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000), | |
0ee2c058 | 602 | DEFINE_PROP_HEX64("msi_win_addr", sPAPRPHBState, msi_win_addr, 0), |
298a9710 DG |
603 | DEFINE_PROP_END_OF_LIST(), |
604 | }; | |
605 | ||
606 | static void spapr_phb_class_init(ObjectClass *klass, void *data) | |
607 | { | |
608 | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); | |
609 | DeviceClass *dc = DEVICE_CLASS(klass); | |
610 | ||
611 | sdc->init = spapr_phb_init; | |
612 | dc->props = spapr_phb_properties; | |
298a9710 | 613 | } |
3384f95c | 614 | |
298a9710 DG |
615 | static TypeInfo spapr_phb_info = { |
616 | .name = "spapr-pci-host-bridge", | |
617 | .parent = TYPE_SYS_BUS_DEVICE, | |
618 | .instance_size = sizeof(sPAPRPHBState), | |
619 | .class_init = spapr_phb_class_init, | |
620 | }; | |
621 | ||
622 | void spapr_create_phb(sPAPREnvironment *spapr, | |
623 | const char *busname, uint64_t buid, | |
624 | uint64_t mem_win_addr, uint64_t mem_win_size, | |
0ee2c058 | 625 | uint64_t io_win_addr, uint64_t msi_win_addr) |
298a9710 DG |
626 | { |
627 | DeviceState *dev; | |
628 | ||
629 | dev = qdev_create(NULL, spapr_phb_info.name); | |
3384f95c | 630 | |
298a9710 DG |
631 | if (busname) { |
632 | qdev_prop_set_string(dev, "busname", g_strdup(busname)); | |
633 | } | |
634 | qdev_prop_set_uint64(dev, "buid", buid); | |
635 | qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr); | |
636 | qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size); | |
637 | qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr); | |
0ee2c058 | 638 | qdev_prop_set_uint64(dev, "msi_win_addr", msi_win_addr); |
298a9710 DG |
639 | |
640 | qdev_init_nofail(dev); | |
3384f95c DG |
641 | } |
642 | ||
643 | /* Macros to operate with address in OF binding to PCI */ | |
644 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
645 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
646 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
647 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
648 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
649 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
650 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
651 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
652 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
653 | ||
e0fdbd7c AK |
654 | int spapr_populate_pci_dt(sPAPRPHBState *phb, |
655 | uint32_t xics_phandle, | |
656 | void *fdt) | |
3384f95c | 657 | { |
7fb0bd34 | 658 | int bus_off, i, j; |
3384f95c | 659 | char nodename[256]; |
3384f95c DG |
660 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
661 | struct { | |
662 | uint32_t hi; | |
663 | uint64_t child; | |
664 | uint64_t parent; | |
665 | uint64_t size; | |
c4889f54 | 666 | } QEMU_PACKED ranges[] = { |
3384f95c DG |
667 | { |
668 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
669 | cpu_to_be64(phb->io_win_addr), | |
670 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
671 | }, | |
672 | { | |
673 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
674 | cpu_to_be64(phb->mem_win_addr), | |
675 | cpu_to_be64(memory_region_size(&phb->memwindow)), | |
676 | }, | |
677 | }; | |
678 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; | |
679 | uint32_t interrupt_map_mask[] = { | |
7fb0bd34 DG |
680 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; |
681 | uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; | |
3384f95c DG |
682 | |
683 | /* Start populating the FDT */ | |
684 | sprintf(nodename, "pci@%" PRIx64, phb->buid); | |
685 | bus_off = fdt_add_subnode(fdt, 0, nodename); | |
686 | if (bus_off < 0) { | |
687 | return bus_off; | |
688 | } | |
689 | ||
690 | #define _FDT(exp) \ | |
691 | do { \ | |
692 | int ret = (exp); \ | |
693 | if (ret < 0) { \ | |
694 | return ret; \ | |
695 | } \ | |
696 | } while (0) | |
697 | ||
698 | /* Write PHB properties */ | |
699 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
700 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
701 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
702 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
703 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
704 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
705 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
706 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges))); | |
707 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); | |
3f7565c9 | 708 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
3384f95c | 709 | |
4d8d5467 BH |
710 | /* Build the interrupt-map, this must matches what is done |
711 | * in pci_spapr_map_irq | |
712 | */ | |
713 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
714 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
7fb0bd34 DG |
715 | for (i = 0; i < PCI_SLOT_MAX; i++) { |
716 | for (j = 0; j < PCI_NUM_PINS; j++) { | |
717 | uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; | |
718 | int lsi_num = pci_spapr_swizzle(i, j); | |
719 | ||
720 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
721 | irqmap[1] = 0; | |
722 | irqmap[2] = 0; | |
723 | irqmap[3] = cpu_to_be32(j+1); | |
724 | irqmap[4] = cpu_to_be32(xics_phandle); | |
a307d594 | 725 | irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); |
7fb0bd34 DG |
726 | irqmap[6] = cpu_to_be32(0x8); |
727 | } | |
3384f95c | 728 | } |
3384f95c DG |
729 | /* Write interrupt map */ |
730 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
7fb0bd34 | 731 | sizeof(interrupt_map))); |
3384f95c | 732 | |
5c4cbcf2 AK |
733 | spapr_dma_dt(fdt, bus_off, "ibm,dma-window", |
734 | phb->dma_liobn, phb->dma_window_start, | |
735 | phb->dma_window_size); | |
edded454 | 736 | |
3384f95c DG |
737 | return 0; |
738 | } | |
298a9710 | 739 | |
fa28f71b AK |
740 | void spapr_pci_rtas_init(void) |
741 | { | |
742 | spapr_rtas_register("read-pci-config", rtas_read_pci_config); | |
743 | spapr_rtas_register("write-pci-config", rtas_write_pci_config); | |
744 | spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config); | |
745 | spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config); | |
0ee2c058 AK |
746 | if (msi_supported) { |
747 | spapr_rtas_register("ibm,query-interrupt-source-number", | |
748 | rtas_ibm_query_interrupt_source_number); | |
749 | spapr_rtas_register("ibm,change-msi", rtas_ibm_change_msi); | |
750 | } | |
fa28f71b AK |
751 | } |
752 | ||
298a9710 DG |
753 | static void register_types(void) |
754 | { | |
755 | type_register_static(&spapr_phb_info); | |
756 | } | |
757 | type_init(register_types) |