[qemu.git] / hw / spapr_pci.c

/*
 * QEMU sPAPR PCI host originated from Uninorth PCI host
 *
 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
 * Copyright (C) 2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pci.h"
#include "pci_host.h"
#include "hw/spapr.h"
#include "hw/spapr_pci.h"
#include "exec-memory.h"
#include <libfdt.h>

#include "hw/pci_internals.h"

static const uint32_t bars[] = {
    PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
    PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
    PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
    /*, PCI_ROM_ADDRESS*/
};

static PCIDevice *find_dev(sPAPREnvironment *spapr,
                           uint64_t buid, uint32_t config_addr)
{
    DeviceState *qdev;
    int devfn = (config_addr >> 8) & 0xFF;
    sPAPRPHBState *phb;

    QLIST_FOREACH(phb, &spapr->phbs, list) {
        if (phb->buid != buid) {
            continue;
        }

        QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
            PCIDevice *dev = (PCIDevice *)qdev;
            if (dev->devfn == devfn) {
                return dev;
            }
        }
    }

    return NULL;
}

static uint32_t rtas_pci_cfgaddr(uint32_t arg)
{
    return ((arg >> 20) & 0xf00) | (arg & 0xff);
}

static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
                                     uint32_t token, uint32_t nargs,
                                     target_ulong args,
                                     uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;
    uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
    PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));

    if (!dev) {
        rtas_st(rets, 0, -1);
        return;
    }
    size = rtas_ld(args, 3);
    addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
    val = pci_host_config_read_common(dev, addr, pci_config_size(dev), size);
    rtas_st(rets, 0, 0);
    rtas_st(rets, 1, val);
}

static void rtas_read_pci_config(sPAPREnvironment *spapr,
                                 uint32_t token, uint32_t nargs,
                                 target_ulong args,
                                 uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;
    PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));

    if (!dev) {
        rtas_st(rets, 0, -1);
        return;
    }
    size = rtas_ld(args, 1);
    addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
    val = pci_host_config_read_common(dev, addr, pci_config_size(dev), size);
    rtas_st(rets, 0, 0);
    rtas_st(rets, 1, val);
}

static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
                                      uint32_t token, uint32_t nargs,
                                      target_ulong args,
                                      uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;
    uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
    PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));

    if (!dev) {
        rtas_st(rets, 0, -1);
        return;
    }
    val = rtas_ld(args, 4);
    size = rtas_ld(args, 3);
    addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
    pci_host_config_write_common(dev, addr, pci_config_size(dev), val, size);
    rtas_st(rets, 0, 0);
}

static void rtas_write_pci_config(sPAPREnvironment *spapr,
                                  uint32_t token, uint32_t nargs,
                                  target_ulong args,
                                  uint32_t nret, target_ulong rets)
{
    uint32_t val, size, addr;
    PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));

    if (!dev) {
        rtas_st(rets, 0, -1);
        return;
    }
    val = rtas_ld(args, 2);
    size = rtas_ld(args, 1);
    addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
    pci_host_config_write_common(dev, addr, pci_config_size(dev), val, size);
    rtas_st(rets, 0, 0);
}

static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
{
    /*
     * Here we need to convert pci_dev + irq_num to some unique value
     * which is less than number of IRQs on the specific bus (now it
     * is 16).  At the moment irq_num == device_id (number of the
     * slot?)
     * FIXME: we should swizzle in fn and irq_num
     */
    return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
}

static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
{
    /*
     * Here we use the number returned by pci_spapr_map_irq to find a
     * corresponding qemu_irq.
     */
    sPAPRPHBState *phb = opaque;

    qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
}

static int spapr_phb_init(SysBusDevice *s)
{
    sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
    int i;

    /* Initialize the LSI table */
    for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
        qemu_irq qirq;
        uint32_t num;

        qirq = spapr_allocate_irq(0, &num);
        if (!qirq) {
            return -1;
        }

        phb->lsi_table[i].dt_irq = num;
        phb->lsi_table[i].qirq = qirq;
    }

    return 0;
}

static int spapr_main_pci_host_init(PCIDevice *d)
{
    return 0;
}

static PCIDeviceInfo spapr_main_pci_host_info = {
    .qdev.name = "spapr-pci-host-bridge",
    .qdev.size = sizeof(PCIDevice),
    .init      = spapr_main_pci_host_init,
};

static void spapr_register_devices(void)
{
    sysbus_register_dev("spapr-pci-host-bridge", sizeof(sPAPRPHBState),
                        spapr_phb_init);
    pci_qdev_register(&spapr_main_pci_host_info);
}

device_init(spapr_register_devices)

static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
                              unsigned size)
{
    switch (size) {
    case 1:
        return cpu_inb(addr);
    case 2:
        return cpu_inw(addr);
    case 4:
        return cpu_inl(addr);
    }
    assert(0);
}

static void spapr_io_write(void *opaque, target_phys_addr_t addr,
                           uint64_t data, unsigned size)
{
    switch (size) {
    case 1:
        cpu_outb(addr, data);
        return;
    case 2:
        cpu_outw(addr, data);
        return;
    case 4:
        cpu_outl(addr, data);
        return;
    }
    assert(0);
}

static MemoryRegionOps spapr_io_ops = {
    .endianness = DEVICE_LITTLE_ENDIAN,
    .read = spapr_io_read,
    .write = spapr_io_write
};

void spapr_create_phb(sPAPREnvironment *spapr,
                      const char *busname, uint64_t buid,
                      uint64_t mem_win_addr, uint64_t mem_win_size,
                      uint64_t io_win_addr)
{
    DeviceState *dev;
    SysBusDevice *s;
    sPAPRPHBState *phb;
    PCIBus *bus;
    char namebuf[strlen(busname)+11];

    dev = qdev_create(NULL, "spapr-pci-host-bridge");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    phb = FROM_SYSBUS(sPAPRPHBState, s);

    phb->mem_win_addr = mem_win_addr;

    sprintf(namebuf, "%s-mem", busname);
    memory_region_init(&phb->memspace, namebuf, INT64_MAX);

    sprintf(namebuf, "%s-memwindow", busname);
    memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
                             SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
    memory_region_add_subregion(get_system_memory(), mem_win_addr,
                                &phb->memwindow);

    phb->io_win_addr = io_win_addr;

    /* On ppc, we only have MMIO no specific IO space from the CPU
     * perspective.  In theory we ought to be able to embed the PCI IO
     * memory region direction in the system memory space.  However,
     * if any of the IO BAR subregions use the old_portio mechanism,
     * that won't be processed properly unless accessed from the
     * system io address space.  This hack to bounce things via
     * system_io works around the problem until all the users of
     * old_portion are updated */
    sprintf(namebuf, "%s-io", busname);
    memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
    /* FIXME: fix to support multiple PHBs */
    memory_region_add_subregion(get_system_io(), 0, &phb->iospace);

    sprintf(namebuf, "%s-iowindow", busname);
    memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
                          namebuf, SPAPR_PCI_IO_WIN_SIZE);
    memory_region_add_subregion(get_system_memory(), io_win_addr,
                                &phb->iowindow);

    phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
                                                 pci_spapr_set_irq,
                                                 pci_spapr_map_irq,
                                                 phb,
                                                 &phb->memspace, &phb->iospace,
                                                 PCI_DEVFN(0, 0),
                                                 SPAPR_PCI_NUM_LSI);

    spapr_rtas_register("read-pci-config", rtas_read_pci_config);
    spapr_rtas_register("write-pci-config", rtas_write_pci_config);
    spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
    spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);

    QLIST_INSERT_HEAD(&spapr->phbs, phb, list);

    /* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
}

/* Macros to operate with address in OF binding to PCI */
#define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
#define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
#define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
#define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
#define b_ss(x)         b_x((x), 24, 2) /* the space code */
#define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
#define b_ddddd(x)      b_x((x), 11, 5) /* device number */
#define b_fff(x)        b_x((x), 8, 3)  /* function number */
#define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */

int spapr_populate_pci_devices(sPAPRPHBState *phb,
                               uint32_t xics_phandle,
                               void *fdt)
{
    PCIBus *bus = phb->host_state.bus;
    int bus_off, i;
    char nodename[256];
    uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
    struct {
        uint32_t hi;
        uint64_t child;
        uint64_t parent;
        uint64_t size;
    } __attribute__((packed)) ranges[] = {
        {
            cpu_to_be32(b_ss(1)), cpu_to_be64(0),
            cpu_to_be64(phb->io_win_addr),
            cpu_to_be64(memory_region_size(&phb->iospace)),
        },
        {
            cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
            cpu_to_be64(phb->mem_win_addr),
            cpu_to_be64(memory_region_size(&phb->memwindow)),
        },
    };
    uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
    uint32_t interrupt_map_mask[] = {
        cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, 0x0};
    uint32_t interrupt_map[bus->nirq][7];

    /* Start populating the FDT */
    sprintf(nodename, "pci@%" PRIx64, phb->buid);
    bus_off = fdt_add_subnode(fdt, 0, nodename);
    if (bus_off < 0) {
        return bus_off;
    }

#define _FDT(exp) \
    do { \
        int ret = (exp);                                           \
        if (ret < 0) {                                             \
            return ret;                                            \
        }                                                          \
    } while (0)

    /* Write PHB properties */
    _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
    _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
    _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
    _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
    _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
    _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
    _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
    _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));

    /* Build the interrupt-map, this must matches what is done
     * in pci_spapr_map_irq
     */
    _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
                     &interrupt_map_mask, sizeof(interrupt_map_mask)));
    for (i = 0; i < 7; i++) {
        uint32_t *irqmap = interrupt_map[i];
        irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
        irqmap[1] = 0;
        irqmap[2] = 0;
        irqmap[3] = 0;
        irqmap[4] = cpu_to_be32(xics_phandle);
        irqmap[5] = cpu_to_be32(phb->lsi_table[i % SPAPR_PCI_NUM_LSI].dt_irq);
        irqmap[6] = cpu_to_be32(0x8);
    }
    /* Write interrupt map */
    _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
                     7 * sizeof(interrupt_map[0])));

    return 0;
}
Commit	Line	Data
3384f95c DG	1	/*
	2	* QEMU sPAPR PCI host originated from Uninorth PCI host
	3	*
	4	* Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
	5	* Copyright (C) 2011 David Gibson, IBM Corporation.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "hw.h"
	26	#include "pci.h"
	27	#include "pci_host.h"
	28	#include "hw/spapr.h"
	29	#include "hw/spapr_pci.h"
	30	#include "exec-memory.h"
	31	#include <libfdt.h>
	32
	33	#include "hw/pci_internals.h"
	34
	35	static const uint32_t bars[] = {
	36	PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
	37	PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
	38	PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
	39	/, PCI_ROM_ADDRESS/
	40	};
	41
	42	static PCIDevice find_dev(sPAPREnvironment spapr,
	43	uint64_t buid, uint32_t config_addr)
	44	{
	45	DeviceState *qdev;
	46	int devfn = (config_addr >> 8) & 0xFF;
	47	sPAPRPHBState *phb;
	48
	49	QLIST_FOREACH(phb, &spapr->phbs, list) {
	50	if (phb->buid != buid) {
	51	continue;
	52	}
	53
3a26360d	54	QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
3384f95c DG	55	PCIDevice dev = (PCIDevice )qdev;
	56	if (dev->devfn == devfn) {
	57	return dev;
	58	}
	59	}
	60	}
	61
	62	return NULL;
	63	}
	64
3f7565c9 BH	65	static uint32_t rtas_pci_cfgaddr(uint32_t arg)
	66	{
	67	return ((arg >> 20) & 0xf00) \| (arg & 0xff);
	68	}
	69
3384f95c DG	70	static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
	71	uint32_t token, uint32_t nargs,
	72	target_ulong args,
	73	uint32_t nret, target_ulong rets)
	74	{
	75	uint32_t val, size, addr;
	76	uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) \| rtas_ld(args, 2);
	77	PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
	78
	79	if (!dev) {
	80	rtas_st(rets, 0, -1);
	81	return;
	82	}
	83	size = rtas_ld(args, 3);
3f7565c9	84	addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
c9c3c80a	85	val = pci_host_config_read_common(dev, addr, pci_config_size(dev), size);
3384f95c DG	86	rtas_st(rets, 0, 0);
	87	rtas_st(rets, 1, val);
	88	}
	89
	90	static void rtas_read_pci_config(sPAPREnvironment *spapr,
	91	uint32_t token, uint32_t nargs,
	92	target_ulong args,
	93	uint32_t nret, target_ulong rets)
	94	{
	95	uint32_t val, size, addr;
	96	PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
	97
	98	if (!dev) {
	99	rtas_st(rets, 0, -1);
	100	return;
	101	}
	102	size = rtas_ld(args, 1);
3f7565c9	103	addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
c9c3c80a	104	val = pci_host_config_read_common(dev, addr, pci_config_size(dev), size);
3384f95c DG	105	rtas_st(rets, 0, 0);
	106	rtas_st(rets, 1, val);
	107	}
	108
	109	static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
	110	uint32_t token, uint32_t nargs,
	111	target_ulong args,
	112	uint32_t nret, target_ulong rets)
	113	{
	114	uint32_t val, size, addr;
	115	uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) \| rtas_ld(args, 2);
	116	PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
	117
	118	if (!dev) {
	119	rtas_st(rets, 0, -1);
	120	return;
	121	}
	122	val = rtas_ld(args, 4);
	123	size = rtas_ld(args, 3);
3f7565c9	124	addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
c9c3c80a	125	pci_host_config_write_common(dev, addr, pci_config_size(dev), val, size);
3384f95c DG	126	rtas_st(rets, 0, 0);
	127	}
	128
	129	static void rtas_write_pci_config(sPAPREnvironment *spapr,
	130	uint32_t token, uint32_t nargs,
	131	target_ulong args,
	132	uint32_t nret, target_ulong rets)
	133	{
	134	uint32_t val, size, addr;
	135	PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
	136
	137	if (!dev) {
	138	rtas_st(rets, 0, -1);
	139	return;
	140	}
	141	val = rtas_ld(args, 2);
	142	size = rtas_ld(args, 1);
3f7565c9	143	addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
c9c3c80a	144	pci_host_config_write_common(dev, addr, pci_config_size(dev), val, size);
3384f95c DG	145	rtas_st(rets, 0, 0);
	146	}
	147
	148	static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
	149	{
	150	/*
	151	* Here we need to convert pci_dev + irq_num to some unique value
	152	* which is less than number of IRQs on the specific bus (now it
	153	* is 16). At the moment irq_num == device_id (number of the
	154	* slot?)
	155	* FIXME: we should swizzle in fn and irq_num
	156	*/
	157	return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
	158	}
	159
	160	static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
	161	{
	162	/*
	163	* Here we use the number returned by pci_spapr_map_irq to find a
	164	* corresponding qemu_irq.
	165	*/
	166	sPAPRPHBState *phb = opaque;
	167
	168	qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
	169	}
	170
	171	static int spapr_phb_init(SysBusDevice *s)
	172	{
	173	sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
	174	int i;
	175
	176	/* Initialize the LSI table */
	177	for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
	178	qemu_irq qirq;
	179	uint32_t num;
	180
	181	qirq = spapr_allocate_irq(0, &num);
	182	if (!qirq) {
	183	return -1;
	184	}
	185
	186	phb->lsi_table[i].dt_irq = num;
	187	phb->lsi_table[i].qirq = qirq;
	188	}
	189
	190	return 0;
	191	}
	192
	193	static int spapr_main_pci_host_init(PCIDevice *d)
	194	{
	195	return 0;
	196	}
	197
	198	static PCIDeviceInfo spapr_main_pci_host_info = {
	199	.qdev.name = "spapr-pci-host-bridge",
	200	.qdev.size = sizeof(PCIDevice),
	201	.init = spapr_main_pci_host_init,
	202	};
	203
	204	static void spapr_register_devices(void)
	205	{
	206	sysbus_register_dev("spapr-pci-host-bridge", sizeof(sPAPRPHBState),
	207	spapr_phb_init);
	208	pci_qdev_register(&spapr_main_pci_host_info);
209	}
210
211	device_init(spapr_register_devices)
212
213	static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
214	unsigned size)
215	{
216	switch (size) {
217	case 1:
218	return cpu_inb(addr);
219	case 2:
220	return cpu_inw(addr);
221	case 4:
222	return cpu_inl(addr);
223	}
224	assert(0);
225	}
226
227	static void spapr_io_write(void *opaque, target_phys_addr_t addr,
228	uint64_t data, unsigned size)
229	{
230	switch (size) {
231	case 1:
232	cpu_outb(addr, data);
233	return;
234	case 2:
235	cpu_outw(addr, data);
236	return;
237	case 4:
238	cpu_outl(addr, data);
239	return;
240	}
241	assert(0);
242	}
243
244	static MemoryRegionOps spapr_io_ops = {
245	.endianness = DEVICE_LITTLE_ENDIAN,
246	.read = spapr_io_read,
247	.write = spapr_io_write
248	};
249
250	void spapr_create_phb(sPAPREnvironment *spapr,
251	const char *busname, uint64_t buid,
252	uint64_t mem_win_addr, uint64_t mem_win_size,
253	uint64_t io_win_addr)
254	{
255	DeviceState *dev;
256	SysBusDevice *s;
257	sPAPRPHBState *phb;
258	PCIBus *bus;
259	char namebuf[strlen(busname)+11];
260
261	dev = qdev_create(NULL, "spapr-pci-host-bridge");
262	qdev_init_nofail(dev);
263	s = sysbus_from_qdev(dev);
264	phb = FROM_SYSBUS(sPAPRPHBState, s);
265
266	phb->mem_win_addr = mem_win_addr;
267
268	sprintf(namebuf, "%s-mem", busname);
269	memory_region_init(&phb->memspace, namebuf, INT64_MAX);
270
271	sprintf(namebuf, "%s-memwindow", busname);
272	memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
273	SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
274	memory_region_add_subregion(get_system_memory(), mem_win_addr,
275	&phb->memwindow);
276
277	phb->io_win_addr = io_win_addr;
278
279	/* On ppc, we only have MMIO no specific IO space from the CPU
280	* perspective. In theory we ought to be able to embed the PCI IO
281	* memory region direction in the system memory space. However,
282	* if any of the IO BAR subregions use the old_portio mechanism,
283	* that won't be processed properly unless accessed from the
284	* system io address space. This hack to bounce things via
285	* system_io works around the problem until all the users of
286	* old_portion are updated */
287	sprintf(namebuf, "%s-io", busname);
288	memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
289	/* FIXME: fix to support multiple PHBs */
290	memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
291
292	sprintf(namebuf, "%s-iowindow", busname);
293	memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
294	namebuf, SPAPR_PCI_IO_WIN_SIZE);
295	memory_region_add_subregion(get_system_memory(), io_win_addr,
296	&phb->iowindow);
297
298	phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
299	pci_spapr_set_irq,
300	pci_spapr_map_irq,
301	phb,
302	&phb->memspace, &phb->iospace,
303	PCI_DEVFN(0, 0),
304	SPAPR_PCI_NUM_LSI);
305
306	spapr_rtas_register("read-pci-config", rtas_read_pci_config);
307	spapr_rtas_register("write-pci-config", rtas_write_pci_config);
308	spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
309	spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
310
311	QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
312
313	/* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
314	}
315
316	/* Macros to operate with address in OF binding to PCI */
317	#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
318	#define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
319	#define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
320	#define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
321	#define b_ss(x) b_x((x), 24, 2) /* the space code */
322	#define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
323	#define b_ddddd(x) b_x((x), 11, 5) /* device number */
324	#define b_fff(x) b_x((x), 8, 3) /* function number */
325	#define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
326
3384f95c DG	327	int spapr_populate_pci_devices(sPAPRPHBState *phb,
	328	uint32_t xics_phandle,
	329	void *fdt)
	330	{
	331	PCIBus *bus = phb->host_state.bus;
4d8d5467	332	int bus_off, i;
3384f95c	333	char nodename[256];
3384f95c DG	334	uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
	335	struct {
	336	uint32_t hi;
	337	uint64_t child;
	338	uint64_t parent;
	339	uint64_t size;
	340	} __attribute__((packed)) ranges[] = {
	341	{
	342	cpu_to_be32(b_ss(1)), cpu_to_be64(0),
	343	cpu_to_be64(phb->io_win_addr),
	344	cpu_to_be64(memory_region_size(&phb->iospace)),
	345	},
	346	{
	347	cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
	348	cpu_to_be64(phb->mem_win_addr),
	349	cpu_to_be64(memory_region_size(&phb->memwindow)),
	350	},
	351	};
	352	uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
	353	uint32_t interrupt_map_mask[] = {
4d8d5467	354	cpu_to_be32(b_ddddd(-1)\|b_fff(0)), 0x0, 0x0, 0x0};
3384f95c DG	355	uint32_t interrupt_map[bus->nirq][7];
	356
	357	/* Start populating the FDT */
	358	sprintf(nodename, "pci@%" PRIx64, phb->buid);
	359	bus_off = fdt_add_subnode(fdt, 0, nodename);
	360	if (bus_off < 0) {
	361	return bus_off;
	362	}
	363
	364	#define _FDT(exp) \
	365	do { \
	366	int ret = (exp); \
	367	if (ret < 0) { \
	368	return ret; \
	369	} \
	370	} while (0)
	371
	372	/* Write PHB properties */
	373	_FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
	374	_FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
	375	_FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
	376	_FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
	377	_FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
	378	_FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
	379	_FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
	380	_FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
	381	_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
3f7565c9	382	_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
3384f95c	383
4d8d5467 BH	384	/* Build the interrupt-map, this must matches what is done
	385	* in pci_spapr_map_irq
	386	*/
	387	_FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
	388	&interrupt_map_mask, sizeof(interrupt_map_mask)));
	389	for (i = 0; i < 7; i++) {
	390	uint32_t *irqmap = interrupt_map[i];
	391	irqmap[0] = cpu_to_be32(b_ddddd(i)\|b_fff(0));
3384f95c DG	392	irqmap[1] = 0;
	393	irqmap[2] = 0;
	394	irqmap[3] = 0;
	395	irqmap[4] = cpu_to_be32(xics_phandle);
4d8d5467	396	irqmap[5] = cpu_to_be32(phb->lsi_table[i % SPAPR_PCI_NUM_LSI].dt_irq);
3384f95c	397	irqmap[6] = cpu_to_be32(0x8);
3384f95c	398	}
3384f95c DG	399	/* Write interrupt map */
3384f95c DG	400	_FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
4d8d5467	401	7 * sizeof(interrupt_map[0])));
3384f95c DG	402
	403	return 0;
	404	}