[qemu.git] / hw / spapr_pci.h

/*
 * QEMU SPAPR PCI BUS definitions
 *
 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#if !defined(__HW_SPAPR_H__)
#error Please include spapr.h before this file!
#endif

#if !defined(__HW_SPAPR_PCI_H__)
#define __HW_SPAPR_PCI_H__

#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/xics.h"

#define SPAPR_MSIX_MAX_DEVS 32

#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"

#define SPAPR_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)

typedef struct sPAPRPHBState {
    PCIHostState parent_obj;

    int32_t index;
    uint64_t buid;
    char *busname;
    char *dtbusname;

    MemoryRegion memspace, iospace;
    hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
    hwaddr msi_win_addr;
    MemoryRegion memwindow, iowindow, msiwindow;

    uint32_t dma_liobn;
    uint64_t dma_window_start;
    uint64_t dma_window_size;
    DMAContext *dma;

    struct {
        uint32_t irq;
    } lsi_table[PCI_NUM_PINS];

    struct {
        uint32_t config_addr;
        uint32_t irq;
        int nvec;
    } msi_table[SPAPR_MSIX_MAX_DEVS];

    QLIST_ENTRY(sPAPRPHBState) list;
} sPAPRPHBState;

#define SPAPR_PCI_BASE_BUID          0x800000020000000ULL

#define SPAPR_PCI_WINDOW_BASE        0x10000000000ULL
#define SPAPR_PCI_WINDOW_SPACING     0x1000000000ULL
#define SPAPR_PCI_MMIO_WIN_OFF       0xA0000000
#define SPAPR_PCI_MMIO_WIN_SIZE      0x20000000
#define SPAPR_PCI_IO_WIN_OFF         0x80000000
#define SPAPR_PCI_IO_WIN_SIZE        0x10000
#define SPAPR_PCI_MSI_WIN_OFF        0x90000000

#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL

static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
{
    return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
}

PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index,
                               const char *busname);

int spapr_populate_pci_dt(sPAPRPHBState *phb,
                          uint32_t xics_phandle,
                          void *fdt);

void spapr_pci_rtas_init(void);

#endif /* __HW_SPAPR_PCI_H__ */
Commit	Line	Data
3384f95c DG	1	/*
	2	* QEMU SPAPR PCI BUS definitions
	3	*
	4	* Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#if !defined(__HW_SPAPR_H__)
	20	#error Please include spapr.h before this file!
	21	#endif
	22
	23	#if !defined(__HW_SPAPR_PCI_H__)
	24	#define __HW_SPAPR_PCI_H__
	25
a2cb15b0 MT	26	#include "hw/pci/pci.h"
a2cb15b0 MT	27	#include "hw/pci/pci_host.h"
3384f95c DG	28	#include "hw/xics.h"
3384f95c DG	29
0ee2c058 AK	30	#define SPAPR_MSIX_MAX_DEVS 32
0ee2c058 AK	31
8c9f64df AF	32	#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
	33
	34	#define SPAPR_PCI_HOST_BRIDGE(obj) \
	35	OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
	36
3384f95c	37	typedef struct sPAPRPHBState {
67c332fd	38	PCIHostState parent_obj;
3384f95c	39
caae58cb	40	int32_t index;
3384f95c	41	uint64_t buid;
298a9710 DG	42	char *busname;
298a9710 DG	43	char *dtbusname;
3384f95c DG	44
3384f95c DG	45	MemoryRegion memspace, iospace;
a8170e5e AK	46	hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
a8170e5e AK	47	hwaddr msi_win_addr;
a3cfa18e	48	MemoryRegion memwindow, iowindow, msiwindow;
0ee2c058	49
5c4cbcf2 AK	50	uint32_t dma_liobn;
	51	uint64_t dma_window_start;
	52	uint64_t dma_window_size;
edded454	53	DMAContext *dma;
3384f95c DG	54
3384f95c DG	55	struct {
a307d594	56	uint32_t irq;
7fb0bd34	57	} lsi_table[PCI_NUM_PINS];
3384f95c	58
0ee2c058 AK	59	struct {
	60	uint32_t config_addr;
	61	uint32_t irq;
	62	int nvec;
	63	} msi_table[SPAPR_MSIX_MAX_DEVS];
	64
3384f95c DG	65	QLIST_ENTRY(sPAPRPHBState) list;
	66	} sPAPRPHBState;
	67
caae58cb DG	68	#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
	69
	70	#define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL
	71	#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL
	72	#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000
	73	#define SPAPR_PCI_MMIO_WIN_SIZE 0x20000000
	74	#define SPAPR_PCI_IO_WIN_OFF 0x80000000
	75	#define SPAPR_PCI_IO_WIN_SIZE 0x10000
	76	#define SPAPR_PCI_MSI_WIN_OFF 0x90000000
	77
	78	#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
	79
a307d594 AK	80	static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
	81	{
	82	return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
	83	}
	84
caae58cb DG	85	PCIHostState spapr_create_phb(sPAPREnvironment spapr, int index,
caae58cb DG	86	const char *busname);
3384f95c	87
e0fdbd7c AK	88	int spapr_populate_pci_dt(sPAPRPHBState *phb,
	89	uint32_t xics_phandle,
	90	void *fdt);
3384f95c	91
fa28f71b AK	92	void spapr_pci_rtas_init(void);
fa28f71b AK	93
3384f95c	94	#endif /* __HW_SPAPR_PCI_H__ */