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Commit | Line | Data |
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420557e8 | 1 | /* |
ee76f82e | 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
5fafdf24 | 3 | * |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
db5ebe5f | 24 | #include "qemu/osdep.h" |
0a2e467b | 25 | #include "qemu/units.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 PB |
27 | #include "qemu-common.h" |
28 | #include "cpu.h" | |
83c9f4ca | 29 | #include "hw/sysbus.h" |
af87bf29 | 30 | #include "qemu/error-report.h" |
1de7afc9 | 31 | #include "qemu/timer.h" |
1527f488 | 32 | #include "hw/sparc/sun4m_iommu.h" |
0d09e41a PB |
33 | #include "hw/timer/m48t59.h" |
34 | #include "hw/sparc/sparc32_dma.h" | |
35 | #include "hw/block/fdc.h" | |
9c17d615 | 36 | #include "sysemu/sysemu.h" |
1422e32d | 37 | #include "net/net.h" |
83c9f4ca | 38 | #include "hw/boards.h" |
0d09e41a | 39 | #include "hw/scsi/esp.h" |
c6363bae | 40 | #include "hw/nvram/sun_nvram.h" |
2024c014 | 41 | #include "hw/nvram/chrp_nvram.h" |
0d09e41a PB |
42 | #include "hw/nvram/fw_cfg.h" |
43 | #include "hw/char/escc.h" | |
83c9f4ca | 44 | #include "hw/empty_slot.h" |
83c9f4ca | 45 | #include "hw/loader.h" |
ca20cf32 | 46 | #include "elf.h" |
97bf4851 | 47 | #include "trace.h" |
420557e8 | 48 | |
36cd9210 BS |
49 | /* |
50 | * Sun4m architecture was used in the following machines: | |
51 | * | |
52 | * SPARCserver 6xxMP/xx | |
77f193da BS |
53 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), |
54 | * SPARCclassic X (4/10) | |
36cd9210 BS |
55 | * SPARCstation LX/ZX (4/30) |
56 | * SPARCstation Voyager | |
57 | * SPARCstation 10/xx, SPARCserver 10/xx | |
58 | * SPARCstation 5, SPARCserver 5 | |
59 | * SPARCstation 20/xx, SPARCserver 20 | |
60 | * SPARCstation 4 | |
61 | * | |
62 | * See for example: http://www.sunhelp.org/faq/sunref1.html | |
63 | */ | |
64 | ||
420557e8 | 65 | #define KERNEL_LOAD_ADDR 0x00004000 |
b6f479d3 | 66 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 67 | #define INITRD_LOAD_ADDR 0x00800000 |
0a2e467b | 68 | #define PROM_SIZE_MAX (1 * MiB) |
40ce0a9a | 69 | #define PROM_VADDR 0xffd00000 |
f930d07e | 70 | #define PROM_FILENAME "openbios-sparc32" |
3cce6243 | 71 | #define CFG_ADDR 0xd00000510ULL |
fbfcf955 | 72 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
b96919e0 MCA |
73 | #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) |
74 | #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) | |
b8174937 | 75 | |
ba3c64fb | 76 | #define MAX_CPUS 16 |
b3a23197 | 77 | #define MAX_PILS 16 |
9a62fb24 | 78 | #define MAX_VSIMMS 4 |
420557e8 | 79 | |
b4ed08e0 BS |
80 | #define ESCC_CLOCK 4915200 |
81 | ||
8137cde8 | 82 | struct sun4m_hwdef { |
a8170e5e AK |
83 | hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
84 | hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; | |
85 | hwaddr serial_base, fd_base; | |
86 | hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; | |
87 | hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; | |
88 | hwaddr bpp_base, dbri_base, sx_base; | |
9a62fb24 | 89 | struct { |
a8170e5e | 90 | hwaddr reg_base, vram_base; |
9a62fb24 | 91 | } vsimm[MAX_VSIMMS]; |
a8170e5e | 92 | hwaddr ecc_base; |
3ebf5aaf | 93 | uint64_t max_mem; |
61999750 BS |
94 | uint32_t ecc_version; |
95 | uint32_t iommu_version; | |
96 | uint16_t machine_id; | |
97 | uint8_t nvram_machine_id; | |
36cd9210 BS |
98 | }; |
99 | ||
ddcd5531 GA |
100 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
101 | Error **errp) | |
81864572 | 102 | { |
48779e50 | 103 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
104 | } |
105 | ||
31688246 | 106 | static void nvram_init(Nvram *nvram, uint8_t *macaddr, |
43a34704 BS |
107 | const char *cmdline, const char *boot_devices, |
108 | ram_addr_t RAM_size, uint32_t kernel_size, | |
f930d07e | 109 | int width, int height, int depth, |
905fdcb5 | 110 | int nvram_machine_id, const char *arch) |
e80cfcfc | 111 | { |
d2c63fc1 | 112 | unsigned int i; |
2024c014 | 113 | int sysp_end; |
d2c63fc1 | 114 | uint8_t image[0x1ff0]; |
31688246 | 115 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
116 | |
117 | memset(image, '\0', sizeof(image)); | |
e80cfcfc | 118 | |
2024c014 TH |
119 | /* OpenBIOS nvram variables partition */ |
120 | sysp_end = chrp_nvram_create_system_partition(image, 0); | |
b6f479d3 | 121 | |
2024c014 TH |
122 | /* Free space partition */ |
123 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 124 | |
905fdcb5 BS |
125 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
126 | nvram_machine_id); | |
d2c63fc1 | 127 | |
31688246 HP |
128 | for (i = 0; i < sizeof(image); i++) { |
129 | (k->write)(nvram, i, image[i]); | |
130 | } | |
e80cfcfc FB |
131 | } |
132 | ||
98cec4a2 | 133 | void cpu_check_irqs(CPUSPARCState *env) |
327ac2e7 | 134 | { |
d8ed887b AF |
135 | CPUState *cs; |
136 | ||
5ee59930 AB |
137 | /* We should be holding the BQL before we mess with IRQs */ |
138 | g_assert(qemu_mutex_iothread_locked()); | |
139 | ||
327ac2e7 BS |
140 | if (env->pil_in && (env->interrupt_index == 0 || |
141 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
142 | unsigned int i; | |
143 | ||
144 | for (i = 15; i > 0; i--) { | |
145 | if (env->pil_in & (1 << i)) { | |
146 | int old_interrupt = env->interrupt_index; | |
147 | ||
148 | env->interrupt_index = TT_EXTINT | i; | |
f32d7ec5 | 149 | if (old_interrupt != env->interrupt_index) { |
c3affe56 | 150 | cs = CPU(sparc_env_get_cpu(env)); |
97bf4851 | 151 | trace_sun4m_cpu_interrupt(i); |
c3affe56 | 152 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
f32d7ec5 | 153 | } |
327ac2e7 BS |
154 | break; |
155 | } | |
156 | } | |
157 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { | |
d8ed887b | 158 | cs = CPU(sparc_env_get_cpu(env)); |
97bf4851 | 159 | trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); |
327ac2e7 | 160 | env->interrupt_index = 0; |
d8ed887b | 161 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
327ac2e7 BS |
162 | } |
163 | } | |
164 | ||
38c66cf2 | 165 | static void cpu_kick_irq(SPARCCPU *cpu) |
94ad5b00 | 166 | { |
38c66cf2 | 167 | CPUSPARCState *env = &cpu->env; |
259186a7 | 168 | CPUState *cs = CPU(cpu); |
38c66cf2 | 169 | |
259186a7 | 170 | cs->halted = 0; |
94ad5b00 | 171 | cpu_check_irqs(env); |
259186a7 | 172 | qemu_cpu_kick(cs); |
94ad5b00 PB |
173 | } |
174 | ||
b3a23197 BS |
175 | static void cpu_set_irq(void *opaque, int irq, int level) |
176 | { | |
e0bbf9b5 AF |
177 | SPARCCPU *cpu = opaque; |
178 | CPUSPARCState *env = &cpu->env; | |
b3a23197 BS |
179 | |
180 | if (level) { | |
97bf4851 | 181 | trace_sun4m_cpu_set_irq_raise(irq); |
327ac2e7 | 182 | env->pil_in |= 1 << irq; |
38c66cf2 | 183 | cpu_kick_irq(cpu); |
b3a23197 | 184 | } else { |
97bf4851 | 185 | trace_sun4m_cpu_set_irq_lower(irq); |
327ac2e7 BS |
186 | env->pil_in &= ~(1 << irq); |
187 | cpu_check_irqs(env); | |
b3a23197 BS |
188 | } |
189 | } | |
190 | ||
191 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) | |
192 | { | |
193 | } | |
194 | ||
c68ea704 FB |
195 | static void main_cpu_reset(void *opaque) |
196 | { | |
5414dec6 | 197 | SPARCCPU *cpu = opaque; |
259186a7 | 198 | CPUState *cs = CPU(cpu); |
3d29fbef | 199 | |
259186a7 AF |
200 | cpu_reset(cs); |
201 | cs->halted = 0; | |
3d29fbef BS |
202 | } |
203 | ||
204 | static void secondary_cpu_reset(void *opaque) | |
205 | { | |
5414dec6 | 206 | SPARCCPU *cpu = opaque; |
259186a7 | 207 | CPUState *cs = CPU(cpu); |
3d29fbef | 208 | |
259186a7 AF |
209 | cpu_reset(cs); |
210 | cs->halted = 1; | |
c68ea704 FB |
211 | } |
212 | ||
6d0c293d BS |
213 | static void cpu_halt_signal(void *opaque, int irq, int level) |
214 | { | |
4917cf44 AF |
215 | if (level && current_cpu) { |
216 | cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); | |
c3affe56 | 217 | } |
6d0c293d BS |
218 | } |
219 | ||
409dbce5 AJ |
220 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
221 | { | |
222 | return addr - 0xf0000000ULL; | |
223 | } | |
224 | ||
3ebf5aaf | 225 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
293f78bc | 226 | const char *initrd_filename, |
c227f099 | 227 | ram_addr_t RAM_size) |
3ebf5aaf BS |
228 | { |
229 | int linux_boot; | |
230 | unsigned int i; | |
231 | long initrd_size, kernel_size; | |
3c178e72 | 232 | uint8_t *ptr; |
3ebf5aaf BS |
233 | |
234 | linux_boot = (kernel_filename != NULL); | |
235 | ||
236 | kernel_size = 0; | |
237 | if (linux_boot) { | |
ca20cf32 BS |
238 | int bswap_needed; |
239 | ||
240 | #ifdef BSWAP_NEEDED | |
241 | bswap_needed = 1; | |
242 | #else | |
243 | bswap_needed = 0; | |
244 | #endif | |
4366e1db LM |
245 | kernel_size = load_elf(kernel_filename, NULL, |
246 | translate_kernel_address, NULL, | |
7ef295ea | 247 | NULL, NULL, NULL, 1, EM_SPARC, 0, 0); |
3ebf5aaf | 248 | if (kernel_size < 0) |
293f78bc | 249 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
250 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
251 | TARGET_PAGE_SIZE); | |
3ebf5aaf | 252 | if (kernel_size < 0) |
293f78bc BS |
253 | kernel_size = load_image_targphys(kernel_filename, |
254 | KERNEL_LOAD_ADDR, | |
255 | RAM_size - KERNEL_LOAD_ADDR); | |
3ebf5aaf | 256 | if (kernel_size < 0) { |
29bd7231 | 257 | error_report("could not load kernel '%s'", kernel_filename); |
3ebf5aaf BS |
258 | exit(1); |
259 | } | |
260 | ||
261 | /* load initrd */ | |
262 | initrd_size = 0; | |
263 | if (initrd_filename) { | |
293f78bc BS |
264 | initrd_size = load_image_targphys(initrd_filename, |
265 | INITRD_LOAD_ADDR, | |
266 | RAM_size - INITRD_LOAD_ADDR); | |
3ebf5aaf | 267 | if (initrd_size < 0) { |
29bd7231 AF |
268 | error_report("could not load initial ram disk '%s'", |
269 | initrd_filename); | |
3ebf5aaf BS |
270 | exit(1); |
271 | } | |
272 | } | |
273 | if (initrd_size > 0) { | |
274 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
0f0f8b61 TH |
275 | ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); |
276 | if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ | |
3c178e72 GH |
277 | stl_p(ptr + 16, INITRD_LOAD_ADDR); |
278 | stl_p(ptr + 20, initrd_size); | |
3ebf5aaf BS |
279 | break; |
280 | } | |
281 | } | |
282 | } | |
283 | } | |
284 | return kernel_size; | |
285 | } | |
286 | ||
a8170e5e | 287 | static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) |
4b48bf05 BS |
288 | { |
289 | DeviceState *dev; | |
290 | SysBusDevice *s; | |
291 | ||
f542ad03 | 292 | dev = qdev_create(NULL, TYPE_SUN4M_IOMMU); |
4b48bf05 | 293 | qdev_prop_set_uint32(dev, "version", version); |
e23a1b33 | 294 | qdev_init_nofail(dev); |
1356b98d | 295 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
296 | sysbus_connect_irq(s, 0, irq); |
297 | sysbus_mmio_map(s, 0, addr); | |
298 | ||
299 | return s; | |
300 | } | |
301 | ||
6aa62ed6 MCA |
302 | static void *sparc32_dma_init(hwaddr dma_base, |
303 | hwaddr esp_base, qemu_irq espdma_irq, | |
304 | hwaddr le_base, qemu_irq ledma_irq) | |
74ff8d90 | 305 | { |
6aa62ed6 MCA |
306 | DeviceState *dma; |
307 | ESPDMADeviceState *espdma; | |
308 | LEDMADeviceState *ledma; | |
309 | SysBusESPState *esp; | |
310 | SysBusPCNetState *lance; | |
74ff8d90 | 311 | |
6aa62ed6 MCA |
312 | dma = qdev_create(NULL, TYPE_SPARC32_DMA); |
313 | qdev_init_nofail(dma); | |
314 | sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); | |
74ff8d90 | 315 | |
6aa62ed6 MCA |
316 | espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( |
317 | OBJECT(dma), "espdma")); | |
318 | sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); | |
319 | ||
320 | esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp")); | |
321 | sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); | |
12850b1b | 322 | scsi_bus_legacy_handle_cmdline(&esp->esp.bus); |
6aa62ed6 MCA |
323 | |
324 | ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( | |
325 | OBJECT(dma), "ledma")); | |
326 | sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); | |
327 | ||
328 | lance = SYSBUS_PCNET(object_resolve_path_component( | |
329 | OBJECT(ledma), "lance")); | |
330 | sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); | |
331 | ||
332 | return dma; | |
74ff8d90 BS |
333 | } |
334 | ||
a8170e5e AK |
335 | static DeviceState *slavio_intctl_init(hwaddr addr, |
336 | hwaddr addrg, | |
462eda24 | 337 | qemu_irq **parent_irq) |
4b48bf05 BS |
338 | { |
339 | DeviceState *dev; | |
340 | SysBusDevice *s; | |
341 | unsigned int i, j; | |
342 | ||
343 | dev = qdev_create(NULL, "slavio_intctl"); | |
e23a1b33 | 344 | qdev_init_nofail(dev); |
4b48bf05 | 345 | |
1356b98d | 346 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
347 | |
348 | for (i = 0; i < MAX_CPUS; i++) { | |
349 | for (j = 0; j < MAX_PILS; j++) { | |
350 | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); | |
351 | } | |
352 | } | |
353 | sysbus_mmio_map(s, 0, addrg); | |
354 | for (i = 0; i < MAX_CPUS; i++) { | |
355 | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); | |
356 | } | |
357 | ||
358 | return dev; | |
359 | } | |
360 | ||
361 | #define SYS_TIMER_OFFSET 0x10000ULL | |
362 | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) | |
363 | ||
a8170e5e | 364 | static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, |
4b48bf05 BS |
365 | qemu_irq *cpu_irqs, unsigned int num_cpus) |
366 | { | |
367 | DeviceState *dev; | |
368 | SysBusDevice *s; | |
369 | unsigned int i; | |
370 | ||
371 | dev = qdev_create(NULL, "slavio_timer"); | |
372 | qdev_prop_set_uint32(dev, "num_cpus", num_cpus); | |
e23a1b33 | 373 | qdev_init_nofail(dev); |
1356b98d | 374 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
375 | sysbus_connect_irq(s, 0, master_irq); |
376 | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); | |
377 | ||
378 | for (i = 0; i < MAX_CPUS; i++) { | |
a8170e5e | 379 | sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); |
4b48bf05 BS |
380 | sysbus_connect_irq(s, i + 1, cpu_irqs[i]); |
381 | } | |
382 | } | |
383 | ||
bea42280 IM |
384 | static qemu_irq slavio_system_powerdown; |
385 | ||
386 | static void slavio_powerdown_req(Notifier *n, void *opaque) | |
387 | { | |
388 | qemu_irq_raise(slavio_system_powerdown); | |
389 | } | |
390 | ||
391 | static Notifier slavio_system_powerdown_notifier = { | |
392 | .notify = slavio_powerdown_req | |
393 | }; | |
394 | ||
4b48bf05 BS |
395 | #define MISC_LEDS 0x01600000 |
396 | #define MISC_CFG 0x01800000 | |
397 | #define MISC_DIAG 0x01a00000 | |
398 | #define MISC_MDM 0x01b00000 | |
399 | #define MISC_SYS 0x01f00000 | |
400 | ||
a8170e5e AK |
401 | static void slavio_misc_init(hwaddr base, |
402 | hwaddr aux1_base, | |
403 | hwaddr aux2_base, qemu_irq irq, | |
b2b6f6ec | 404 | qemu_irq fdc_tc) |
4b48bf05 BS |
405 | { |
406 | DeviceState *dev; | |
407 | SysBusDevice *s; | |
408 | ||
409 | dev = qdev_create(NULL, "slavio_misc"); | |
e23a1b33 | 410 | qdev_init_nofail(dev); |
1356b98d | 411 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
412 | if (base) { |
413 | /* 8 bit registers */ | |
414 | /* Slavio control */ | |
415 | sysbus_mmio_map(s, 0, base + MISC_CFG); | |
416 | /* Diagnostics */ | |
417 | sysbus_mmio_map(s, 1, base + MISC_DIAG); | |
418 | /* Modem control */ | |
419 | sysbus_mmio_map(s, 2, base + MISC_MDM); | |
420 | /* 16 bit registers */ | |
421 | /* ss600mp diag LEDs */ | |
422 | sysbus_mmio_map(s, 3, base + MISC_LEDS); | |
423 | /* 32 bit registers */ | |
424 | /* System control */ | |
425 | sysbus_mmio_map(s, 4, base + MISC_SYS); | |
426 | } | |
427 | if (aux1_base) { | |
428 | /* AUX 1 (Misc System Functions) */ | |
429 | sysbus_mmio_map(s, 5, aux1_base); | |
430 | } | |
431 | if (aux2_base) { | |
432 | /* AUX 2 (Software Powerdown Control) */ | |
433 | sysbus_mmio_map(s, 6, aux2_base); | |
434 | } | |
435 | sysbus_connect_irq(s, 0, irq); | |
436 | sysbus_connect_irq(s, 1, fdc_tc); | |
bea42280 IM |
437 | slavio_system_powerdown = qdev_get_gpio_in(dev, 0); |
438 | qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); | |
4b48bf05 BS |
439 | } |
440 | ||
a8170e5e | 441 | static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) |
4b48bf05 BS |
442 | { |
443 | DeviceState *dev; | |
444 | SysBusDevice *s; | |
445 | ||
446 | dev = qdev_create(NULL, "eccmemctl"); | |
447 | qdev_prop_set_uint32(dev, "version", version); | |
e23a1b33 | 448 | qdev_init_nofail(dev); |
1356b98d | 449 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
450 | sysbus_connect_irq(s, 0, irq); |
451 | sysbus_mmio_map(s, 0, base); | |
452 | if (version == 0) { // SS-600MP only | |
453 | sysbus_mmio_map(s, 1, base + 0x1000); | |
454 | } | |
455 | } | |
456 | ||
a8170e5e | 457 | static void apc_init(hwaddr power_base, qemu_irq cpu_halt) |
4b48bf05 BS |
458 | { |
459 | DeviceState *dev; | |
460 | SysBusDevice *s; | |
461 | ||
462 | dev = qdev_create(NULL, "apc"); | |
e23a1b33 | 463 | qdev_init_nofail(dev); |
1356b98d | 464 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
465 | /* Power management (APC) XXX: not a Slavio device */ |
466 | sysbus_mmio_map(s, 0, power_base); | |
467 | sysbus_connect_irq(s, 0, cpu_halt); | |
468 | } | |
469 | ||
55d7bfe2 | 470 | static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
4b48bf05 BS |
471 | int height, int depth) |
472 | { | |
473 | DeviceState *dev; | |
474 | SysBusDevice *s; | |
475 | ||
476 | dev = qdev_create(NULL, "SUNW,tcx"); | |
4b48bf05 BS |
477 | qdev_prop_set_uint32(dev, "vram_size", vram_size); |
478 | qdev_prop_set_uint16(dev, "width", width); | |
479 | qdev_prop_set_uint16(dev, "height", height); | |
480 | qdev_prop_set_uint16(dev, "depth", depth); | |
e23a1b33 | 481 | qdev_init_nofail(dev); |
1356b98d | 482 | s = SYS_BUS_DEVICE(dev); |
55d7bfe2 MCA |
483 | |
484 | /* 10/ROM : FCode ROM */ | |
da87dd7b | 485 | sysbus_mmio_map(s, 0, addr); |
55d7bfe2 MCA |
486 | /* 2/STIP : Stipple */ |
487 | sysbus_mmio_map(s, 1, addr + 0x04000000ULL); | |
488 | /* 3/BLIT : Blitter */ | |
489 | sysbus_mmio_map(s, 2, addr + 0x06000000ULL); | |
490 | /* 5/RSTIP : Raw Stipple */ | |
491 | sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); | |
492 | /* 6/RBLIT : Raw Blitter */ | |
493 | sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); | |
494 | /* 7/TEC : Transform Engine */ | |
495 | sysbus_mmio_map(s, 5, addr + 0x00700000ULL); | |
496 | /* 8/CMAP : DAC */ | |
497 | sysbus_mmio_map(s, 6, addr + 0x00200000ULL); | |
498 | /* 9/THC : */ | |
499 | if (depth == 8) { | |
500 | sysbus_mmio_map(s, 7, addr + 0x00300000ULL); | |
4b48bf05 | 501 | } else { |
55d7bfe2 | 502 | sysbus_mmio_map(s, 7, addr + 0x00301000ULL); |
4b48bf05 | 503 | } |
55d7bfe2 MCA |
504 | /* 11/DHC : */ |
505 | sysbus_mmio_map(s, 8, addr + 0x00240000ULL); | |
506 | /* 12/ALT : */ | |
507 | sysbus_mmio_map(s, 9, addr + 0x00280000ULL); | |
508 | /* 0/DFB8 : 8-bit plane */ | |
509 | sysbus_mmio_map(s, 10, addr + 0x00800000ULL); | |
510 | /* 1/DFB24 : 24bit plane */ | |
511 | sysbus_mmio_map(s, 11, addr + 0x02000000ULL); | |
512 | /* 4/RDFB32: Raw framebuffer. Control plane */ | |
513 | sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); | |
514 | /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ | |
515 | if (depth == 8) { | |
516 | sysbus_mmio_map(s, 13, addr + 0x00301000ULL); | |
517 | } | |
518 | ||
519 | sysbus_connect_irq(s, 0, irq); | |
4b48bf05 BS |
520 | } |
521 | ||
af87bf29 MCA |
522 | static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
523 | int height, int depth) | |
524 | { | |
525 | DeviceState *dev; | |
526 | SysBusDevice *s; | |
527 | ||
528 | dev = qdev_create(NULL, "cgthree"); | |
529 | qdev_prop_set_uint32(dev, "vram-size", vram_size); | |
530 | qdev_prop_set_uint16(dev, "width", width); | |
531 | qdev_prop_set_uint16(dev, "height", height); | |
532 | qdev_prop_set_uint16(dev, "depth", depth); | |
af87bf29 MCA |
533 | qdev_init_nofail(dev); |
534 | s = SYS_BUS_DEVICE(dev); | |
535 | ||
536 | /* FCode ROM */ | |
537 | sysbus_mmio_map(s, 0, addr); | |
538 | /* DAC */ | |
539 | sysbus_mmio_map(s, 1, addr + 0x400000ULL); | |
540 | /* 8-bit plane */ | |
541 | sysbus_mmio_map(s, 2, addr + 0x800000ULL); | |
542 | ||
543 | sysbus_connect_irq(s, 0, irq); | |
544 | } | |
545 | ||
325f2747 | 546 | /* NCR89C100/MACIO Internal ID register */ |
ef9dfa4c AF |
547 | |
548 | #define TYPE_MACIO_ID_REGISTER "macio_idreg" | |
549 | ||
325f2747 BS |
550 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
551 | ||
a8170e5e | 552 | static void idreg_init(hwaddr addr) |
325f2747 BS |
553 | { |
554 | DeviceState *dev; | |
555 | SysBusDevice *s; | |
556 | ||
ef9dfa4c | 557 | dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); |
e23a1b33 | 558 | qdev_init_nofail(dev); |
1356b98d | 559 | s = SYS_BUS_DEVICE(dev); |
325f2747 BS |
560 | |
561 | sysbus_mmio_map(s, 0, addr); | |
3c8133f9 PM |
562 | address_space_write_rom(&address_space_memory, addr, |
563 | MEMTXATTRS_UNSPECIFIED, | |
564 | idreg_data, sizeof(idreg_data)); | |
325f2747 BS |
565 | } |
566 | ||
ef9dfa4c AF |
567 | #define MACIO_ID_REGISTER(obj) \ |
568 | OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) | |
569 | ||
3150fa50 | 570 | typedef struct IDRegState { |
ef9dfa4c AF |
571 | SysBusDevice parent_obj; |
572 | ||
3150fa50 AK |
573 | MemoryRegion mem; |
574 | } IDRegState; | |
575 | ||
a2a5a7b5 | 576 | static void idreg_realize(DeviceState *ds, Error **errp) |
325f2747 | 577 | { |
a2a5a7b5 TH |
578 | IDRegState *s = MACIO_ID_REGISTER(ds); |
579 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
580 | Error *local_err = NULL; | |
581 | ||
582 | memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", | |
583 | sizeof(idreg_data), &local_err); | |
584 | if (local_err) { | |
585 | error_propagate(errp, local_err); | |
586 | return; | |
587 | } | |
325f2747 | 588 | |
c5705a77 | 589 | vmstate_register_ram_global(&s->mem); |
3150fa50 | 590 | memory_region_set_readonly(&s->mem, true); |
750ecd44 | 591 | sysbus_init_mmio(dev, &s->mem); |
999e12bb AL |
592 | } |
593 | ||
a2a5a7b5 TH |
594 | static void idreg_class_init(ObjectClass *oc, void *data) |
595 | { | |
596 | DeviceClass *dc = DEVICE_CLASS(oc); | |
597 | ||
598 | dc->realize = idreg_realize; | |
599 | } | |
600 | ||
8c43a6f0 | 601 | static const TypeInfo idreg_info = { |
ef9dfa4c | 602 | .name = TYPE_MACIO_ID_REGISTER, |
39bffca2 AL |
603 | .parent = TYPE_SYS_BUS_DEVICE, |
604 | .instance_size = sizeof(IDRegState), | |
a2a5a7b5 | 605 | .class_init = idreg_class_init, |
325f2747 BS |
606 | }; |
607 | ||
b3a49965 AF |
608 | #define TYPE_TCX_AFX "tcx_afx" |
609 | #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) | |
610 | ||
3150fa50 | 611 | typedef struct AFXState { |
b3a49965 AF |
612 | SysBusDevice parent_obj; |
613 | ||
3150fa50 AK |
614 | MemoryRegion mem; |
615 | } AFXState; | |
616 | ||
c5de386a | 617 | /* SS-5 TCX AFX register */ |
a8170e5e | 618 | static void afx_init(hwaddr addr) |
c5de386a AT |
619 | { |
620 | DeviceState *dev; | |
621 | SysBusDevice *s; | |
622 | ||
b3a49965 | 623 | dev = qdev_create(NULL, TYPE_TCX_AFX); |
c5de386a | 624 | qdev_init_nofail(dev); |
1356b98d | 625 | s = SYS_BUS_DEVICE(dev); |
c5de386a AT |
626 | |
627 | sysbus_mmio_map(s, 0, addr); | |
628 | } | |
629 | ||
a2a5a7b5 | 630 | static void afx_realize(DeviceState *ds, Error **errp) |
c5de386a | 631 | { |
a2a5a7b5 TH |
632 | AFXState *s = TCX_AFX(ds); |
633 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
634 | Error *local_err = NULL; | |
635 | ||
636 | memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, | |
637 | &local_err); | |
638 | if (local_err) { | |
639 | error_propagate(errp, local_err); | |
640 | return; | |
641 | } | |
c5de386a | 642 | |
c5705a77 | 643 | vmstate_register_ram_global(&s->mem); |
750ecd44 | 644 | sysbus_init_mmio(dev, &s->mem); |
999e12bb AL |
645 | } |
646 | ||
a2a5a7b5 TH |
647 | static void afx_class_init(ObjectClass *oc, void *data) |
648 | { | |
649 | DeviceClass *dc = DEVICE_CLASS(oc); | |
650 | ||
651 | dc->realize = afx_realize; | |
652 | } | |
653 | ||
8c43a6f0 | 654 | static const TypeInfo afx_info = { |
b3a49965 | 655 | .name = TYPE_TCX_AFX, |
39bffca2 AL |
656 | .parent = TYPE_SYS_BUS_DEVICE, |
657 | .instance_size = sizeof(AFXState), | |
a2a5a7b5 | 658 | .class_init = afx_class_init, |
c5de386a AT |
659 | }; |
660 | ||
e6f54c91 AF |
661 | #define TYPE_OPENPROM "openprom" |
662 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
663 | ||
3150fa50 | 664 | typedef struct PROMState { |
e6f54c91 AF |
665 | SysBusDevice parent_obj; |
666 | ||
3150fa50 AK |
667 | MemoryRegion prom; |
668 | } PROMState; | |
669 | ||
f48f6569 | 670 | /* Boot PROM (OpenBIOS) */ |
409dbce5 AJ |
671 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
672 | { | |
a8170e5e | 673 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
674 | return addr + *base_addr - PROM_VADDR; |
675 | } | |
676 | ||
a8170e5e | 677 | static void prom_init(hwaddr addr, const char *bios_name) |
f48f6569 BS |
678 | { |
679 | DeviceState *dev; | |
680 | SysBusDevice *s; | |
681 | char *filename; | |
682 | int ret; | |
683 | ||
e6f54c91 | 684 | dev = qdev_create(NULL, TYPE_OPENPROM); |
e23a1b33 | 685 | qdev_init_nofail(dev); |
1356b98d | 686 | s = SYS_BUS_DEVICE(dev); |
f48f6569 BS |
687 | |
688 | sysbus_mmio_map(s, 0, addr); | |
689 | ||
690 | /* load boot prom */ | |
691 | if (bios_name == NULL) { | |
692 | bios_name = PROM_FILENAME; | |
693 | } | |
694 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
695 | if (filename) { | |
4366e1db LM |
696 | ret = load_elf(filename, NULL, |
697 | translate_prom_address, &addr, NULL, | |
7ef295ea | 698 | NULL, NULL, 1, EM_SPARC, 0, 0); |
f48f6569 BS |
699 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
700 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
701 | } | |
7267c094 | 702 | g_free(filename); |
f48f6569 BS |
703 | } else { |
704 | ret = -1; | |
705 | } | |
706 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
29bd7231 | 707 | error_report("could not load prom '%s'", bios_name); |
f48f6569 BS |
708 | exit(1); |
709 | } | |
710 | } | |
711 | ||
a2a5a7b5 | 712 | static void prom_realize(DeviceState *ds, Error **errp) |
f48f6569 | 713 | { |
a2a5a7b5 TH |
714 | PROMState *s = OPENPROM(ds); |
715 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
716 | Error *local_err = NULL; | |
717 | ||
718 | memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", | |
719 | PROM_SIZE_MAX, &local_err); | |
720 | if (local_err) { | |
721 | error_propagate(errp, local_err); | |
722 | return; | |
723 | } | |
f48f6569 | 724 | |
c5705a77 | 725 | vmstate_register_ram_global(&s->prom); |
3150fa50 | 726 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 727 | sysbus_init_mmio(dev, &s->prom); |
f48f6569 BS |
728 | } |
729 | ||
999e12bb AL |
730 | static Property prom_properties[] = { |
731 | {/* end of property list */}, | |
732 | }; | |
733 | ||
734 | static void prom_class_init(ObjectClass *klass, void *data) | |
735 | { | |
39bffca2 | 736 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 737 | |
39bffca2 | 738 | dc->props = prom_properties; |
a2a5a7b5 | 739 | dc->realize = prom_realize; |
999e12bb AL |
740 | } |
741 | ||
8c43a6f0 | 742 | static const TypeInfo prom_info = { |
e6f54c91 | 743 | .name = TYPE_OPENPROM, |
39bffca2 AL |
744 | .parent = TYPE_SYS_BUS_DEVICE, |
745 | .instance_size = sizeof(PROMState), | |
746 | .class_init = prom_class_init, | |
f48f6569 BS |
747 | }; |
748 | ||
5ab6b4c6 AF |
749 | #define TYPE_SUN4M_MEMORY "memory" |
750 | #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) | |
751 | ||
752 | typedef struct RamDevice { | |
753 | SysBusDevice parent_obj; | |
754 | ||
3150fa50 | 755 | MemoryRegion ram; |
04843626 | 756 | uint64_t size; |
ee6847d1 GH |
757 | } RamDevice; |
758 | ||
a350db85 | 759 | /* System RAM */ |
dc8b6dd9 | 760 | static void ram_realize(DeviceState *dev, Error **errp) |
a350db85 | 761 | { |
5ab6b4c6 | 762 | RamDevice *d = SUN4M_RAM(dev); |
dc8b6dd9 | 763 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
a350db85 | 764 | |
8e7ba4ed DM |
765 | memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", |
766 | d->size); | |
dc8b6dd9 | 767 | sysbus_init_mmio(sbd, &d->ram); |
a350db85 BS |
768 | } |
769 | ||
a8170e5e | 770 | static void ram_init(hwaddr addr, ram_addr_t RAM_size, |
a350db85 BS |
771 | uint64_t max_mem) |
772 | { | |
773 | DeviceState *dev; | |
774 | SysBusDevice *s; | |
ee6847d1 | 775 | RamDevice *d; |
a350db85 BS |
776 | |
777 | /* allocate RAM */ | |
778 | if ((uint64_t)RAM_size > max_mem) { | |
0a2e467b PMD |
779 | error_report("Too much memory for this machine: %" PRId64 "," |
780 | " maximum %" PRId64, | |
781 | RAM_size / MiB, max_mem / MiB); | |
a350db85 BS |
782 | exit(1); |
783 | } | |
784 | dev = qdev_create(NULL, "memory"); | |
1356b98d | 785 | s = SYS_BUS_DEVICE(dev); |
a350db85 | 786 | |
5ab6b4c6 | 787 | d = SUN4M_RAM(dev); |
ee6847d1 | 788 | d->size = RAM_size; |
e23a1b33 | 789 | qdev_init_nofail(dev); |
ee6847d1 | 790 | |
a350db85 BS |
791 | sysbus_mmio_map(s, 0, addr); |
792 | } | |
793 | ||
999e12bb AL |
794 | static Property ram_properties[] = { |
795 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
796 | DEFINE_PROP_END_OF_LIST(), | |
797 | }; | |
798 | ||
799 | static void ram_class_init(ObjectClass *klass, void *data) | |
800 | { | |
39bffca2 | 801 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 802 | |
dc8b6dd9 | 803 | dc->realize = ram_realize; |
39bffca2 | 804 | dc->props = ram_properties; |
999e12bb AL |
805 | } |
806 | ||
8c43a6f0 | 807 | static const TypeInfo ram_info = { |
5ab6b4c6 | 808 | .name = TYPE_SUN4M_MEMORY, |
39bffca2 AL |
809 | .parent = TYPE_SYS_BUS_DEVICE, |
810 | .instance_size = sizeof(RamDevice), | |
811 | .class_init = ram_class_init, | |
a350db85 BS |
812 | }; |
813 | ||
49cbd887 | 814 | static void cpu_devinit(const char *cpu_type, unsigned int id, |
89835363 | 815 | uint64_t prom_addr, qemu_irq **cpu_irqs) |
666713c0 | 816 | { |
259186a7 | 817 | CPUState *cs; |
8968f588 | 818 | SPARCCPU *cpu; |
98cec4a2 | 819 | CPUSPARCState *env; |
666713c0 | 820 | |
49cbd887 | 821 | cpu = SPARC_CPU(cpu_create(cpu_type)); |
8968f588 | 822 | env = &cpu->env; |
666713c0 BS |
823 | |
824 | cpu_sparc_set_id(env, id); | |
825 | if (id == 0) { | |
5414dec6 | 826 | qemu_register_reset(main_cpu_reset, cpu); |
666713c0 | 827 | } else { |
5414dec6 | 828 | qemu_register_reset(secondary_cpu_reset, cpu); |
259186a7 AF |
829 | cs = CPU(cpu); |
830 | cs->halted = 1; | |
666713c0 | 831 | } |
e0bbf9b5 | 832 | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); |
666713c0 | 833 | env->prom_addr = prom_addr; |
666713c0 BS |
834 | } |
835 | ||
acfbe712 BS |
836 | static void dummy_fdc_tc(void *opaque, int irq, int level) |
837 | { | |
838 | } | |
839 | ||
6b63ef4d | 840 | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, |
3ef96221 | 841 | MachineState *machine) |
420557e8 | 842 | { |
61b97833 | 843 | DeviceState *slavio_intctl; |
713c45fa | 844 | unsigned int i; |
6aa62ed6 | 845 | void *nvram; |
9540619d | 846 | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; |
2582cfa0 | 847 | qemu_irq fdc_tc; |
5c6602c5 | 848 | unsigned long kernel_size; |
fd8014e1 | 849 | DriveInfo *fd[MAX_FD]; |
a88b362c | 850 | FWCfgState *fw_cfg; |
9a62fb24 | 851 | unsigned int num_vsimms; |
2cc75c32 LV |
852 | DeviceState *dev; |
853 | SysBusDevice *s; | |
420557e8 | 854 | |
ba3c64fb FB |
855 | /* init CPUs */ |
856 | for(i = 0; i < smp_cpus; i++) { | |
49cbd887 | 857 | cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); |
ba3c64fb | 858 | } |
b3a23197 BS |
859 | |
860 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
861 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
862 | ||
3ebf5aaf | 863 | |
3ebf5aaf | 864 | /* set up devices */ |
3ef96221 | 865 | ram_init(0, machine->ram_size, hwdef->max_mem); |
676d9b9b AT |
866 | /* models without ECC don't trap when missing ram is accessed */ |
867 | if (!hwdef->ecc_base) { | |
3ef96221 | 868 | empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); |
676d9b9b | 869 | } |
a350db85 | 870 | |
f48f6569 BS |
871 | prom_init(hwdef->slavio_base, bios_name); |
872 | ||
d453c2c3 BS |
873 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
874 | hwdef->intctl_base + 0x10000ULL, | |
462eda24 | 875 | cpu_irqs); |
a1961a4b BS |
876 | |
877 | for (i = 0; i < 32; i++) { | |
d453c2c3 | 878 | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
a1961a4b BS |
879 | } |
880 | for (i = 0; i < MAX_CPUS; i++) { | |
d453c2c3 | 881 | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); |
a1961a4b | 882 | } |
b3a23197 | 883 | |
fe096129 | 884 | if (hwdef->idreg_base) { |
325f2747 | 885 | idreg_init(hwdef->idreg_base); |
4c2485de BS |
886 | } |
887 | ||
c5de386a AT |
888 | if (hwdef->afx_base) { |
889 | afx_init(hwdef->afx_base); | |
890 | } | |
891 | ||
6aa62ed6 | 892 | iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); |
ff403da6 | 893 | |
3386376c AT |
894 | if (hwdef->iommu_pad_base) { |
895 | /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. | |
896 | Software shouldn't use aliased addresses, neither should it crash | |
897 | when does. Using empty_slot instead of aliasing can help with | |
898 | debugging such accesses */ | |
899 | empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); | |
900 | } | |
901 | ||
6aa62ed6 MCA |
902 | sparc32_dma_init(hwdef->dma_base, |
903 | hwdef->esp_base, slavio_irq[18], | |
904 | hwdef->le_base, slavio_irq[16]); | |
e6ca02a4 | 905 | |
eee0b836 | 906 | if (graphic_depth != 8 && graphic_depth != 24) { |
af87bf29 | 907 | error_report("Unsupported depth: %d", graphic_depth); |
eee0b836 BS |
908 | exit (1); |
909 | } | |
9a62fb24 BB |
910 | num_vsimms = 0; |
911 | if (num_vsimms == 0) { | |
af87bf29 MCA |
912 | if (vga_interface_type == VGA_CG3) { |
913 | if (graphic_depth != 8) { | |
914 | error_report("Unsupported depth: %d", graphic_depth); | |
915 | exit(1); | |
916 | } | |
917 | ||
918 | if (!(graphic_width == 1024 && graphic_height == 768) && | |
919 | !(graphic_width == 1152 && graphic_height == 900)) { | |
920 | error_report("Unsupported resolution: %d x %d", graphic_width, | |
921 | graphic_height); | |
922 | exit(1); | |
923 | } | |
924 | ||
925 | /* sbus irq 5 */ | |
926 | cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, | |
927 | graphic_width, graphic_height, graphic_depth); | |
928 | } else { | |
929 | /* If no display specified, default to TCX */ | |
930 | if (graphic_depth != 8 && graphic_depth != 24) { | |
931 | error_report("Unsupported depth: %d", graphic_depth); | |
932 | exit(1); | |
933 | } | |
934 | ||
935 | if (!(graphic_width == 1024 && graphic_height == 768)) { | |
936 | error_report("Unsupported resolution: %d x %d", | |
937 | graphic_width, graphic_height); | |
938 | exit(1); | |
939 | } | |
940 | ||
55d7bfe2 MCA |
941 | tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, |
942 | graphic_width, graphic_height, graphic_depth); | |
af87bf29 | 943 | } |
9a62fb24 BB |
944 | } |
945 | ||
946 | for (i = num_vsimms; i < MAX_VSIMMS; i++) { | |
947 | /* vsimm registers probed by OBP */ | |
948 | if (hwdef->vsimm[i].reg_base) { | |
949 | empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); | |
950 | } | |
951 | } | |
952 | ||
953 | if (hwdef->sx_base) { | |
954 | empty_slot_init(hwdef->sx_base, 0x2000); | |
955 | } | |
dbe06e18 | 956 | |
6de04973 | 957 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); |
81732d19 | 958 | |
c533e0b3 | 959 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); |
81732d19 | 960 | |
5cbdb3a3 SW |
961 | /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device |
962 | Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ | |
2cc75c32 LV |
963 | dev = qdev_create(NULL, TYPE_ESCC); |
964 | qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); | |
965 | qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); | |
966 | qdev_prop_set_uint32(dev, "it_shift", 1); | |
967 | qdev_prop_set_chr(dev, "chrB", NULL); | |
968 | qdev_prop_set_chr(dev, "chrA", NULL); | |
969 | qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); | |
970 | qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); | |
971 | qdev_init_nofail(dev); | |
972 | s = SYS_BUS_DEVICE(dev); | |
973 | sysbus_connect_irq(s, 0, slavio_irq[14]); | |
974 | sysbus_connect_irq(s, 1, slavio_irq[14]); | |
975 | sysbus_mmio_map(s, 0, hwdef->ms_kb_base); | |
976 | ||
977 | dev = qdev_create(NULL, TYPE_ESCC); | |
978 | qdev_prop_set_uint32(dev, "disabled", 0); | |
979 | qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); | |
980 | qdev_prop_set_uint32(dev, "it_shift", 1); | |
9bca0edb PM |
981 | qdev_prop_set_chr(dev, "chrB", serial_hd(1)); |
982 | qdev_prop_set_chr(dev, "chrA", serial_hd(0)); | |
2cc75c32 LV |
983 | qdev_prop_set_uint32(dev, "chnBtype", escc_serial); |
984 | qdev_prop_set_uint32(dev, "chnAtype", escc_serial); | |
985 | qdev_init_nofail(dev); | |
986 | ||
987 | s = SYS_BUS_DEVICE(dev); | |
988 | sysbus_connect_irq(s, 0, slavio_irq[15]); | |
989 | sysbus_connect_irq(s, 1, slavio_irq[15]); | |
990 | sysbus_mmio_map(s, 0, hwdef->serial_base); | |
741402f9 | 991 | |
2582cfa0 | 992 | if (hwdef->apc_base) { |
ca43b97b | 993 | apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); |
2582cfa0 | 994 | } |
2be17ebd | 995 | |
fe096129 | 996 | if (hwdef->fd_base) { |
e4bcb14c | 997 | /* there is zero or one floppy drive */ |
309e60bd | 998 | memset(fd, 0, sizeof(fd)); |
fd8014e1 | 999 | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
c533e0b3 | 1000 | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, |
2582cfa0 | 1001 | &fdc_tc); |
acfbe712 | 1002 | } else { |
ca43b97b | 1003 | fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); |
e4bcb14c TS |
1004 | } |
1005 | ||
acfbe712 BS |
1006 | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
1007 | slavio_irq[30], fdc_tc); | |
1008 | ||
fa28ec52 BS |
1009 | if (hwdef->cs_base) { |
1010 | sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, | |
c533e0b3 | 1011 | slavio_irq[5]); |
fa28ec52 | 1012 | } |
b3ceef24 | 1013 | |
9a62fb24 BB |
1014 | if (hwdef->dbri_base) { |
1015 | /* ISDN chip with attached CS4215 audio codec */ | |
1016 | /* prom space */ | |
1017 | empty_slot_init(hwdef->dbri_base+0x1000, 0x30); | |
1018 | /* reg space */ | |
1019 | empty_slot_init(hwdef->dbri_base+0x10000, 0x100); | |
1020 | } | |
1021 | ||
1022 | if (hwdef->bpp_base) { | |
1023 | /* parallel port */ | |
1024 | empty_slot_init(hwdef->bpp_base, 0x20); | |
1025 | } | |
1026 | ||
3ef96221 MA |
1027 | kernel_size = sun4m_load_kernel(machine->kernel_filename, |
1028 | machine->initrd_filename, | |
1029 | machine->ram_size); | |
36cd9210 | 1030 | |
3ef96221 MA |
1031 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, |
1032 | machine->boot_order, machine->ram_size, kernel_size, | |
1033 | graphic_width, graphic_height, graphic_depth, | |
1034 | hwdef->nvram_machine_id, "Sun4m"); | |
7eb0c8e8 | 1035 | |
fe096129 | 1036 | if (hwdef->ecc_base) |
c533e0b3 | 1037 | ecc_init(hwdef->ecc_base, slavio_irq[28], |
e42c20b4 | 1038 | hwdef->ecc_version); |
3cce6243 | 1039 | |
84983214 MCA |
1040 | dev = qdev_create(NULL, TYPE_FW_CFG_MEM); |
1041 | fw_cfg = FW_CFG(dev); | |
1042 | qdev_prop_set_uint32(dev, "data_width", 1); | |
1043 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
1044 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, | |
1045 | OBJECT(fw_cfg), NULL); | |
1046 | qdev_init_nofail(dev); | |
1047 | s = SYS_BUS_DEVICE(dev); | |
1048 | sysbus_mmio_map(s, 0, CFG_ADDR); | |
1049 | sysbus_mmio_map(s, 1, CFG_ADDR + 2); | |
1050 | ||
5836d168 | 1051 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
70db9222 | 1052 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
905fdcb5 BS |
1053 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1054 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
fbfcf955 | 1055 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
b96919e0 MCA |
1056 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); |
1057 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); | |
513f789f BS |
1058 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1059 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 1060 | if (machine->kernel_cmdline) { |
513f789f | 1061 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
6b63ef4d | 1062 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, |
3ef96221 MA |
1063 | machine->kernel_cmdline); |
1064 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
748a4ee3 | 1065 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 | 1066 | strlen(machine->kernel_cmdline) + 1); |
513f789f BS |
1067 | } else { |
1068 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
748a4ee3 | 1069 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f BS |
1070 | } |
1071 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
1072 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used | |
3ef96221 | 1073 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
513f789f | 1074 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
36cd9210 BS |
1075 | } |
1076 | ||
905fdcb5 | 1077 | enum { |
905fdcb5 BS |
1078 | ss5_id = 32, |
1079 | vger_id, | |
1080 | lx_id, | |
1081 | ss4_id, | |
1082 | scls_id, | |
1083 | sbook_id, | |
1084 | ss10_id = 64, | |
1085 | ss20_id, | |
1086 | ss600mp_id, | |
905fdcb5 BS |
1087 | }; |
1088 | ||
8137cde8 | 1089 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
36cd9210 BS |
1090 | /* SS-5 */ |
1091 | { | |
1092 | .iommu_base = 0x10000000, | |
3386376c AT |
1093 | .iommu_pad_base = 0x10004000, |
1094 | .iommu_pad_len = 0x0fffb000, | |
36cd9210 BS |
1095 | .tcx_base = 0x50000000, |
1096 | .cs_base = 0x6c000000, | |
384ccb5d | 1097 | .slavio_base = 0x70000000, |
36cd9210 BS |
1098 | .ms_kb_base = 0x71000000, |
1099 | .serial_base = 0x71100000, | |
1100 | .nvram_base = 0x71200000, | |
1101 | .fd_base = 0x71400000, | |
1102 | .counter_base = 0x71d00000, | |
1103 | .intctl_base = 0x71e00000, | |
4c2485de | 1104 | .idreg_base = 0x78000000, |
36cd9210 BS |
1105 | .dma_base = 0x78400000, |
1106 | .esp_base = 0x78800000, | |
1107 | .le_base = 0x78c00000, | |
127fc407 | 1108 | .apc_base = 0x6a000000, |
c5de386a | 1109 | .afx_base = 0x6e000000, |
0019ad53 BS |
1110 | .aux1_base = 0x71900000, |
1111 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1112 | .nvram_machine_id = 0x80, |
1113 | .machine_id = ss5_id, | |
cf3102ac | 1114 | .iommu_version = 0x05000000, |
3ebf5aaf | 1115 | .max_mem = 0x10000000, |
e0353fe2 BS |
1116 | }, |
1117 | /* SS-10 */ | |
e0353fe2 | 1118 | { |
5dcb6b91 BS |
1119 | .iommu_base = 0xfe0000000ULL, |
1120 | .tcx_base = 0xe20000000ULL, | |
5dcb6b91 BS |
1121 | .slavio_base = 0xff0000000ULL, |
1122 | .ms_kb_base = 0xff1000000ULL, | |
1123 | .serial_base = 0xff1100000ULL, | |
1124 | .nvram_base = 0xff1200000ULL, | |
1125 | .fd_base = 0xff1700000ULL, | |
1126 | .counter_base = 0xff1300000ULL, | |
1127 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1128 | .idreg_base = 0xef0000000ULL, |
5dcb6b91 BS |
1129 | .dma_base = 0xef0400000ULL, |
1130 | .esp_base = 0xef0800000ULL, | |
1131 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 1132 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
1133 | .aux1_base = 0xff1800000ULL, |
1134 | .aux2_base = 0xff1a01000ULL, | |
7eb0c8e8 BS |
1135 | .ecc_base = 0xf00000000ULL, |
1136 | .ecc_version = 0x10000000, // version 0, implementation 1 | |
905fdcb5 BS |
1137 | .nvram_machine_id = 0x72, |
1138 | .machine_id = ss10_id, | |
7fbfb139 | 1139 | .iommu_version = 0x03000000, |
6ef05b95 | 1140 | .max_mem = 0xf00000000ULL, |
36cd9210 | 1141 | }, |
6a3b9cc9 BS |
1142 | /* SS-600MP */ |
1143 | { | |
1144 | .iommu_base = 0xfe0000000ULL, | |
1145 | .tcx_base = 0xe20000000ULL, | |
6a3b9cc9 BS |
1146 | .slavio_base = 0xff0000000ULL, |
1147 | .ms_kb_base = 0xff1000000ULL, | |
1148 | .serial_base = 0xff1100000ULL, | |
1149 | .nvram_base = 0xff1200000ULL, | |
6a3b9cc9 BS |
1150 | .counter_base = 0xff1300000ULL, |
1151 | .intctl_base = 0xff1400000ULL, | |
1152 | .dma_base = 0xef0081000ULL, | |
1153 | .esp_base = 0xef0080000ULL, | |
1154 | .le_base = 0xef0060000ULL, | |
0019ad53 | 1155 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
1156 | .aux1_base = 0xff1800000ULL, |
1157 | .aux2_base = 0xff1a01000ULL, // XXX should not exist | |
7eb0c8e8 BS |
1158 | .ecc_base = 0xf00000000ULL, |
1159 | .ecc_version = 0x00000000, // version 0, implementation 0 | |
905fdcb5 BS |
1160 | .nvram_machine_id = 0x71, |
1161 | .machine_id = ss600mp_id, | |
7fbfb139 | 1162 | .iommu_version = 0x01000000, |
6ef05b95 | 1163 | .max_mem = 0xf00000000ULL, |
6a3b9cc9 | 1164 | }, |
ae40972f BS |
1165 | /* SS-20 */ |
1166 | { | |
1167 | .iommu_base = 0xfe0000000ULL, | |
1168 | .tcx_base = 0xe20000000ULL, | |
ae40972f BS |
1169 | .slavio_base = 0xff0000000ULL, |
1170 | .ms_kb_base = 0xff1000000ULL, | |
1171 | .serial_base = 0xff1100000ULL, | |
1172 | .nvram_base = 0xff1200000ULL, | |
1173 | .fd_base = 0xff1700000ULL, | |
1174 | .counter_base = 0xff1300000ULL, | |
1175 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1176 | .idreg_base = 0xef0000000ULL, |
ae40972f BS |
1177 | .dma_base = 0xef0400000ULL, |
1178 | .esp_base = 0xef0800000ULL, | |
1179 | .le_base = 0xef0c00000ULL, | |
9a62fb24 | 1180 | .bpp_base = 0xef4800000ULL, |
0019ad53 | 1181 | .apc_base = 0xefa000000ULL, // XXX should not exist |
577d8dd4 BS |
1182 | .aux1_base = 0xff1800000ULL, |
1183 | .aux2_base = 0xff1a01000ULL, | |
9a62fb24 BB |
1184 | .dbri_base = 0xee0000000ULL, |
1185 | .sx_base = 0xf80000000ULL, | |
1186 | .vsimm = { | |
1187 | { | |
1188 | .reg_base = 0x9c000000ULL, | |
1189 | .vram_base = 0xfc000000ULL | |
1190 | }, { | |
1191 | .reg_base = 0x90000000ULL, | |
1192 | .vram_base = 0xf0000000ULL | |
1193 | }, { | |
1194 | .reg_base = 0x94000000ULL | |
1195 | }, { | |
1196 | .reg_base = 0x98000000ULL | |
1197 | } | |
1198 | }, | |
ae40972f BS |
1199 | .ecc_base = 0xf00000000ULL, |
1200 | .ecc_version = 0x20000000, // version 0, implementation 2 | |
905fdcb5 BS |
1201 | .nvram_machine_id = 0x72, |
1202 | .machine_id = ss20_id, | |
ae40972f | 1203 | .iommu_version = 0x13000000, |
6ef05b95 | 1204 | .max_mem = 0xf00000000ULL, |
ae40972f | 1205 | }, |
a526a31c BS |
1206 | /* Voyager */ |
1207 | { | |
1208 | .iommu_base = 0x10000000, | |
1209 | .tcx_base = 0x50000000, | |
a526a31c BS |
1210 | .slavio_base = 0x70000000, |
1211 | .ms_kb_base = 0x71000000, | |
1212 | .serial_base = 0x71100000, | |
1213 | .nvram_base = 0x71200000, | |
1214 | .fd_base = 0x71400000, | |
1215 | .counter_base = 0x71d00000, | |
1216 | .intctl_base = 0x71e00000, | |
1217 | .idreg_base = 0x78000000, | |
1218 | .dma_base = 0x78400000, | |
1219 | .esp_base = 0x78800000, | |
1220 | .le_base = 0x78c00000, | |
1221 | .apc_base = 0x71300000, // pmc | |
1222 | .aux1_base = 0x71900000, | |
1223 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1224 | .nvram_machine_id = 0x80, |
1225 | .machine_id = vger_id, | |
a526a31c | 1226 | .iommu_version = 0x05000000, |
a526a31c | 1227 | .max_mem = 0x10000000, |
a526a31c BS |
1228 | }, |
1229 | /* LX */ | |
1230 | { | |
1231 | .iommu_base = 0x10000000, | |
3386376c AT |
1232 | .iommu_pad_base = 0x10004000, |
1233 | .iommu_pad_len = 0x0fffb000, | |
a526a31c | 1234 | .tcx_base = 0x50000000, |
a526a31c BS |
1235 | .slavio_base = 0x70000000, |
1236 | .ms_kb_base = 0x71000000, | |
1237 | .serial_base = 0x71100000, | |
1238 | .nvram_base = 0x71200000, | |
1239 | .fd_base = 0x71400000, | |
1240 | .counter_base = 0x71d00000, | |
1241 | .intctl_base = 0x71e00000, | |
1242 | .idreg_base = 0x78000000, | |
1243 | .dma_base = 0x78400000, | |
1244 | .esp_base = 0x78800000, | |
1245 | .le_base = 0x78c00000, | |
a526a31c BS |
1246 | .aux1_base = 0x71900000, |
1247 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1248 | .nvram_machine_id = 0x80, |
1249 | .machine_id = lx_id, | |
a526a31c | 1250 | .iommu_version = 0x04000000, |
a526a31c | 1251 | .max_mem = 0x10000000, |
a526a31c BS |
1252 | }, |
1253 | /* SS-4 */ | |
1254 | { | |
1255 | .iommu_base = 0x10000000, | |
1256 | .tcx_base = 0x50000000, | |
1257 | .cs_base = 0x6c000000, | |
1258 | .slavio_base = 0x70000000, | |
1259 | .ms_kb_base = 0x71000000, | |
1260 | .serial_base = 0x71100000, | |
1261 | .nvram_base = 0x71200000, | |
1262 | .fd_base = 0x71400000, | |
1263 | .counter_base = 0x71d00000, | |
1264 | .intctl_base = 0x71e00000, | |
1265 | .idreg_base = 0x78000000, | |
1266 | .dma_base = 0x78400000, | |
1267 | .esp_base = 0x78800000, | |
1268 | .le_base = 0x78c00000, | |
1269 | .apc_base = 0x6a000000, | |
1270 | .aux1_base = 0x71900000, | |
1271 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1272 | .nvram_machine_id = 0x80, |
1273 | .machine_id = ss4_id, | |
a526a31c | 1274 | .iommu_version = 0x05000000, |
a526a31c | 1275 | .max_mem = 0x10000000, |
a526a31c BS |
1276 | }, |
1277 | /* SPARCClassic */ | |
1278 | { | |
1279 | .iommu_base = 0x10000000, | |
1280 | .tcx_base = 0x50000000, | |
a526a31c BS |
1281 | .slavio_base = 0x70000000, |
1282 | .ms_kb_base = 0x71000000, | |
1283 | .serial_base = 0x71100000, | |
1284 | .nvram_base = 0x71200000, | |
1285 | .fd_base = 0x71400000, | |
1286 | .counter_base = 0x71d00000, | |
1287 | .intctl_base = 0x71e00000, | |
1288 | .idreg_base = 0x78000000, | |
1289 | .dma_base = 0x78400000, | |
1290 | .esp_base = 0x78800000, | |
1291 | .le_base = 0x78c00000, | |
1292 | .apc_base = 0x6a000000, | |
1293 | .aux1_base = 0x71900000, | |
1294 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1295 | .nvram_machine_id = 0x80, |
1296 | .machine_id = scls_id, | |
a526a31c | 1297 | .iommu_version = 0x05000000, |
a526a31c | 1298 | .max_mem = 0x10000000, |
a526a31c BS |
1299 | }, |
1300 | /* SPARCbook */ | |
1301 | { | |
1302 | .iommu_base = 0x10000000, | |
1303 | .tcx_base = 0x50000000, // XXX | |
a526a31c BS |
1304 | .slavio_base = 0x70000000, |
1305 | .ms_kb_base = 0x71000000, | |
1306 | .serial_base = 0x71100000, | |
1307 | .nvram_base = 0x71200000, | |
1308 | .fd_base = 0x71400000, | |
1309 | .counter_base = 0x71d00000, | |
1310 | .intctl_base = 0x71e00000, | |
1311 | .idreg_base = 0x78000000, | |
1312 | .dma_base = 0x78400000, | |
1313 | .esp_base = 0x78800000, | |
1314 | .le_base = 0x78c00000, | |
1315 | .apc_base = 0x6a000000, | |
1316 | .aux1_base = 0x71900000, | |
1317 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1318 | .nvram_machine_id = 0x80, |
1319 | .machine_id = sbook_id, | |
a526a31c | 1320 | .iommu_version = 0x05000000, |
a526a31c | 1321 | .max_mem = 0x10000000, |
a526a31c | 1322 | }, |
36cd9210 BS |
1323 | }; |
1324 | ||
36cd9210 | 1325 | /* SPARCstation 5 hardware initialisation */ |
3ef96221 | 1326 | static void ss5_init(MachineState *machine) |
36cd9210 | 1327 | { |
3ef96221 | 1328 | sun4m_hw_init(&sun4m_hwdefs[0], machine); |
420557e8 | 1329 | } |
c0e564d5 | 1330 | |
e0353fe2 | 1331 | /* SPARCstation 10 hardware initialisation */ |
3ef96221 | 1332 | static void ss10_init(MachineState *machine) |
e0353fe2 | 1333 | { |
3ef96221 | 1334 | sun4m_hw_init(&sun4m_hwdefs[1], machine); |
e0353fe2 BS |
1335 | } |
1336 | ||
6a3b9cc9 | 1337 | /* SPARCserver 600MP hardware initialisation */ |
3ef96221 | 1338 | static void ss600mp_init(MachineState *machine) |
6a3b9cc9 | 1339 | { |
3ef96221 | 1340 | sun4m_hw_init(&sun4m_hwdefs[2], machine); |
6a3b9cc9 BS |
1341 | } |
1342 | ||
ae40972f | 1343 | /* SPARCstation 20 hardware initialisation */ |
3ef96221 | 1344 | static void ss20_init(MachineState *machine) |
ae40972f | 1345 | { |
3ef96221 | 1346 | sun4m_hw_init(&sun4m_hwdefs[3], machine); |
ee76f82e BS |
1347 | } |
1348 | ||
a526a31c | 1349 | /* SPARCstation Voyager hardware initialisation */ |
3ef96221 | 1350 | static void vger_init(MachineState *machine) |
a526a31c | 1351 | { |
3ef96221 | 1352 | sun4m_hw_init(&sun4m_hwdefs[4], machine); |
a526a31c BS |
1353 | } |
1354 | ||
1355 | /* SPARCstation LX hardware initialisation */ | |
3ef96221 | 1356 | static void ss_lx_init(MachineState *machine) |
a526a31c | 1357 | { |
3ef96221 | 1358 | sun4m_hw_init(&sun4m_hwdefs[5], machine); |
a526a31c BS |
1359 | } |
1360 | ||
1361 | /* SPARCstation 4 hardware initialisation */ | |
3ef96221 | 1362 | static void ss4_init(MachineState *machine) |
a526a31c | 1363 | { |
3ef96221 | 1364 | sun4m_hw_init(&sun4m_hwdefs[6], machine); |
a526a31c BS |
1365 | } |
1366 | ||
1367 | /* SPARCClassic hardware initialisation */ | |
3ef96221 | 1368 | static void scls_init(MachineState *machine) |
a526a31c | 1369 | { |
3ef96221 | 1370 | sun4m_hw_init(&sun4m_hwdefs[7], machine); |
a526a31c BS |
1371 | } |
1372 | ||
1373 | /* SPARCbook hardware initialisation */ | |
3ef96221 | 1374 | static void sbook_init(MachineState *machine) |
a526a31c | 1375 | { |
3ef96221 | 1376 | sun4m_hw_init(&sun4m_hwdefs[8], machine); |
a526a31c BS |
1377 | } |
1378 | ||
8a661aea | 1379 | static void ss5_class_init(ObjectClass *oc, void *data) |
e264d29d | 1380 | { |
8a661aea AF |
1381 | MachineClass *mc = MACHINE_CLASS(oc); |
1382 | ||
e264d29d EH |
1383 | mc->desc = "Sun4m platform, SPARCstation 5"; |
1384 | mc->init = ss5_init; | |
1385 | mc->block_default_type = IF_SCSI; | |
1386 | mc->is_default = 1; | |
1387 | mc->default_boot_order = "c"; | |
49cbd887 | 1388 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
e264d29d | 1389 | } |
e0353fe2 | 1390 | |
8a661aea AF |
1391 | static const TypeInfo ss5_type = { |
1392 | .name = MACHINE_TYPE_NAME("SS-5"), | |
1393 | .parent = TYPE_MACHINE, | |
1394 | .class_init = ss5_class_init, | |
1395 | }; | |
6a3b9cc9 | 1396 | |
8a661aea | 1397 | static void ss10_class_init(ObjectClass *oc, void *data) |
e264d29d | 1398 | { |
8a661aea AF |
1399 | MachineClass *mc = MACHINE_CLASS(oc); |
1400 | ||
e264d29d EH |
1401 | mc->desc = "Sun4m platform, SPARCstation 10"; |
1402 | mc->init = ss10_init; | |
1403 | mc->block_default_type = IF_SCSI; | |
1404 | mc->max_cpus = 4; | |
1405 | mc->default_boot_order = "c"; | |
49cbd887 | 1406 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
e264d29d | 1407 | } |
ae40972f | 1408 | |
8a661aea AF |
1409 | static const TypeInfo ss10_type = { |
1410 | .name = MACHINE_TYPE_NAME("SS-10"), | |
1411 | .parent = TYPE_MACHINE, | |
1412 | .class_init = ss10_class_init, | |
1413 | }; | |
ae40972f | 1414 | |
8a661aea | 1415 | static void ss600mp_class_init(ObjectClass *oc, void *data) |
e264d29d | 1416 | { |
8a661aea AF |
1417 | MachineClass *mc = MACHINE_CLASS(oc); |
1418 | ||
e264d29d EH |
1419 | mc->desc = "Sun4m platform, SPARCserver 600MP"; |
1420 | mc->init = ss600mp_init; | |
1421 | mc->block_default_type = IF_SCSI; | |
1422 | mc->max_cpus = 4; | |
1423 | mc->default_boot_order = "c"; | |
49cbd887 | 1424 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
e264d29d | 1425 | } |
a526a31c | 1426 | |
8a661aea AF |
1427 | static const TypeInfo ss600mp_type = { |
1428 | .name = MACHINE_TYPE_NAME("SS-600MP"), | |
1429 | .parent = TYPE_MACHINE, | |
1430 | .class_init = ss600mp_class_init, | |
1431 | }; | |
a526a31c | 1432 | |
8a661aea | 1433 | static void ss20_class_init(ObjectClass *oc, void *data) |
e264d29d | 1434 | { |
8a661aea AF |
1435 | MachineClass *mc = MACHINE_CLASS(oc); |
1436 | ||
e264d29d EH |
1437 | mc->desc = "Sun4m platform, SPARCstation 20"; |
1438 | mc->init = ss20_init; | |
1439 | mc->block_default_type = IF_SCSI; | |
1440 | mc->max_cpus = 4; | |
1441 | mc->default_boot_order = "c"; | |
49cbd887 | 1442 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
e264d29d | 1443 | } |
a526a31c | 1444 | |
8a661aea AF |
1445 | static const TypeInfo ss20_type = { |
1446 | .name = MACHINE_TYPE_NAME("SS-20"), | |
1447 | .parent = TYPE_MACHINE, | |
1448 | .class_init = ss20_class_init, | |
1449 | }; | |
a526a31c | 1450 | |
8a661aea | 1451 | static void voyager_class_init(ObjectClass *oc, void *data) |
e264d29d | 1452 | { |
8a661aea AF |
1453 | MachineClass *mc = MACHINE_CLASS(oc); |
1454 | ||
e264d29d EH |
1455 | mc->desc = "Sun4m platform, SPARCstation Voyager"; |
1456 | mc->init = vger_init; | |
1457 | mc->block_default_type = IF_SCSI; | |
1458 | mc->default_boot_order = "c"; | |
49cbd887 | 1459 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
e264d29d EH |
1460 | } |
1461 | ||
8a661aea AF |
1462 | static const TypeInfo voyager_type = { |
1463 | .name = MACHINE_TYPE_NAME("Voyager"), | |
1464 | .parent = TYPE_MACHINE, | |
1465 | .class_init = voyager_class_init, | |
1466 | }; | |
e264d29d | 1467 | |
8a661aea | 1468 | static void ss_lx_class_init(ObjectClass *oc, void *data) |
e264d29d | 1469 | { |
8a661aea AF |
1470 | MachineClass *mc = MACHINE_CLASS(oc); |
1471 | ||
e264d29d EH |
1472 | mc->desc = "Sun4m platform, SPARCstation LX"; |
1473 | mc->init = ss_lx_init; | |
1474 | mc->block_default_type = IF_SCSI; | |
1475 | mc->default_boot_order = "c"; | |
49cbd887 | 1476 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
e264d29d EH |
1477 | } |
1478 | ||
8a661aea AF |
1479 | static const TypeInfo ss_lx_type = { |
1480 | .name = MACHINE_TYPE_NAME("LX"), | |
1481 | .parent = TYPE_MACHINE, | |
1482 | .class_init = ss_lx_class_init, | |
1483 | }; | |
e264d29d | 1484 | |
8a661aea | 1485 | static void ss4_class_init(ObjectClass *oc, void *data) |
e264d29d | 1486 | { |
8a661aea AF |
1487 | MachineClass *mc = MACHINE_CLASS(oc); |
1488 | ||
e264d29d EH |
1489 | mc->desc = "Sun4m platform, SPARCstation 4"; |
1490 | mc->init = ss4_init; | |
1491 | mc->block_default_type = IF_SCSI; | |
1492 | mc->default_boot_order = "c"; | |
49cbd887 | 1493 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
e264d29d EH |
1494 | } |
1495 | ||
8a661aea AF |
1496 | static const TypeInfo ss4_type = { |
1497 | .name = MACHINE_TYPE_NAME("SS-4"), | |
1498 | .parent = TYPE_MACHINE, | |
1499 | .class_init = ss4_class_init, | |
1500 | }; | |
e264d29d | 1501 | |
8a661aea | 1502 | static void scls_class_init(ObjectClass *oc, void *data) |
e264d29d | 1503 | { |
8a661aea AF |
1504 | MachineClass *mc = MACHINE_CLASS(oc); |
1505 | ||
e264d29d EH |
1506 | mc->desc = "Sun4m platform, SPARCClassic"; |
1507 | mc->init = scls_init; | |
1508 | mc->block_default_type = IF_SCSI; | |
1509 | mc->default_boot_order = "c"; | |
49cbd887 | 1510 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
e264d29d EH |
1511 | } |
1512 | ||
8a661aea AF |
1513 | static const TypeInfo scls_type = { |
1514 | .name = MACHINE_TYPE_NAME("SPARCClassic"), | |
1515 | .parent = TYPE_MACHINE, | |
1516 | .class_init = scls_class_init, | |
1517 | }; | |
e264d29d | 1518 | |
8a661aea | 1519 | static void sbook_class_init(ObjectClass *oc, void *data) |
e264d29d | 1520 | { |
8a661aea AF |
1521 | MachineClass *mc = MACHINE_CLASS(oc); |
1522 | ||
e264d29d EH |
1523 | mc->desc = "Sun4m platform, SPARCbook"; |
1524 | mc->init = sbook_init; | |
1525 | mc->block_default_type = IF_SCSI; | |
1526 | mc->default_boot_order = "c"; | |
49cbd887 | 1527 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
e264d29d EH |
1528 | } |
1529 | ||
8a661aea AF |
1530 | static const TypeInfo sbook_type = { |
1531 | .name = MACHINE_TYPE_NAME("SPARCbook"), | |
1532 | .parent = TYPE_MACHINE, | |
1533 | .class_init = sbook_class_init, | |
1534 | }; | |
a526a31c | 1535 | |
83f7d43a AF |
1536 | static void sun4m_register_types(void) |
1537 | { | |
1538 | type_register_static(&idreg_info); | |
1539 | type_register_static(&afx_info); | |
1540 | type_register_static(&prom_info); | |
1541 | type_register_static(&ram_info); | |
83f7d43a | 1542 | |
8a661aea AF |
1543 | type_register_static(&ss5_type); |
1544 | type_register_static(&ss10_type); | |
1545 | type_register_static(&ss600mp_type); | |
1546 | type_register_static(&ss20_type); | |
1547 | type_register_static(&voyager_type); | |
1548 | type_register_static(&ss_lx_type); | |
1549 | type_register_static(&ss4_type); | |
1550 | type_register_static(&scls_type); | |
1551 | type_register_static(&sbook_type); | |
1552 | } | |
1553 | ||
83f7d43a | 1554 | type_init(sun4m_register_types) |