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[mirror_qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/sysbus.h"
30 #include "qemu/error-report.h"
31 #include "qemu/timer.h"
32 #include "hw/sparc/sun4m_iommu.h"
33 #include "hw/timer/m48t59.h"
34 #include "hw/sparc/sparc32_dma.h"
35 #include "hw/block/fdc.h"
36 #include "sysemu/sysemu.h"
37 #include "net/net.h"
38 #include "hw/boards.h"
39 #include "hw/scsi/esp.h"
40 #include "hw/nvram/sun_nvram.h"
41 #include "hw/nvram/chrp_nvram.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/empty_slot.h"
45 #include "hw/loader.h"
46 #include "elf.h"
47 #include "trace.h"
48
49 /*
50 * Sun4m architecture was used in the following machines:
51 *
52 * SPARCserver 6xxMP/xx
53 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
54 * SPARCclassic X (4/10)
55 * SPARCstation LX/ZX (4/30)
56 * SPARCstation Voyager
57 * SPARCstation 10/xx, SPARCserver 10/xx
58 * SPARCstation 5, SPARCserver 5
59 * SPARCstation 20/xx, SPARCserver 20
60 * SPARCstation 4
61 *
62 * See for example: http://www.sunhelp.org/faq/sunref1.html
63 */
64
65 #define KERNEL_LOAD_ADDR 0x00004000
66 #define CMDLINE_ADDR 0x007ff000
67 #define INITRD_LOAD_ADDR 0x00800000
68 #define PROM_SIZE_MAX (1 * MiB)
69 #define PROM_VADDR 0xffd00000
70 #define PROM_FILENAME "openbios-sparc32"
71 #define CFG_ADDR 0xd00000510ULL
72 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
73 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
74 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
75
76 #define MAX_CPUS 16
77 #define MAX_PILS 16
78 #define MAX_VSIMMS 4
79
80 #define ESCC_CLOCK 4915200
81
82 struct sun4m_hwdef {
83 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
84 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
85 hwaddr serial_base, fd_base;
86 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
87 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
88 hwaddr bpp_base, dbri_base, sx_base;
89 struct {
90 hwaddr reg_base, vram_base;
91 } vsimm[MAX_VSIMMS];
92 hwaddr ecc_base;
93 uint64_t max_mem;
94 uint32_t ecc_version;
95 uint32_t iommu_version;
96 uint16_t machine_id;
97 uint8_t nvram_machine_id;
98 };
99
100 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
101 Error **errp)
102 {
103 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
104 }
105
106 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
107 const char *cmdline, const char *boot_devices,
108 ram_addr_t RAM_size, uint32_t kernel_size,
109 int width, int height, int depth,
110 int nvram_machine_id, const char *arch)
111 {
112 unsigned int i;
113 int sysp_end;
114 uint8_t image[0x1ff0];
115 NvramClass *k = NVRAM_GET_CLASS(nvram);
116
117 memset(image, '\0', sizeof(image));
118
119 /* OpenBIOS nvram variables partition */
120 sysp_end = chrp_nvram_create_system_partition(image, 0);
121
122 /* Free space partition */
123 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
124
125 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
126 nvram_machine_id);
127
128 for (i = 0; i < sizeof(image); i++) {
129 (k->write)(nvram, i, image[i]);
130 }
131 }
132
133 void cpu_check_irqs(CPUSPARCState *env)
134 {
135 CPUState *cs;
136
137 /* We should be holding the BQL before we mess with IRQs */
138 g_assert(qemu_mutex_iothread_locked());
139
140 if (env->pil_in && (env->interrupt_index == 0 ||
141 (env->interrupt_index & ~15) == TT_EXTINT)) {
142 unsigned int i;
143
144 for (i = 15; i > 0; i--) {
145 if (env->pil_in & (1 << i)) {
146 int old_interrupt = env->interrupt_index;
147
148 env->interrupt_index = TT_EXTINT | i;
149 if (old_interrupt != env->interrupt_index) {
150 cs = CPU(sparc_env_get_cpu(env));
151 trace_sun4m_cpu_interrupt(i);
152 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
153 }
154 break;
155 }
156 }
157 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
158 cs = CPU(sparc_env_get_cpu(env));
159 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
160 env->interrupt_index = 0;
161 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
162 }
163 }
164
165 static void cpu_kick_irq(SPARCCPU *cpu)
166 {
167 CPUSPARCState *env = &cpu->env;
168 CPUState *cs = CPU(cpu);
169
170 cs->halted = 0;
171 cpu_check_irqs(env);
172 qemu_cpu_kick(cs);
173 }
174
175 static void cpu_set_irq(void *opaque, int irq, int level)
176 {
177 SPARCCPU *cpu = opaque;
178 CPUSPARCState *env = &cpu->env;
179
180 if (level) {
181 trace_sun4m_cpu_set_irq_raise(irq);
182 env->pil_in |= 1 << irq;
183 cpu_kick_irq(cpu);
184 } else {
185 trace_sun4m_cpu_set_irq_lower(irq);
186 env->pil_in &= ~(1 << irq);
187 cpu_check_irqs(env);
188 }
189 }
190
191 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
192 {
193 }
194
195 static void main_cpu_reset(void *opaque)
196 {
197 SPARCCPU *cpu = opaque;
198 CPUState *cs = CPU(cpu);
199
200 cpu_reset(cs);
201 cs->halted = 0;
202 }
203
204 static void secondary_cpu_reset(void *opaque)
205 {
206 SPARCCPU *cpu = opaque;
207 CPUState *cs = CPU(cpu);
208
209 cpu_reset(cs);
210 cs->halted = 1;
211 }
212
213 static void cpu_halt_signal(void *opaque, int irq, int level)
214 {
215 if (level && current_cpu) {
216 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
217 }
218 }
219
220 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
221 {
222 return addr - 0xf0000000ULL;
223 }
224
225 static unsigned long sun4m_load_kernel(const char *kernel_filename,
226 const char *initrd_filename,
227 ram_addr_t RAM_size)
228 {
229 int linux_boot;
230 unsigned int i;
231 long initrd_size, kernel_size;
232 uint8_t *ptr;
233
234 linux_boot = (kernel_filename != NULL);
235
236 kernel_size = 0;
237 if (linux_boot) {
238 int bswap_needed;
239
240 #ifdef BSWAP_NEEDED
241 bswap_needed = 1;
242 #else
243 bswap_needed = 0;
244 #endif
245 kernel_size = load_elf(kernel_filename, NULL,
246 translate_kernel_address, NULL,
247 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
248 if (kernel_size < 0)
249 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
250 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
251 TARGET_PAGE_SIZE);
252 if (kernel_size < 0)
253 kernel_size = load_image_targphys(kernel_filename,
254 KERNEL_LOAD_ADDR,
255 RAM_size - KERNEL_LOAD_ADDR);
256 if (kernel_size < 0) {
257 error_report("could not load kernel '%s'", kernel_filename);
258 exit(1);
259 }
260
261 /* load initrd */
262 initrd_size = 0;
263 if (initrd_filename) {
264 initrd_size = load_image_targphys(initrd_filename,
265 INITRD_LOAD_ADDR,
266 RAM_size - INITRD_LOAD_ADDR);
267 if (initrd_size < 0) {
268 error_report("could not load initial ram disk '%s'",
269 initrd_filename);
270 exit(1);
271 }
272 }
273 if (initrd_size > 0) {
274 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
275 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
276 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
277 stl_p(ptr + 16, INITRD_LOAD_ADDR);
278 stl_p(ptr + 20, initrd_size);
279 break;
280 }
281 }
282 }
283 }
284 return kernel_size;
285 }
286
287 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
288 {
289 DeviceState *dev;
290 SysBusDevice *s;
291
292 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
293 qdev_prop_set_uint32(dev, "version", version);
294 qdev_init_nofail(dev);
295 s = SYS_BUS_DEVICE(dev);
296 sysbus_connect_irq(s, 0, irq);
297 sysbus_mmio_map(s, 0, addr);
298
299 return s;
300 }
301
302 static void *sparc32_dma_init(hwaddr dma_base,
303 hwaddr esp_base, qemu_irq espdma_irq,
304 hwaddr le_base, qemu_irq ledma_irq)
305 {
306 DeviceState *dma;
307 ESPDMADeviceState *espdma;
308 LEDMADeviceState *ledma;
309 SysBusESPState *esp;
310 SysBusPCNetState *lance;
311
312 dma = qdev_create(NULL, TYPE_SPARC32_DMA);
313 qdev_init_nofail(dma);
314 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
315
316 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
317 OBJECT(dma), "espdma"));
318 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
319
320 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
321 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
322 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
323
324 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
325 OBJECT(dma), "ledma"));
326 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
327
328 lance = SYSBUS_PCNET(object_resolve_path_component(
329 OBJECT(ledma), "lance"));
330 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
331
332 return dma;
333 }
334
335 static DeviceState *slavio_intctl_init(hwaddr addr,
336 hwaddr addrg,
337 qemu_irq **parent_irq)
338 {
339 DeviceState *dev;
340 SysBusDevice *s;
341 unsigned int i, j;
342
343 dev = qdev_create(NULL, "slavio_intctl");
344 qdev_init_nofail(dev);
345
346 s = SYS_BUS_DEVICE(dev);
347
348 for (i = 0; i < MAX_CPUS; i++) {
349 for (j = 0; j < MAX_PILS; j++) {
350 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
351 }
352 }
353 sysbus_mmio_map(s, 0, addrg);
354 for (i = 0; i < MAX_CPUS; i++) {
355 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
356 }
357
358 return dev;
359 }
360
361 #define SYS_TIMER_OFFSET 0x10000ULL
362 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
363
364 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
365 qemu_irq *cpu_irqs, unsigned int num_cpus)
366 {
367 DeviceState *dev;
368 SysBusDevice *s;
369 unsigned int i;
370
371 dev = qdev_create(NULL, "slavio_timer");
372 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
373 qdev_init_nofail(dev);
374 s = SYS_BUS_DEVICE(dev);
375 sysbus_connect_irq(s, 0, master_irq);
376 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
377
378 for (i = 0; i < MAX_CPUS; i++) {
379 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
380 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
381 }
382 }
383
384 static qemu_irq slavio_system_powerdown;
385
386 static void slavio_powerdown_req(Notifier *n, void *opaque)
387 {
388 qemu_irq_raise(slavio_system_powerdown);
389 }
390
391 static Notifier slavio_system_powerdown_notifier = {
392 .notify = slavio_powerdown_req
393 };
394
395 #define MISC_LEDS 0x01600000
396 #define MISC_CFG 0x01800000
397 #define MISC_DIAG 0x01a00000
398 #define MISC_MDM 0x01b00000
399 #define MISC_SYS 0x01f00000
400
401 static void slavio_misc_init(hwaddr base,
402 hwaddr aux1_base,
403 hwaddr aux2_base, qemu_irq irq,
404 qemu_irq fdc_tc)
405 {
406 DeviceState *dev;
407 SysBusDevice *s;
408
409 dev = qdev_create(NULL, "slavio_misc");
410 qdev_init_nofail(dev);
411 s = SYS_BUS_DEVICE(dev);
412 if (base) {
413 /* 8 bit registers */
414 /* Slavio control */
415 sysbus_mmio_map(s, 0, base + MISC_CFG);
416 /* Diagnostics */
417 sysbus_mmio_map(s, 1, base + MISC_DIAG);
418 /* Modem control */
419 sysbus_mmio_map(s, 2, base + MISC_MDM);
420 /* 16 bit registers */
421 /* ss600mp diag LEDs */
422 sysbus_mmio_map(s, 3, base + MISC_LEDS);
423 /* 32 bit registers */
424 /* System control */
425 sysbus_mmio_map(s, 4, base + MISC_SYS);
426 }
427 if (aux1_base) {
428 /* AUX 1 (Misc System Functions) */
429 sysbus_mmio_map(s, 5, aux1_base);
430 }
431 if (aux2_base) {
432 /* AUX 2 (Software Powerdown Control) */
433 sysbus_mmio_map(s, 6, aux2_base);
434 }
435 sysbus_connect_irq(s, 0, irq);
436 sysbus_connect_irq(s, 1, fdc_tc);
437 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
438 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
439 }
440
441 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
442 {
443 DeviceState *dev;
444 SysBusDevice *s;
445
446 dev = qdev_create(NULL, "eccmemctl");
447 qdev_prop_set_uint32(dev, "version", version);
448 qdev_init_nofail(dev);
449 s = SYS_BUS_DEVICE(dev);
450 sysbus_connect_irq(s, 0, irq);
451 sysbus_mmio_map(s, 0, base);
452 if (version == 0) { // SS-600MP only
453 sysbus_mmio_map(s, 1, base + 0x1000);
454 }
455 }
456
457 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
458 {
459 DeviceState *dev;
460 SysBusDevice *s;
461
462 dev = qdev_create(NULL, "apc");
463 qdev_init_nofail(dev);
464 s = SYS_BUS_DEVICE(dev);
465 /* Power management (APC) XXX: not a Slavio device */
466 sysbus_mmio_map(s, 0, power_base);
467 sysbus_connect_irq(s, 0, cpu_halt);
468 }
469
470 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
471 int height, int depth)
472 {
473 DeviceState *dev;
474 SysBusDevice *s;
475
476 dev = qdev_create(NULL, "SUNW,tcx");
477 qdev_prop_set_uint32(dev, "vram_size", vram_size);
478 qdev_prop_set_uint16(dev, "width", width);
479 qdev_prop_set_uint16(dev, "height", height);
480 qdev_prop_set_uint16(dev, "depth", depth);
481 qdev_init_nofail(dev);
482 s = SYS_BUS_DEVICE(dev);
483
484 /* 10/ROM : FCode ROM */
485 sysbus_mmio_map(s, 0, addr);
486 /* 2/STIP : Stipple */
487 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
488 /* 3/BLIT : Blitter */
489 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
490 /* 5/RSTIP : Raw Stipple */
491 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
492 /* 6/RBLIT : Raw Blitter */
493 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
494 /* 7/TEC : Transform Engine */
495 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
496 /* 8/CMAP : DAC */
497 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
498 /* 9/THC : */
499 if (depth == 8) {
500 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
501 } else {
502 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
503 }
504 /* 11/DHC : */
505 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
506 /* 12/ALT : */
507 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
508 /* 0/DFB8 : 8-bit plane */
509 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
510 /* 1/DFB24 : 24bit plane */
511 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
512 /* 4/RDFB32: Raw framebuffer. Control plane */
513 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
514 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
515 if (depth == 8) {
516 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
517 }
518
519 sysbus_connect_irq(s, 0, irq);
520 }
521
522 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
523 int height, int depth)
524 {
525 DeviceState *dev;
526 SysBusDevice *s;
527
528 dev = qdev_create(NULL, "cgthree");
529 qdev_prop_set_uint32(dev, "vram-size", vram_size);
530 qdev_prop_set_uint16(dev, "width", width);
531 qdev_prop_set_uint16(dev, "height", height);
532 qdev_prop_set_uint16(dev, "depth", depth);
533 qdev_init_nofail(dev);
534 s = SYS_BUS_DEVICE(dev);
535
536 /* FCode ROM */
537 sysbus_mmio_map(s, 0, addr);
538 /* DAC */
539 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
540 /* 8-bit plane */
541 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
542
543 sysbus_connect_irq(s, 0, irq);
544 }
545
546 /* NCR89C100/MACIO Internal ID register */
547
548 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
549
550 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
551
552 static void idreg_init(hwaddr addr)
553 {
554 DeviceState *dev;
555 SysBusDevice *s;
556
557 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
558 qdev_init_nofail(dev);
559 s = SYS_BUS_DEVICE(dev);
560
561 sysbus_mmio_map(s, 0, addr);
562 address_space_write_rom(&address_space_memory, addr,
563 MEMTXATTRS_UNSPECIFIED,
564 idreg_data, sizeof(idreg_data));
565 }
566
567 #define MACIO_ID_REGISTER(obj) \
568 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
569
570 typedef struct IDRegState {
571 SysBusDevice parent_obj;
572
573 MemoryRegion mem;
574 } IDRegState;
575
576 static void idreg_realize(DeviceState *ds, Error **errp)
577 {
578 IDRegState *s = MACIO_ID_REGISTER(ds);
579 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
580 Error *local_err = NULL;
581
582 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
583 sizeof(idreg_data), &local_err);
584 if (local_err) {
585 error_propagate(errp, local_err);
586 return;
587 }
588
589 vmstate_register_ram_global(&s->mem);
590 memory_region_set_readonly(&s->mem, true);
591 sysbus_init_mmio(dev, &s->mem);
592 }
593
594 static void idreg_class_init(ObjectClass *oc, void *data)
595 {
596 DeviceClass *dc = DEVICE_CLASS(oc);
597
598 dc->realize = idreg_realize;
599 }
600
601 static const TypeInfo idreg_info = {
602 .name = TYPE_MACIO_ID_REGISTER,
603 .parent = TYPE_SYS_BUS_DEVICE,
604 .instance_size = sizeof(IDRegState),
605 .class_init = idreg_class_init,
606 };
607
608 #define TYPE_TCX_AFX "tcx_afx"
609 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
610
611 typedef struct AFXState {
612 SysBusDevice parent_obj;
613
614 MemoryRegion mem;
615 } AFXState;
616
617 /* SS-5 TCX AFX register */
618 static void afx_init(hwaddr addr)
619 {
620 DeviceState *dev;
621 SysBusDevice *s;
622
623 dev = qdev_create(NULL, TYPE_TCX_AFX);
624 qdev_init_nofail(dev);
625 s = SYS_BUS_DEVICE(dev);
626
627 sysbus_mmio_map(s, 0, addr);
628 }
629
630 static void afx_realize(DeviceState *ds, Error **errp)
631 {
632 AFXState *s = TCX_AFX(ds);
633 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
634 Error *local_err = NULL;
635
636 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
637 &local_err);
638 if (local_err) {
639 error_propagate(errp, local_err);
640 return;
641 }
642
643 vmstate_register_ram_global(&s->mem);
644 sysbus_init_mmio(dev, &s->mem);
645 }
646
647 static void afx_class_init(ObjectClass *oc, void *data)
648 {
649 DeviceClass *dc = DEVICE_CLASS(oc);
650
651 dc->realize = afx_realize;
652 }
653
654 static const TypeInfo afx_info = {
655 .name = TYPE_TCX_AFX,
656 .parent = TYPE_SYS_BUS_DEVICE,
657 .instance_size = sizeof(AFXState),
658 .class_init = afx_class_init,
659 };
660
661 #define TYPE_OPENPROM "openprom"
662 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
663
664 typedef struct PROMState {
665 SysBusDevice parent_obj;
666
667 MemoryRegion prom;
668 } PROMState;
669
670 /* Boot PROM (OpenBIOS) */
671 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
672 {
673 hwaddr *base_addr = (hwaddr *)opaque;
674 return addr + *base_addr - PROM_VADDR;
675 }
676
677 static void prom_init(hwaddr addr, const char *bios_name)
678 {
679 DeviceState *dev;
680 SysBusDevice *s;
681 char *filename;
682 int ret;
683
684 dev = qdev_create(NULL, TYPE_OPENPROM);
685 qdev_init_nofail(dev);
686 s = SYS_BUS_DEVICE(dev);
687
688 sysbus_mmio_map(s, 0, addr);
689
690 /* load boot prom */
691 if (bios_name == NULL) {
692 bios_name = PROM_FILENAME;
693 }
694 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
695 if (filename) {
696 ret = load_elf(filename, NULL,
697 translate_prom_address, &addr, NULL,
698 NULL, NULL, 1, EM_SPARC, 0, 0);
699 if (ret < 0 || ret > PROM_SIZE_MAX) {
700 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
701 }
702 g_free(filename);
703 } else {
704 ret = -1;
705 }
706 if (ret < 0 || ret > PROM_SIZE_MAX) {
707 error_report("could not load prom '%s'", bios_name);
708 exit(1);
709 }
710 }
711
712 static void prom_realize(DeviceState *ds, Error **errp)
713 {
714 PROMState *s = OPENPROM(ds);
715 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
716 Error *local_err = NULL;
717
718 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
719 PROM_SIZE_MAX, &local_err);
720 if (local_err) {
721 error_propagate(errp, local_err);
722 return;
723 }
724
725 vmstate_register_ram_global(&s->prom);
726 memory_region_set_readonly(&s->prom, true);
727 sysbus_init_mmio(dev, &s->prom);
728 }
729
730 static Property prom_properties[] = {
731 {/* end of property list */},
732 };
733
734 static void prom_class_init(ObjectClass *klass, void *data)
735 {
736 DeviceClass *dc = DEVICE_CLASS(klass);
737
738 dc->props = prom_properties;
739 dc->realize = prom_realize;
740 }
741
742 static const TypeInfo prom_info = {
743 .name = TYPE_OPENPROM,
744 .parent = TYPE_SYS_BUS_DEVICE,
745 .instance_size = sizeof(PROMState),
746 .class_init = prom_class_init,
747 };
748
749 #define TYPE_SUN4M_MEMORY "memory"
750 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
751
752 typedef struct RamDevice {
753 SysBusDevice parent_obj;
754
755 MemoryRegion ram;
756 uint64_t size;
757 } RamDevice;
758
759 /* System RAM */
760 static void ram_realize(DeviceState *dev, Error **errp)
761 {
762 RamDevice *d = SUN4M_RAM(dev);
763 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
764
765 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
766 d->size);
767 sysbus_init_mmio(sbd, &d->ram);
768 }
769
770 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
771 uint64_t max_mem)
772 {
773 DeviceState *dev;
774 SysBusDevice *s;
775 RamDevice *d;
776
777 /* allocate RAM */
778 if ((uint64_t)RAM_size > max_mem) {
779 error_report("Too much memory for this machine: %" PRId64 ","
780 " maximum %" PRId64,
781 RAM_size / MiB, max_mem / MiB);
782 exit(1);
783 }
784 dev = qdev_create(NULL, "memory");
785 s = SYS_BUS_DEVICE(dev);
786
787 d = SUN4M_RAM(dev);
788 d->size = RAM_size;
789 qdev_init_nofail(dev);
790
791 sysbus_mmio_map(s, 0, addr);
792 }
793
794 static Property ram_properties[] = {
795 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
796 DEFINE_PROP_END_OF_LIST(),
797 };
798
799 static void ram_class_init(ObjectClass *klass, void *data)
800 {
801 DeviceClass *dc = DEVICE_CLASS(klass);
802
803 dc->realize = ram_realize;
804 dc->props = ram_properties;
805 }
806
807 static const TypeInfo ram_info = {
808 .name = TYPE_SUN4M_MEMORY,
809 .parent = TYPE_SYS_BUS_DEVICE,
810 .instance_size = sizeof(RamDevice),
811 .class_init = ram_class_init,
812 };
813
814 static void cpu_devinit(const char *cpu_type, unsigned int id,
815 uint64_t prom_addr, qemu_irq **cpu_irqs)
816 {
817 CPUState *cs;
818 SPARCCPU *cpu;
819 CPUSPARCState *env;
820
821 cpu = SPARC_CPU(cpu_create(cpu_type));
822 env = &cpu->env;
823
824 cpu_sparc_set_id(env, id);
825 if (id == 0) {
826 qemu_register_reset(main_cpu_reset, cpu);
827 } else {
828 qemu_register_reset(secondary_cpu_reset, cpu);
829 cs = CPU(cpu);
830 cs->halted = 1;
831 }
832 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
833 env->prom_addr = prom_addr;
834 }
835
836 static void dummy_fdc_tc(void *opaque, int irq, int level)
837 {
838 }
839
840 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
841 MachineState *machine)
842 {
843 DeviceState *slavio_intctl;
844 unsigned int i;
845 void *nvram;
846 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
847 qemu_irq fdc_tc;
848 unsigned long kernel_size;
849 DriveInfo *fd[MAX_FD];
850 FWCfgState *fw_cfg;
851 unsigned int num_vsimms;
852 DeviceState *dev;
853 SysBusDevice *s;
854
855 /* init CPUs */
856 for(i = 0; i < smp_cpus; i++) {
857 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
858 }
859
860 for (i = smp_cpus; i < MAX_CPUS; i++)
861 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
862
863
864 /* set up devices */
865 ram_init(0, machine->ram_size, hwdef->max_mem);
866 /* models without ECC don't trap when missing ram is accessed */
867 if (!hwdef->ecc_base) {
868 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
869 }
870
871 prom_init(hwdef->slavio_base, bios_name);
872
873 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
874 hwdef->intctl_base + 0x10000ULL,
875 cpu_irqs);
876
877 for (i = 0; i < 32; i++) {
878 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
879 }
880 for (i = 0; i < MAX_CPUS; i++) {
881 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
882 }
883
884 if (hwdef->idreg_base) {
885 idreg_init(hwdef->idreg_base);
886 }
887
888 if (hwdef->afx_base) {
889 afx_init(hwdef->afx_base);
890 }
891
892 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
893
894 if (hwdef->iommu_pad_base) {
895 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
896 Software shouldn't use aliased addresses, neither should it crash
897 when does. Using empty_slot instead of aliasing can help with
898 debugging such accesses */
899 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
900 }
901
902 sparc32_dma_init(hwdef->dma_base,
903 hwdef->esp_base, slavio_irq[18],
904 hwdef->le_base, slavio_irq[16]);
905
906 if (graphic_depth != 8 && graphic_depth != 24) {
907 error_report("Unsupported depth: %d", graphic_depth);
908 exit (1);
909 }
910 num_vsimms = 0;
911 if (num_vsimms == 0) {
912 if (vga_interface_type == VGA_CG3) {
913 if (graphic_depth != 8) {
914 error_report("Unsupported depth: %d", graphic_depth);
915 exit(1);
916 }
917
918 if (!(graphic_width == 1024 && graphic_height == 768) &&
919 !(graphic_width == 1152 && graphic_height == 900)) {
920 error_report("Unsupported resolution: %d x %d", graphic_width,
921 graphic_height);
922 exit(1);
923 }
924
925 /* sbus irq 5 */
926 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
927 graphic_width, graphic_height, graphic_depth);
928 } else {
929 /* If no display specified, default to TCX */
930 if (graphic_depth != 8 && graphic_depth != 24) {
931 error_report("Unsupported depth: %d", graphic_depth);
932 exit(1);
933 }
934
935 if (!(graphic_width == 1024 && graphic_height == 768)) {
936 error_report("Unsupported resolution: %d x %d",
937 graphic_width, graphic_height);
938 exit(1);
939 }
940
941 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
942 graphic_width, graphic_height, graphic_depth);
943 }
944 }
945
946 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
947 /* vsimm registers probed by OBP */
948 if (hwdef->vsimm[i].reg_base) {
949 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
950 }
951 }
952
953 if (hwdef->sx_base) {
954 empty_slot_init(hwdef->sx_base, 0x2000);
955 }
956
957 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
958
959 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
960
961 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
962 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
963 dev = qdev_create(NULL, TYPE_ESCC);
964 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
965 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
966 qdev_prop_set_uint32(dev, "it_shift", 1);
967 qdev_prop_set_chr(dev, "chrB", NULL);
968 qdev_prop_set_chr(dev, "chrA", NULL);
969 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
970 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
971 qdev_init_nofail(dev);
972 s = SYS_BUS_DEVICE(dev);
973 sysbus_connect_irq(s, 0, slavio_irq[14]);
974 sysbus_connect_irq(s, 1, slavio_irq[14]);
975 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
976
977 dev = qdev_create(NULL, TYPE_ESCC);
978 qdev_prop_set_uint32(dev, "disabled", 0);
979 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
980 qdev_prop_set_uint32(dev, "it_shift", 1);
981 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
982 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
983 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
984 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
985 qdev_init_nofail(dev);
986
987 s = SYS_BUS_DEVICE(dev);
988 sysbus_connect_irq(s, 0, slavio_irq[15]);
989 sysbus_connect_irq(s, 1, slavio_irq[15]);
990 sysbus_mmio_map(s, 0, hwdef->serial_base);
991
992 if (hwdef->apc_base) {
993 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
994 }
995
996 if (hwdef->fd_base) {
997 /* there is zero or one floppy drive */
998 memset(fd, 0, sizeof(fd));
999 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1000 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1001 &fdc_tc);
1002 } else {
1003 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1004 }
1005
1006 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1007 slavio_irq[30], fdc_tc);
1008
1009 if (hwdef->cs_base) {
1010 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1011 slavio_irq[5]);
1012 }
1013
1014 if (hwdef->dbri_base) {
1015 /* ISDN chip with attached CS4215 audio codec */
1016 /* prom space */
1017 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1018 /* reg space */
1019 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1020 }
1021
1022 if (hwdef->bpp_base) {
1023 /* parallel port */
1024 empty_slot_init(hwdef->bpp_base, 0x20);
1025 }
1026
1027 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1028 machine->initrd_filename,
1029 machine->ram_size);
1030
1031 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1032 machine->boot_order, machine->ram_size, kernel_size,
1033 graphic_width, graphic_height, graphic_depth,
1034 hwdef->nvram_machine_id, "Sun4m");
1035
1036 if (hwdef->ecc_base)
1037 ecc_init(hwdef->ecc_base, slavio_irq[28],
1038 hwdef->ecc_version);
1039
1040 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
1041 fw_cfg = FW_CFG(dev);
1042 qdev_prop_set_uint32(dev, "data_width", 1);
1043 qdev_prop_set_bit(dev, "dma_enabled", false);
1044 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1045 OBJECT(fw_cfg), NULL);
1046 qdev_init_nofail(dev);
1047 s = SYS_BUS_DEVICE(dev);
1048 sysbus_mmio_map(s, 0, CFG_ADDR);
1049 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1050
1051 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1052 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1053 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1054 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1055 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1056 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1057 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1058 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1059 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1060 if (machine->kernel_cmdline) {
1061 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1062 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1063 machine->kernel_cmdline);
1064 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1065 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1066 strlen(machine->kernel_cmdline) + 1);
1067 } else {
1068 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1069 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1070 }
1071 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1072 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1073 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1074 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1075 }
1076
1077 enum {
1078 ss5_id = 32,
1079 vger_id,
1080 lx_id,
1081 ss4_id,
1082 scls_id,
1083 sbook_id,
1084 ss10_id = 64,
1085 ss20_id,
1086 ss600mp_id,
1087 };
1088
1089 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1090 /* SS-5 */
1091 {
1092 .iommu_base = 0x10000000,
1093 .iommu_pad_base = 0x10004000,
1094 .iommu_pad_len = 0x0fffb000,
1095 .tcx_base = 0x50000000,
1096 .cs_base = 0x6c000000,
1097 .slavio_base = 0x70000000,
1098 .ms_kb_base = 0x71000000,
1099 .serial_base = 0x71100000,
1100 .nvram_base = 0x71200000,
1101 .fd_base = 0x71400000,
1102 .counter_base = 0x71d00000,
1103 .intctl_base = 0x71e00000,
1104 .idreg_base = 0x78000000,
1105 .dma_base = 0x78400000,
1106 .esp_base = 0x78800000,
1107 .le_base = 0x78c00000,
1108 .apc_base = 0x6a000000,
1109 .afx_base = 0x6e000000,
1110 .aux1_base = 0x71900000,
1111 .aux2_base = 0x71910000,
1112 .nvram_machine_id = 0x80,
1113 .machine_id = ss5_id,
1114 .iommu_version = 0x05000000,
1115 .max_mem = 0x10000000,
1116 },
1117 /* SS-10 */
1118 {
1119 .iommu_base = 0xfe0000000ULL,
1120 .tcx_base = 0xe20000000ULL,
1121 .slavio_base = 0xff0000000ULL,
1122 .ms_kb_base = 0xff1000000ULL,
1123 .serial_base = 0xff1100000ULL,
1124 .nvram_base = 0xff1200000ULL,
1125 .fd_base = 0xff1700000ULL,
1126 .counter_base = 0xff1300000ULL,
1127 .intctl_base = 0xff1400000ULL,
1128 .idreg_base = 0xef0000000ULL,
1129 .dma_base = 0xef0400000ULL,
1130 .esp_base = 0xef0800000ULL,
1131 .le_base = 0xef0c00000ULL,
1132 .apc_base = 0xefa000000ULL, // XXX should not exist
1133 .aux1_base = 0xff1800000ULL,
1134 .aux2_base = 0xff1a01000ULL,
1135 .ecc_base = 0xf00000000ULL,
1136 .ecc_version = 0x10000000, // version 0, implementation 1
1137 .nvram_machine_id = 0x72,
1138 .machine_id = ss10_id,
1139 .iommu_version = 0x03000000,
1140 .max_mem = 0xf00000000ULL,
1141 },
1142 /* SS-600MP */
1143 {
1144 .iommu_base = 0xfe0000000ULL,
1145 .tcx_base = 0xe20000000ULL,
1146 .slavio_base = 0xff0000000ULL,
1147 .ms_kb_base = 0xff1000000ULL,
1148 .serial_base = 0xff1100000ULL,
1149 .nvram_base = 0xff1200000ULL,
1150 .counter_base = 0xff1300000ULL,
1151 .intctl_base = 0xff1400000ULL,
1152 .dma_base = 0xef0081000ULL,
1153 .esp_base = 0xef0080000ULL,
1154 .le_base = 0xef0060000ULL,
1155 .apc_base = 0xefa000000ULL, // XXX should not exist
1156 .aux1_base = 0xff1800000ULL,
1157 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1158 .ecc_base = 0xf00000000ULL,
1159 .ecc_version = 0x00000000, // version 0, implementation 0
1160 .nvram_machine_id = 0x71,
1161 .machine_id = ss600mp_id,
1162 .iommu_version = 0x01000000,
1163 .max_mem = 0xf00000000ULL,
1164 },
1165 /* SS-20 */
1166 {
1167 .iommu_base = 0xfe0000000ULL,
1168 .tcx_base = 0xe20000000ULL,
1169 .slavio_base = 0xff0000000ULL,
1170 .ms_kb_base = 0xff1000000ULL,
1171 .serial_base = 0xff1100000ULL,
1172 .nvram_base = 0xff1200000ULL,
1173 .fd_base = 0xff1700000ULL,
1174 .counter_base = 0xff1300000ULL,
1175 .intctl_base = 0xff1400000ULL,
1176 .idreg_base = 0xef0000000ULL,
1177 .dma_base = 0xef0400000ULL,
1178 .esp_base = 0xef0800000ULL,
1179 .le_base = 0xef0c00000ULL,
1180 .bpp_base = 0xef4800000ULL,
1181 .apc_base = 0xefa000000ULL, // XXX should not exist
1182 .aux1_base = 0xff1800000ULL,
1183 .aux2_base = 0xff1a01000ULL,
1184 .dbri_base = 0xee0000000ULL,
1185 .sx_base = 0xf80000000ULL,
1186 .vsimm = {
1187 {
1188 .reg_base = 0x9c000000ULL,
1189 .vram_base = 0xfc000000ULL
1190 }, {
1191 .reg_base = 0x90000000ULL,
1192 .vram_base = 0xf0000000ULL
1193 }, {
1194 .reg_base = 0x94000000ULL
1195 }, {
1196 .reg_base = 0x98000000ULL
1197 }
1198 },
1199 .ecc_base = 0xf00000000ULL,
1200 .ecc_version = 0x20000000, // version 0, implementation 2
1201 .nvram_machine_id = 0x72,
1202 .machine_id = ss20_id,
1203 .iommu_version = 0x13000000,
1204 .max_mem = 0xf00000000ULL,
1205 },
1206 /* Voyager */
1207 {
1208 .iommu_base = 0x10000000,
1209 .tcx_base = 0x50000000,
1210 .slavio_base = 0x70000000,
1211 .ms_kb_base = 0x71000000,
1212 .serial_base = 0x71100000,
1213 .nvram_base = 0x71200000,
1214 .fd_base = 0x71400000,
1215 .counter_base = 0x71d00000,
1216 .intctl_base = 0x71e00000,
1217 .idreg_base = 0x78000000,
1218 .dma_base = 0x78400000,
1219 .esp_base = 0x78800000,
1220 .le_base = 0x78c00000,
1221 .apc_base = 0x71300000, // pmc
1222 .aux1_base = 0x71900000,
1223 .aux2_base = 0x71910000,
1224 .nvram_machine_id = 0x80,
1225 .machine_id = vger_id,
1226 .iommu_version = 0x05000000,
1227 .max_mem = 0x10000000,
1228 },
1229 /* LX */
1230 {
1231 .iommu_base = 0x10000000,
1232 .iommu_pad_base = 0x10004000,
1233 .iommu_pad_len = 0x0fffb000,
1234 .tcx_base = 0x50000000,
1235 .slavio_base = 0x70000000,
1236 .ms_kb_base = 0x71000000,
1237 .serial_base = 0x71100000,
1238 .nvram_base = 0x71200000,
1239 .fd_base = 0x71400000,
1240 .counter_base = 0x71d00000,
1241 .intctl_base = 0x71e00000,
1242 .idreg_base = 0x78000000,
1243 .dma_base = 0x78400000,
1244 .esp_base = 0x78800000,
1245 .le_base = 0x78c00000,
1246 .aux1_base = 0x71900000,
1247 .aux2_base = 0x71910000,
1248 .nvram_machine_id = 0x80,
1249 .machine_id = lx_id,
1250 .iommu_version = 0x04000000,
1251 .max_mem = 0x10000000,
1252 },
1253 /* SS-4 */
1254 {
1255 .iommu_base = 0x10000000,
1256 .tcx_base = 0x50000000,
1257 .cs_base = 0x6c000000,
1258 .slavio_base = 0x70000000,
1259 .ms_kb_base = 0x71000000,
1260 .serial_base = 0x71100000,
1261 .nvram_base = 0x71200000,
1262 .fd_base = 0x71400000,
1263 .counter_base = 0x71d00000,
1264 .intctl_base = 0x71e00000,
1265 .idreg_base = 0x78000000,
1266 .dma_base = 0x78400000,
1267 .esp_base = 0x78800000,
1268 .le_base = 0x78c00000,
1269 .apc_base = 0x6a000000,
1270 .aux1_base = 0x71900000,
1271 .aux2_base = 0x71910000,
1272 .nvram_machine_id = 0x80,
1273 .machine_id = ss4_id,
1274 .iommu_version = 0x05000000,
1275 .max_mem = 0x10000000,
1276 },
1277 /* SPARCClassic */
1278 {
1279 .iommu_base = 0x10000000,
1280 .tcx_base = 0x50000000,
1281 .slavio_base = 0x70000000,
1282 .ms_kb_base = 0x71000000,
1283 .serial_base = 0x71100000,
1284 .nvram_base = 0x71200000,
1285 .fd_base = 0x71400000,
1286 .counter_base = 0x71d00000,
1287 .intctl_base = 0x71e00000,
1288 .idreg_base = 0x78000000,
1289 .dma_base = 0x78400000,
1290 .esp_base = 0x78800000,
1291 .le_base = 0x78c00000,
1292 .apc_base = 0x6a000000,
1293 .aux1_base = 0x71900000,
1294 .aux2_base = 0x71910000,
1295 .nvram_machine_id = 0x80,
1296 .machine_id = scls_id,
1297 .iommu_version = 0x05000000,
1298 .max_mem = 0x10000000,
1299 },
1300 /* SPARCbook */
1301 {
1302 .iommu_base = 0x10000000,
1303 .tcx_base = 0x50000000, // XXX
1304 .slavio_base = 0x70000000,
1305 .ms_kb_base = 0x71000000,
1306 .serial_base = 0x71100000,
1307 .nvram_base = 0x71200000,
1308 .fd_base = 0x71400000,
1309 .counter_base = 0x71d00000,
1310 .intctl_base = 0x71e00000,
1311 .idreg_base = 0x78000000,
1312 .dma_base = 0x78400000,
1313 .esp_base = 0x78800000,
1314 .le_base = 0x78c00000,
1315 .apc_base = 0x6a000000,
1316 .aux1_base = 0x71900000,
1317 .aux2_base = 0x71910000,
1318 .nvram_machine_id = 0x80,
1319 .machine_id = sbook_id,
1320 .iommu_version = 0x05000000,
1321 .max_mem = 0x10000000,
1322 },
1323 };
1324
1325 /* SPARCstation 5 hardware initialisation */
1326 static void ss5_init(MachineState *machine)
1327 {
1328 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1329 }
1330
1331 /* SPARCstation 10 hardware initialisation */
1332 static void ss10_init(MachineState *machine)
1333 {
1334 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1335 }
1336
1337 /* SPARCserver 600MP hardware initialisation */
1338 static void ss600mp_init(MachineState *machine)
1339 {
1340 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1341 }
1342
1343 /* SPARCstation 20 hardware initialisation */
1344 static void ss20_init(MachineState *machine)
1345 {
1346 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1347 }
1348
1349 /* SPARCstation Voyager hardware initialisation */
1350 static void vger_init(MachineState *machine)
1351 {
1352 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1353 }
1354
1355 /* SPARCstation LX hardware initialisation */
1356 static void ss_lx_init(MachineState *machine)
1357 {
1358 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1359 }
1360
1361 /* SPARCstation 4 hardware initialisation */
1362 static void ss4_init(MachineState *machine)
1363 {
1364 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1365 }
1366
1367 /* SPARCClassic hardware initialisation */
1368 static void scls_init(MachineState *machine)
1369 {
1370 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1371 }
1372
1373 /* SPARCbook hardware initialisation */
1374 static void sbook_init(MachineState *machine)
1375 {
1376 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1377 }
1378
1379 static void ss5_class_init(ObjectClass *oc, void *data)
1380 {
1381 MachineClass *mc = MACHINE_CLASS(oc);
1382
1383 mc->desc = "Sun4m platform, SPARCstation 5";
1384 mc->init = ss5_init;
1385 mc->block_default_type = IF_SCSI;
1386 mc->is_default = 1;
1387 mc->default_boot_order = "c";
1388 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1389 }
1390
1391 static const TypeInfo ss5_type = {
1392 .name = MACHINE_TYPE_NAME("SS-5"),
1393 .parent = TYPE_MACHINE,
1394 .class_init = ss5_class_init,
1395 };
1396
1397 static void ss10_class_init(ObjectClass *oc, void *data)
1398 {
1399 MachineClass *mc = MACHINE_CLASS(oc);
1400
1401 mc->desc = "Sun4m platform, SPARCstation 10";
1402 mc->init = ss10_init;
1403 mc->block_default_type = IF_SCSI;
1404 mc->max_cpus = 4;
1405 mc->default_boot_order = "c";
1406 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1407 }
1408
1409 static const TypeInfo ss10_type = {
1410 .name = MACHINE_TYPE_NAME("SS-10"),
1411 .parent = TYPE_MACHINE,
1412 .class_init = ss10_class_init,
1413 };
1414
1415 static void ss600mp_class_init(ObjectClass *oc, void *data)
1416 {
1417 MachineClass *mc = MACHINE_CLASS(oc);
1418
1419 mc->desc = "Sun4m platform, SPARCserver 600MP";
1420 mc->init = ss600mp_init;
1421 mc->block_default_type = IF_SCSI;
1422 mc->max_cpus = 4;
1423 mc->default_boot_order = "c";
1424 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1425 }
1426
1427 static const TypeInfo ss600mp_type = {
1428 .name = MACHINE_TYPE_NAME("SS-600MP"),
1429 .parent = TYPE_MACHINE,
1430 .class_init = ss600mp_class_init,
1431 };
1432
1433 static void ss20_class_init(ObjectClass *oc, void *data)
1434 {
1435 MachineClass *mc = MACHINE_CLASS(oc);
1436
1437 mc->desc = "Sun4m platform, SPARCstation 20";
1438 mc->init = ss20_init;
1439 mc->block_default_type = IF_SCSI;
1440 mc->max_cpus = 4;
1441 mc->default_boot_order = "c";
1442 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1443 }
1444
1445 static const TypeInfo ss20_type = {
1446 .name = MACHINE_TYPE_NAME("SS-20"),
1447 .parent = TYPE_MACHINE,
1448 .class_init = ss20_class_init,
1449 };
1450
1451 static void voyager_class_init(ObjectClass *oc, void *data)
1452 {
1453 MachineClass *mc = MACHINE_CLASS(oc);
1454
1455 mc->desc = "Sun4m platform, SPARCstation Voyager";
1456 mc->init = vger_init;
1457 mc->block_default_type = IF_SCSI;
1458 mc->default_boot_order = "c";
1459 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1460 }
1461
1462 static const TypeInfo voyager_type = {
1463 .name = MACHINE_TYPE_NAME("Voyager"),
1464 .parent = TYPE_MACHINE,
1465 .class_init = voyager_class_init,
1466 };
1467
1468 static void ss_lx_class_init(ObjectClass *oc, void *data)
1469 {
1470 MachineClass *mc = MACHINE_CLASS(oc);
1471
1472 mc->desc = "Sun4m platform, SPARCstation LX";
1473 mc->init = ss_lx_init;
1474 mc->block_default_type = IF_SCSI;
1475 mc->default_boot_order = "c";
1476 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1477 }
1478
1479 static const TypeInfo ss_lx_type = {
1480 .name = MACHINE_TYPE_NAME("LX"),
1481 .parent = TYPE_MACHINE,
1482 .class_init = ss_lx_class_init,
1483 };
1484
1485 static void ss4_class_init(ObjectClass *oc, void *data)
1486 {
1487 MachineClass *mc = MACHINE_CLASS(oc);
1488
1489 mc->desc = "Sun4m platform, SPARCstation 4";
1490 mc->init = ss4_init;
1491 mc->block_default_type = IF_SCSI;
1492 mc->default_boot_order = "c";
1493 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1494 }
1495
1496 static const TypeInfo ss4_type = {
1497 .name = MACHINE_TYPE_NAME("SS-4"),
1498 .parent = TYPE_MACHINE,
1499 .class_init = ss4_class_init,
1500 };
1501
1502 static void scls_class_init(ObjectClass *oc, void *data)
1503 {
1504 MachineClass *mc = MACHINE_CLASS(oc);
1505
1506 mc->desc = "Sun4m platform, SPARCClassic";
1507 mc->init = scls_init;
1508 mc->block_default_type = IF_SCSI;
1509 mc->default_boot_order = "c";
1510 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1511 }
1512
1513 static const TypeInfo scls_type = {
1514 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1515 .parent = TYPE_MACHINE,
1516 .class_init = scls_class_init,
1517 };
1518
1519 static void sbook_class_init(ObjectClass *oc, void *data)
1520 {
1521 MachineClass *mc = MACHINE_CLASS(oc);
1522
1523 mc->desc = "Sun4m platform, SPARCbook";
1524 mc->init = sbook_init;
1525 mc->block_default_type = IF_SCSI;
1526 mc->default_boot_order = "c";
1527 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1528 }
1529
1530 static const TypeInfo sbook_type = {
1531 .name = MACHINE_TYPE_NAME("SPARCbook"),
1532 .parent = TYPE_MACHINE,
1533 .class_init = sbook_class_init,
1534 };
1535
1536 static void sun4m_register_types(void)
1537 {
1538 type_register_static(&idreg_info);
1539 type_register_static(&afx_info);
1540 type_register_static(&prom_info);
1541 type_register_static(&ram_info);
1542
1543 type_register_static(&ss5_type);
1544 type_register_static(&ss10_type);
1545 type_register_static(&ss600mp_type);
1546 type_register_static(&ss20_type);
1547 type_register_static(&voyager_type);
1548 type_register_static(&ss_lx_type);
1549 type_register_static(&ss4_type);
1550 type_register_static(&scls_type);
1551 type_register_static(&sbook_type);
1552 }
1553
1554 type_init(sun4m_register_types)
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