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Commit | Line | Data |
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b00052e4 AZ |
1 | /* |
2 | * PXA270-based Clamshell PDA platforms. | |
3 | * | |
4 | * Copyright (c) 2006 Openedhand Ltd. | |
5 | * Written by Andrzej Zaborowski <balrog@zabor.org> | |
6 | * | |
7 | * This code is licensed under the GNU GPL v2. | |
8 | */ | |
9 | ||
87ecb68b PB |
10 | #include "hw.h" |
11 | #include "pxa.h" | |
12 | #include "arm-misc.h" | |
13 | #include "sysemu.h" | |
14 | #include "pcmcia.h" | |
15 | #include "i2c.h" | |
a984a69e | 16 | #include "ssi.h" |
87ecb68b PB |
17 | #include "flash.h" |
18 | #include "qemu-timer.h" | |
19 | #include "devices.h" | |
e33d8cdb | 20 | #include "sharpsl.h" |
87ecb68b PB |
21 | #include "console.h" |
22 | #include "block.h" | |
23 | #include "audio/audio.h" | |
24 | #include "boards.h" | |
2446333c | 25 | #include "blockdev.h" |
383d01c6 | 26 | #include "sysbus.h" |
b00052e4 | 27 | |
b00052e4 AZ |
28 | #undef REG_FMT |
29 | #define REG_FMT "0x%02lx" | |
30 | ||
31 | /* Spitz Flash */ | |
32 | #define FLASH_BASE 0x0c000000 | |
33 | #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ | |
34 | #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ | |
35 | #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ | |
36 | #define FLASH_ECCCNTR 0x0c /* ECC byte counter */ | |
37 | #define FLASH_ECCCLRR 0x10 /* Clear ECC */ | |
38 | #define FLASH_FLASHIO 0x14 /* Flash I/O */ | |
39 | #define FLASH_FLASHCTL 0x18 /* Flash Control */ | |
40 | ||
41 | #define FLASHCTL_CE0 (1 << 0) | |
42 | #define FLASHCTL_CLE (1 << 1) | |
43 | #define FLASHCTL_ALE (1 << 2) | |
44 | #define FLASHCTL_WP (1 << 3) | |
45 | #define FLASHCTL_CE1 (1 << 4) | |
46 | #define FLASHCTL_RYBY (1 << 5) | |
47 | #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) | |
48 | ||
bc24a225 | 49 | typedef struct { |
34f9f0b5 | 50 | SysBusDevice busdev; |
bc24a225 | 51 | NANDFlashState *nand; |
b00052e4 | 52 | uint8_t ctl; |
34f9f0b5 DES |
53 | uint8_t manf_id; |
54 | uint8_t chip_id; | |
bc24a225 PB |
55 | ECCState ecc; |
56 | } SLNANDState; | |
b00052e4 | 57 | |
c227f099 | 58 | static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) |
b00052e4 | 59 | { |
bc24a225 | 60 | SLNANDState *s = (SLNANDState *) opaque; |
b00052e4 | 61 | int ryby; |
b00052e4 AZ |
62 | |
63 | switch (addr) { | |
64 | #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) | |
65 | case FLASH_ECCLPLB: | |
66 | return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | | |
67 | BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); | |
68 | ||
69 | #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) | |
70 | case FLASH_ECCLPUB: | |
71 | return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | | |
72 | BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); | |
73 | ||
74 | case FLASH_ECCCP: | |
75 | return s->ecc.cp; | |
76 | ||
77 | case FLASH_ECCCNTR: | |
78 | return s->ecc.count & 0xff; | |
79 | ||
80 | case FLASH_FLASHCTL: | |
81 | nand_getpins(s->nand, &ryby); | |
82 | if (ryby) | |
83 | return s->ctl | FLASHCTL_RYBY; | |
84 | else | |
85 | return s->ctl; | |
86 | ||
87 | case FLASH_FLASHIO: | |
88 | return ecc_digest(&s->ecc, nand_getio(s->nand)); | |
89 | ||
90 | default: | |
a8b7063b | 91 | zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
b00052e4 AZ |
92 | } |
93 | return 0; | |
94 | } | |
95 | ||
c227f099 | 96 | static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) |
a5236105 | 97 | { |
bc24a225 | 98 | SLNANDState *s = (SLNANDState *) opaque; |
a5236105 AZ |
99 | |
100 | if (addr == FLASH_FLASHIO) | |
101 | return ecc_digest(&s->ecc, nand_getio(s->nand)) | | |
102 | (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16); | |
103 | ||
104 | return sl_readb(opaque, addr); | |
105 | } | |
106 | ||
c227f099 | 107 | static void sl_writeb(void *opaque, target_phys_addr_t addr, |
b00052e4 AZ |
108 | uint32_t value) |
109 | { | |
bc24a225 | 110 | SLNANDState *s = (SLNANDState *) opaque; |
b00052e4 AZ |
111 | |
112 | switch (addr) { | |
113 | case FLASH_ECCCLRR: | |
114 | /* Value is ignored. */ | |
115 | ecc_reset(&s->ecc); | |
116 | break; | |
117 | ||
118 | case FLASH_FLASHCTL: | |
119 | s->ctl = value & 0xff & ~FLASHCTL_RYBY; | |
120 | nand_setpins(s->nand, | |
121 | s->ctl & FLASHCTL_CLE, | |
122 | s->ctl & FLASHCTL_ALE, | |
123 | s->ctl & FLASHCTL_NCE, | |
124 | s->ctl & FLASHCTL_WP, | |
125 | 0); | |
126 | break; | |
127 | ||
128 | case FLASH_FLASHIO: | |
129 | nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff)); | |
130 | break; | |
131 | ||
132 | default: | |
a8b7063b | 133 | zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
b00052e4 AZ |
134 | } |
135 | } | |
136 | ||
137 | enum { | |
138 | FLASH_128M, | |
139 | FLASH_1024M, | |
140 | }; | |
141 | ||
34f9f0b5 DES |
142 | static CPUReadMemoryFunc * const sl_readfn[] = { |
143 | sl_readb, | |
144 | sl_readb, | |
145 | sl_readl, | |
146 | }; | |
147 | static CPUWriteMemoryFunc * const sl_writefn[] = { | |
148 | sl_writeb, | |
149 | sl_writeb, | |
150 | sl_writeb, | |
151 | }; | |
152 | ||
bc24a225 | 153 | static void sl_flash_register(PXA2xxState *cpu, int size) |
b00052e4 | 154 | { |
34f9f0b5 DES |
155 | DeviceState *dev; |
156 | ||
157 | dev = qdev_create(NULL, "sl-nand"); | |
158 | ||
159 | qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG); | |
160 | if (size == FLASH_128M) | |
161 | qdev_prop_set_uint8(dev, "chip_id", 0x73); | |
162 | else if (size == FLASH_1024M) | |
163 | qdev_prop_set_uint8(dev, "chip_id", 0xf1); | |
164 | ||
165 | qdev_init_nofail(dev); | |
166 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, FLASH_BASE); | |
167 | } | |
168 | ||
169 | static int sl_nand_init(SysBusDevice *dev) { | |
b00052e4 | 170 | int iomemtype; |
bc24a225 | 171 | SLNANDState *s; |
34f9f0b5 DES |
172 | |
173 | s = FROM_SYSBUS(SLNANDState, dev); | |
174 | ||
b00052e4 | 175 | s->ctl = 0; |
34f9f0b5 | 176 | s->nand = nand_init(s->manf_id, s->chip_id); |
b00052e4 | 177 | |
1eed09cb | 178 | iomemtype = cpu_register_io_memory(sl_readfn, |
2507c12a | 179 | sl_writefn, s, DEVICE_NATIVE_ENDIAN); |
aa941b94 | 180 | |
34f9f0b5 DES |
181 | sysbus_init_mmio(dev, 0x40, iomemtype); |
182 | ||
183 | return 0; | |
b00052e4 AZ |
184 | } |
185 | ||
186 | /* Spitz Keyboard */ | |
187 | ||
188 | #define SPITZ_KEY_STROBE_NUM 11 | |
189 | #define SPITZ_KEY_SENSE_NUM 7 | |
190 | ||
191 | static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { | |
192 | 12, 17, 91, 34, 36, 38, 39 | |
193 | }; | |
194 | ||
195 | static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = { | |
196 | 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 | |
197 | }; | |
198 | ||
199 | /* Eighth additional row maps the special keys */ | |
200 | static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { | |
201 | { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 }, | |
202 | { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 }, | |
203 | { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 }, | |
204 | { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 }, | |
205 | { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 }, | |
2b76bdc9 AZ |
206 | { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 }, |
207 | { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 }, | |
b00052e4 AZ |
208 | { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, |
209 | }; | |
210 | ||
211 | #define SPITZ_GPIO_AK_INT 13 /* Remote control */ | |
212 | #define SPITZ_GPIO_SYNC 16 /* Sync button */ | |
213 | #define SPITZ_GPIO_ON_KEY 95 /* Power button */ | |
214 | #define SPITZ_GPIO_SWA 97 /* Lid */ | |
215 | #define SPITZ_GPIO_SWB 96 /* Tablet mode */ | |
216 | ||
217 | /* The special buttons are mapped to unused keys */ | |
218 | static const int spitz_gpiomap[5] = { | |
219 | SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY, | |
220 | SPITZ_GPIO_SWA, SPITZ_GPIO_SWB, | |
221 | }; | |
222 | static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, }; | |
223 | ||
bc24a225 | 224 | typedef struct { |
38641a52 AZ |
225 | qemu_irq sense[SPITZ_KEY_SENSE_NUM]; |
226 | qemu_irq *strobe; | |
227 | qemu_irq gpiomap[5]; | |
b00052e4 AZ |
228 | int keymap[0x80]; |
229 | uint16_t keyrow[SPITZ_KEY_SENSE_NUM]; | |
230 | uint16_t strobe_state; | |
231 | uint16_t sense_state; | |
232 | ||
233 | uint16_t pre_map[0x100]; | |
234 | uint16_t modifiers; | |
235 | uint16_t imodifiers; | |
236 | uint8_t fifo[16]; | |
237 | int fifopos, fifolen; | |
238 | QEMUTimer *kbdtimer; | |
bc24a225 | 239 | } SpitzKeyboardState; |
b00052e4 | 240 | |
bc24a225 | 241 | static void spitz_keyboard_sense_update(SpitzKeyboardState *s) |
b00052e4 AZ |
242 | { |
243 | int i; | |
244 | uint16_t strobe, sense = 0; | |
245 | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) { | |
246 | strobe = s->keyrow[i] & s->strobe_state; | |
247 | if (strobe) { | |
248 | sense |= 1 << i; | |
249 | if (!(s->sense_state & (1 << i))) | |
38641a52 | 250 | qemu_irq_raise(s->sense[i]); |
b00052e4 | 251 | } else if (s->sense_state & (1 << i)) |
38641a52 | 252 | qemu_irq_lower(s->sense[i]); |
b00052e4 AZ |
253 | } |
254 | ||
255 | s->sense_state = sense; | |
256 | } | |
257 | ||
38641a52 | 258 | static void spitz_keyboard_strobe(void *opaque, int line, int level) |
b00052e4 | 259 | { |
bc24a225 | 260 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
38641a52 AZ |
261 | |
262 | if (level) | |
263 | s->strobe_state |= 1 << line; | |
264 | else | |
265 | s->strobe_state &= ~(1 << line); | |
266 | spitz_keyboard_sense_update(s); | |
b00052e4 AZ |
267 | } |
268 | ||
bc24a225 | 269 | static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode) |
b00052e4 AZ |
270 | { |
271 | int spitz_keycode = s->keymap[keycode & 0x7f]; | |
272 | if (spitz_keycode == -1) | |
273 | return; | |
274 | ||
275 | /* Handle the additional keys */ | |
276 | if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) { | |
38641a52 | 277 | qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^ |
b00052e4 AZ |
278 | spitz_gpio_invert[spitz_keycode & 0xf]); |
279 | return; | |
280 | } | |
281 | ||
282 | if (keycode & 0x80) | |
283 | s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf)); | |
284 | else | |
285 | s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf); | |
286 | ||
287 | spitz_keyboard_sense_update(s); | |
288 | } | |
289 | ||
290 | #define SHIFT (1 << 7) | |
291 | #define CTRL (1 << 8) | |
292 | #define FN (1 << 9) | |
293 | ||
294 | #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c | |
295 | ||
bc24a225 | 296 | static void spitz_keyboard_handler(SpitzKeyboardState *s, int keycode) |
b00052e4 AZ |
297 | { |
298 | uint16_t code; | |
299 | int mapcode; | |
300 | switch (keycode) { | |
301 | case 0x2a: /* Left Shift */ | |
302 | s->modifiers |= 1; | |
303 | break; | |
304 | case 0xaa: | |
305 | s->modifiers &= ~1; | |
306 | break; | |
307 | case 0x36: /* Right Shift */ | |
308 | s->modifiers |= 2; | |
309 | break; | |
310 | case 0xb6: | |
311 | s->modifiers &= ~2; | |
312 | break; | |
313 | case 0x1d: /* Control */ | |
314 | s->modifiers |= 4; | |
315 | break; | |
316 | case 0x9d: | |
317 | s->modifiers &= ~4; | |
318 | break; | |
319 | case 0x38: /* Alt */ | |
320 | s->modifiers |= 8; | |
321 | break; | |
322 | case 0xb8: | |
323 | s->modifiers &= ~8; | |
324 | break; | |
325 | } | |
326 | ||
327 | code = s->pre_map[mapcode = ((s->modifiers & 3) ? | |
328 | (keycode | SHIFT) : | |
329 | (keycode & ~SHIFT))]; | |
330 | ||
331 | if (code != mapcode) { | |
332 | #if 0 | |
333 | if ((code & SHIFT) && !(s->modifiers & 1)) | |
334 | QUEUE_KEY(0x2a | (keycode & 0x80)); | |
335 | if ((code & CTRL ) && !(s->modifiers & 4)) | |
336 | QUEUE_KEY(0x1d | (keycode & 0x80)); | |
337 | if ((code & FN ) && !(s->modifiers & 8)) | |
338 | QUEUE_KEY(0x38 | (keycode & 0x80)); | |
339 | if ((code & FN ) && (s->modifiers & 1)) | |
340 | QUEUE_KEY(0x2a | (~keycode & 0x80)); | |
341 | if ((code & FN ) && (s->modifiers & 2)) | |
342 | QUEUE_KEY(0x36 | (~keycode & 0x80)); | |
343 | #else | |
344 | if (keycode & 0x80) { | |
345 | if ((s->imodifiers & 1 ) && !(s->modifiers & 1)) | |
346 | QUEUE_KEY(0x2a | 0x80); | |
347 | if ((s->imodifiers & 4 ) && !(s->modifiers & 4)) | |
348 | QUEUE_KEY(0x1d | 0x80); | |
349 | if ((s->imodifiers & 8 ) && !(s->modifiers & 8)) | |
350 | QUEUE_KEY(0x38 | 0x80); | |
351 | if ((s->imodifiers & 0x10) && (s->modifiers & 1)) | |
352 | QUEUE_KEY(0x2a); | |
353 | if ((s->imodifiers & 0x20) && (s->modifiers & 2)) | |
354 | QUEUE_KEY(0x36); | |
355 | s->imodifiers = 0; | |
356 | } else { | |
357 | if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) { | |
358 | QUEUE_KEY(0x2a); | |
359 | s->imodifiers |= 1; | |
360 | } | |
361 | if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) { | |
362 | QUEUE_KEY(0x1d); | |
363 | s->imodifiers |= 4; | |
364 | } | |
365 | if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) { | |
366 | QUEUE_KEY(0x38); | |
367 | s->imodifiers |= 8; | |
368 | } | |
369 | if ((code & FN ) && (s->modifiers & 1) && | |
370 | !(s->imodifiers & 0x10)) { | |
371 | QUEUE_KEY(0x2a | 0x80); | |
372 | s->imodifiers |= 0x10; | |
373 | } | |
374 | if ((code & FN ) && (s->modifiers & 2) && | |
375 | !(s->imodifiers & 0x20)) { | |
376 | QUEUE_KEY(0x36 | 0x80); | |
377 | s->imodifiers |= 0x20; | |
378 | } | |
379 | } | |
380 | #endif | |
381 | } | |
382 | ||
383 | QUEUE_KEY((code & 0x7f) | (keycode & 0x80)); | |
384 | } | |
385 | ||
386 | static void spitz_keyboard_tick(void *opaque) | |
387 | { | |
bc24a225 | 388 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
b00052e4 AZ |
389 | |
390 | if (s->fifolen) { | |
391 | spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]); | |
392 | s->fifolen --; | |
393 | if (s->fifopos >= 16) | |
394 | s->fifopos = 0; | |
395 | } | |
396 | ||
6ee093c9 JQ |
397 | qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + |
398 | get_ticks_per_sec() / 32); | |
b00052e4 AZ |
399 | } |
400 | ||
bc24a225 | 401 | static void spitz_keyboard_pre_map(SpitzKeyboardState *s) |
b00052e4 AZ |
402 | { |
403 | int i; | |
404 | for (i = 0; i < 0x100; i ++) | |
405 | s->pre_map[i] = i; | |
406 | s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */ | |
407 | s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */ | |
408 | s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */ | |
409 | s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */ | |
410 | s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */ | |
411 | s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */ | |
412 | s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */ | |
413 | s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */ | |
414 | s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */ | |
415 | s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */ | |
416 | s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */ | |
417 | s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */ | |
418 | s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */ | |
419 | s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */ | |
420 | s->pre_map[0x0d ] = 0x12 | FN; /* equal */ | |
421 | s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */ | |
422 | s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */ | |
423 | s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */ | |
2b76bdc9 AZ |
424 | s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */ |
425 | s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */ | |
b00052e4 AZ |
426 | s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */ |
427 | s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */ | |
428 | s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */ | |
429 | s->pre_map[0x2b ] = 0x25 | FN; /* backslash */ | |
430 | s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */ | |
431 | s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */ | |
2b76bdc9 | 432 | s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */ |
b00052e4 | 433 | s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */ |
2b76bdc9 | 434 | s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */ |
b00052e4 AZ |
435 | s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */ |
436 | s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */ | |
437 | s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */ | |
438 | ||
439 | s->modifiers = 0; | |
440 | s->imodifiers = 0; | |
441 | s->fifopos = 0; | |
442 | s->fifolen = 0; | |
443 | s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s); | |
444 | spitz_keyboard_tick(s); | |
445 | } | |
446 | ||
447 | #undef SHIFT | |
448 | #undef CTRL | |
449 | #undef FN | |
450 | ||
aa941b94 AZ |
451 | static void spitz_keyboard_save(QEMUFile *f, void *opaque) |
452 | { | |
bc24a225 | 453 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
aa941b94 AZ |
454 | int i; |
455 | ||
456 | qemu_put_be16s(f, &s->sense_state); | |
457 | qemu_put_be16s(f, &s->strobe_state); | |
458 | for (i = 0; i < 5; i ++) | |
459 | qemu_put_byte(f, spitz_gpio_invert[i]); | |
460 | } | |
461 | ||
462 | static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id) | |
463 | { | |
bc24a225 | 464 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
aa941b94 AZ |
465 | int i; |
466 | ||
467 | qemu_get_be16s(f, &s->sense_state); | |
468 | qemu_get_be16s(f, &s->strobe_state); | |
469 | for (i = 0; i < 5; i ++) | |
470 | spitz_gpio_invert[i] = qemu_get_byte(f); | |
471 | ||
472 | /* Release all pressed keys */ | |
473 | memset(s->keyrow, 0, sizeof(s->keyrow)); | |
474 | spitz_keyboard_sense_update(s); | |
475 | s->modifiers = 0; | |
476 | s->imodifiers = 0; | |
477 | s->fifopos = 0; | |
478 | s->fifolen = 0; | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
bc24a225 | 483 | static void spitz_keyboard_register(PXA2xxState *cpu) |
b00052e4 AZ |
484 | { |
485 | int i, j; | |
bc24a225 | 486 | SpitzKeyboardState *s; |
b00052e4 | 487 | |
bc24a225 PB |
488 | s = (SpitzKeyboardState *) |
489 | qemu_mallocz(sizeof(SpitzKeyboardState)); | |
490 | memset(s, 0, sizeof(SpitzKeyboardState)); | |
b00052e4 AZ |
491 | |
492 | for (i = 0; i < 0x80; i ++) | |
493 | s->keymap[i] = -1; | |
494 | for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++) | |
495 | for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++) | |
496 | if (spitz_keymap[i][j] != -1) | |
497 | s->keymap[spitz_keymap[i][j]] = (i << 4) | j; | |
498 | ||
38641a52 AZ |
499 | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) |
500 | s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]]; | |
501 | ||
502 | for (i = 0; i < 5; i ++) | |
503 | s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]]; | |
504 | ||
505 | s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s, | |
506 | SPITZ_KEY_STROBE_NUM); | |
b00052e4 | 507 | for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++) |
38641a52 | 508 | pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]); |
b00052e4 AZ |
509 | |
510 | spitz_keyboard_pre_map(s); | |
511 | qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s); | |
aa941b94 | 512 | |
0be71e32 | 513 | register_savevm(NULL, "spitz_keyboard", 0, 0, |
aa941b94 | 514 | spitz_keyboard_save, spitz_keyboard_load, s); |
b00052e4 AZ |
515 | } |
516 | ||
b00052e4 AZ |
517 | /* LCD backlight controller */ |
518 | ||
519 | #define LCDTG_RESCTL 0x00 | |
520 | #define LCDTG_PHACTRL 0x01 | |
521 | #define LCDTG_DUTYCTRL 0x02 | |
522 | #define LCDTG_POWERREG0 0x03 | |
523 | #define LCDTG_POWERREG1 0x04 | |
524 | #define LCDTG_GPOR3 0x05 | |
525 | #define LCDTG_PICTRL 0x06 | |
526 | #define LCDTG_POLCTRL 0x07 | |
527 | ||
a984a69e PB |
528 | typedef struct { |
529 | SSISlave ssidev; | |
43842120 DES |
530 | uint32_t bl_intensity; |
531 | uint32_t bl_power; | |
a984a69e | 532 | } SpitzLCDTG; |
b00052e4 | 533 | |
a984a69e | 534 | static void spitz_bl_update(SpitzLCDTG *s) |
b00052e4 | 535 | { |
a984a69e PB |
536 | if (s->bl_power && s->bl_intensity) |
537 | zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity); | |
b00052e4 | 538 | else |
89cdb6af | 539 | zaurus_printf("LCD Backlight now off\n"); |
b00052e4 AZ |
540 | } |
541 | ||
a984a69e PB |
542 | /* FIXME: Implement GPIO properly and remove this hack. */ |
543 | static SpitzLCDTG *spitz_lcdtg; | |
544 | ||
38641a52 | 545 | static inline void spitz_bl_bit5(void *opaque, int line, int level) |
b00052e4 | 546 | { |
a984a69e PB |
547 | SpitzLCDTG *s = spitz_lcdtg; |
548 | int prev = s->bl_intensity; | |
b00052e4 AZ |
549 | |
550 | if (level) | |
a984a69e | 551 | s->bl_intensity &= ~0x20; |
b00052e4 | 552 | else |
a984a69e | 553 | s->bl_intensity |= 0x20; |
b00052e4 | 554 | |
a984a69e PB |
555 | if (s->bl_power && prev != s->bl_intensity) |
556 | spitz_bl_update(s); | |
b00052e4 AZ |
557 | } |
558 | ||
38641a52 | 559 | static inline void spitz_bl_power(void *opaque, int line, int level) |
b00052e4 | 560 | { |
a984a69e PB |
561 | SpitzLCDTG *s = spitz_lcdtg; |
562 | s->bl_power = !!level; | |
563 | spitz_bl_update(s); | |
b00052e4 AZ |
564 | } |
565 | ||
a984a69e | 566 | static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) |
b00052e4 | 567 | { |
a984a69e PB |
568 | SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); |
569 | int addr; | |
570 | addr = value >> 5; | |
571 | value &= 0x1f; | |
b00052e4 AZ |
572 | |
573 | switch (addr) { | |
574 | case LCDTG_RESCTL: | |
575 | if (value) | |
89cdb6af | 576 | zaurus_printf("LCD in QVGA mode\n"); |
b00052e4 | 577 | else |
89cdb6af | 578 | zaurus_printf("LCD in VGA mode\n"); |
b00052e4 AZ |
579 | break; |
580 | ||
581 | case LCDTG_DUTYCTRL: | |
a984a69e PB |
582 | s->bl_intensity &= ~0x1f; |
583 | s->bl_intensity |= value; | |
584 | if (s->bl_power) | |
585 | spitz_bl_update(s); | |
b00052e4 AZ |
586 | break; |
587 | ||
588 | case LCDTG_POWERREG0: | |
589 | /* Set common voltage to M62332FP */ | |
590 | break; | |
591 | } | |
a984a69e PB |
592 | return 0; |
593 | } | |
594 | ||
81a322d4 | 595 | static int spitz_lcdtg_init(SSISlave *dev) |
a984a69e PB |
596 | { |
597 | SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); | |
598 | ||
599 | spitz_lcdtg = s; | |
600 | s->bl_power = 0; | |
601 | s->bl_intensity = 0x20; | |
602 | ||
81a322d4 | 603 | return 0; |
b00052e4 AZ |
604 | } |
605 | ||
606 | /* SSP devices */ | |
607 | ||
608 | #define CORGI_SSP_PORT 2 | |
609 | ||
610 | #define SPITZ_GPIO_LCDCON_CS 53 | |
611 | #define SPITZ_GPIO_ADS7846_CS 14 | |
612 | #define SPITZ_GPIO_MAX1111_CS 20 | |
613 | #define SPITZ_GPIO_TP_INT 11 | |
614 | ||
a984a69e | 615 | static DeviceState *max1111; |
b00052e4 AZ |
616 | |
617 | /* "Demux" the signal based on current chipselect */ | |
a984a69e PB |
618 | typedef struct { |
619 | SSISlave ssidev; | |
620 | SSIBus *bus[3]; | |
43842120 | 621 | uint32_t enable[3]; |
a984a69e | 622 | } CorgiSSPState; |
b00052e4 | 623 | |
a984a69e | 624 | static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value) |
b00052e4 | 625 | { |
a984a69e PB |
626 | CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); |
627 | int i; | |
628 | ||
629 | for (i = 0; i < 3; i++) { | |
630 | if (s->enable[i]) { | |
631 | return ssi_transfer(s->bus[i], value); | |
632 | } | |
633 | } | |
634 | return 0; | |
b00052e4 AZ |
635 | } |
636 | ||
38641a52 | 637 | static void corgi_ssp_gpio_cs(void *opaque, int line, int level) |
b00052e4 | 638 | { |
a984a69e PB |
639 | CorgiSSPState *s = (CorgiSSPState *)opaque; |
640 | assert(line >= 0 && line < 3); | |
641 | s->enable[line] = !level; | |
b00052e4 AZ |
642 | } |
643 | ||
644 | #define MAX1111_BATT_VOLT 1 | |
645 | #define MAX1111_BATT_TEMP 2 | |
646 | #define MAX1111_ACIN_VOLT 3 | |
647 | ||
648 | #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ | |
649 | #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ | |
650 | #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ | |
651 | ||
38641a52 | 652 | static void spitz_adc_temp_on(void *opaque, int line, int level) |
b00052e4 AZ |
653 | { |
654 | if (!max1111) | |
655 | return; | |
656 | ||
657 | if (level) | |
658 | max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); | |
659 | else | |
660 | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); | |
661 | } | |
662 | ||
81a322d4 | 663 | static int corgi_ssp_init(SSISlave *dev) |
a984a69e PB |
664 | { |
665 | CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); | |
666 | ||
667 | qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3); | |
02e2da45 PB |
668 | s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0"); |
669 | s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1"); | |
670 | s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2"); | |
a984a69e | 671 | |
81a322d4 | 672 | return 0; |
a984a69e PB |
673 | } |
674 | ||
bc24a225 | 675 | static void spitz_ssp_attach(PXA2xxState *cpu) |
b00052e4 | 676 | { |
a984a69e PB |
677 | DeviceState *mux; |
678 | DeviceState *dev; | |
679 | void *bus; | |
680 | ||
681 | mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); | |
38641a52 | 682 | |
a984a69e | 683 | bus = qdev_get_child_bus(mux, "ssi0"); |
22ed1d34 | 684 | ssi_create_slave(bus, "spitz-lcdtg"); |
b00052e4 | 685 | |
a984a69e PB |
686 | bus = qdev_get_child_bus(mux, "ssi1"); |
687 | dev = ssi_create_slave(bus, "ads7846"); | |
688 | qdev_connect_gpio_out(dev, 0, | |
689 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]); | |
b00052e4 | 690 | |
a984a69e PB |
691 | bus = qdev_get_child_bus(mux, "ssi2"); |
692 | max1111 = ssi_create_slave(bus, "max1111"); | |
b00052e4 AZ |
693 | max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); |
694 | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); | |
695 | max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); | |
696 | ||
a984a69e PB |
697 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, |
698 | qdev_get_gpio_in(mux, 0)); | |
699 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, | |
700 | qdev_get_gpio_in(mux, 1)); | |
701 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, | |
702 | qdev_get_gpio_in(mux, 2)); | |
b00052e4 AZ |
703 | } |
704 | ||
705 | /* CF Microdrive */ | |
706 | ||
bc24a225 | 707 | static void spitz_microdrive_attach(PXA2xxState *cpu, int slot) |
b00052e4 | 708 | { |
bc24a225 | 709 | PCMCIACardState *md; |
e4bcb14c | 710 | BlockDriverState *bs; |
751c6a17 | 711 | DriveInfo *dinfo; |
b00052e4 | 712 | |
751c6a17 GH |
713 | dinfo = drive_get(IF_IDE, 0, 0); |
714 | if (!dinfo) | |
e4bcb14c | 715 | return; |
751c6a17 | 716 | bs = dinfo->bdrv; |
e4bcb14c | 717 | if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) { |
f455e98c | 718 | md = dscm1xxxx_init(dinfo); |
15b18ec2 | 719 | pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md); |
b00052e4 AZ |
720 | } |
721 | } | |
722 | ||
adb86c37 AZ |
723 | /* Wm8750 and Max7310 on I2C */ |
724 | ||
725 | #define AKITA_MAX_ADDR 0x18 | |
611d7189 AZ |
726 | #define SPITZ_WM_ADDRL 0x1b |
727 | #define SPITZ_WM_ADDRH 0x1a | |
adb86c37 AZ |
728 | |
729 | #define SPITZ_GPIO_WM 5 | |
730 | ||
38641a52 | 731 | static void spitz_wm8750_addr(void *opaque, int line, int level) |
adb86c37 AZ |
732 | { |
733 | i2c_slave *wm = (i2c_slave *) opaque; | |
734 | if (level) | |
735 | i2c_set_slave_address(wm, SPITZ_WM_ADDRH); | |
736 | else | |
737 | i2c_set_slave_address(wm, SPITZ_WM_ADDRL); | |
738 | } | |
adb86c37 | 739 | |
bc24a225 | 740 | static void spitz_i2c_setup(PXA2xxState *cpu) |
adb86c37 AZ |
741 | { |
742 | /* Attach the CPU on one end of our I2C bus. */ | |
743 | i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]); | |
744 | ||
cdbe40ca | 745 | DeviceState *wm; |
adb86c37 | 746 | |
adb86c37 | 747 | /* Attach a WM8750 to the bus */ |
cdbe40ca | 748 | wm = i2c_create_slave(bus, "wm8750", 0); |
adb86c37 | 749 | |
38641a52 AZ |
750 | spitz_wm8750_addr(wm, 0, 0); |
751 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM, | |
752 | qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]); | |
adb86c37 AZ |
753 | /* .. and to the sound interface. */ |
754 | cpu->i2s->opaque = wm; | |
755 | cpu->i2s->codec_out = wm8750_dac_dat; | |
756 | cpu->i2s->codec_in = wm8750_adc_dat; | |
757 | wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s); | |
adb86c37 AZ |
758 | } |
759 | ||
bc24a225 | 760 | static void spitz_akita_i2c_setup(PXA2xxState *cpu) |
adb86c37 AZ |
761 | { |
762 | /* Attach a Max7310 to Akita I2C bus. */ | |
6c0bd6bd PB |
763 | i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310", |
764 | AKITA_MAX_ADDR); | |
adb86c37 AZ |
765 | } |
766 | ||
b00052e4 AZ |
767 | /* Other peripherals */ |
768 | ||
38641a52 | 769 | static void spitz_out_switch(void *opaque, int line, int level) |
b00052e4 | 770 | { |
38641a52 AZ |
771 | switch (line) { |
772 | case 0: | |
89cdb6af | 773 | zaurus_printf("Charging %s.\n", level ? "off" : "on"); |
38641a52 AZ |
774 | break; |
775 | case 1: | |
89cdb6af | 776 | zaurus_printf("Discharging %s.\n", level ? "on" : "off"); |
38641a52 AZ |
777 | break; |
778 | case 2: | |
89cdb6af | 779 | zaurus_printf("Green LED %s.\n", level ? "on" : "off"); |
38641a52 AZ |
780 | break; |
781 | case 3: | |
89cdb6af | 782 | zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); |
38641a52 AZ |
783 | break; |
784 | case 4: | |
785 | spitz_bl_bit5(opaque, line, level); | |
786 | break; | |
787 | case 5: | |
788 | spitz_bl_power(opaque, line, level); | |
789 | break; | |
790 | case 6: | |
791 | spitz_adc_temp_on(opaque, line, level); | |
792 | break; | |
793 | } | |
b00052e4 AZ |
794 | } |
795 | ||
796 | #define SPITZ_SCP_LED_GREEN 1 | |
797 | #define SPITZ_SCP_JK_B 2 | |
798 | #define SPITZ_SCP_CHRG_ON 3 | |
799 | #define SPITZ_SCP_MUTE_L 4 | |
800 | #define SPITZ_SCP_MUTE_R 5 | |
801 | #define SPITZ_SCP_CF_POWER 6 | |
802 | #define SPITZ_SCP_LED_ORANGE 7 | |
803 | #define SPITZ_SCP_JK_A 8 | |
804 | #define SPITZ_SCP_ADC_TEMP_ON 9 | |
805 | #define SPITZ_SCP2_IR_ON 1 | |
806 | #define SPITZ_SCP2_AKIN_PULLUP 2 | |
807 | #define SPITZ_SCP2_BACKLIGHT_CONT 7 | |
808 | #define SPITZ_SCP2_BACKLIGHT_ON 8 | |
809 | #define SPITZ_SCP2_MIC_BIAS 9 | |
810 | ||
bc24a225 | 811 | static void spitz_scoop_gpio_setup(PXA2xxState *cpu, |
383d01c6 | 812 | DeviceState *scp0, DeviceState *scp1) |
b00052e4 | 813 | { |
38641a52 AZ |
814 | qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8); |
815 | ||
383d01c6 DES |
816 | qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); |
817 | qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]); | |
818 | qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); | |
819 | qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); | |
b00052e4 | 820 | |
e33d8cdb | 821 | if (scp1) { |
383d01c6 DES |
822 | qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]); |
823 | qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]); | |
b00052e4 AZ |
824 | } |
825 | ||
383d01c6 | 826 | qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); |
b00052e4 AZ |
827 | } |
828 | ||
829 | #define SPITZ_GPIO_HSYNC 22 | |
830 | #define SPITZ_GPIO_SD_DETECT 9 | |
831 | #define SPITZ_GPIO_SD_WP 81 | |
832 | #define SPITZ_GPIO_ON_RESET 89 | |
833 | #define SPITZ_GPIO_BAT_COVER 90 | |
834 | #define SPITZ_GPIO_CF1_IRQ 105 | |
835 | #define SPITZ_GPIO_CF1_CD 94 | |
836 | #define SPITZ_GPIO_CF2_IRQ 106 | |
837 | #define SPITZ_GPIO_CF2_CD 93 | |
838 | ||
38641a52 | 839 | static int spitz_hsync; |
b00052e4 | 840 | |
38641a52 | 841 | static void spitz_lcd_hsync_handler(void *opaque, int line, int level) |
b00052e4 | 842 | { |
bc24a225 | 843 | PXA2xxState *cpu = (PXA2xxState *) opaque; |
38641a52 | 844 | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync); |
b00052e4 AZ |
845 | spitz_hsync ^= 1; |
846 | } | |
847 | ||
bc24a225 | 848 | static void spitz_gpio_setup(PXA2xxState *cpu, int slots) |
b00052e4 | 849 | { |
38641a52 | 850 | qemu_irq lcd_hsync; |
b00052e4 AZ |
851 | /* |
852 | * Bad hack: We toggle the LCD hsync GPIO on every GPIO status | |
853 | * read to satisfy broken guests that poll-wait for hsync. | |
854 | * Simulating a real hsync event would be less practical and | |
855 | * wouldn't guarantee that a guest ever exits the loop. | |
856 | */ | |
857 | spitz_hsync = 0; | |
38641a52 AZ |
858 | lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0]; |
859 | pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync); | |
860 | pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync); | |
b00052e4 AZ |
861 | |
862 | /* MMC/SD host */ | |
02ce600c AZ |
863 | pxa2xx_mmci_handlers(cpu->mmc, |
864 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP], | |
865 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]); | |
b00052e4 AZ |
866 | |
867 | /* Battery lock always closed */ | |
38641a52 | 868 | qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]); |
b00052e4 AZ |
869 | |
870 | /* Handle reset */ | |
38641a52 | 871 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset); |
b00052e4 AZ |
872 | |
873 | /* PCMCIA signals: card's IRQ and Card-Detect */ | |
b00052e4 | 874 | if (slots >= 1) |
38641a52 AZ |
875 | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0], |
876 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ], | |
877 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]); | |
b00052e4 | 878 | if (slots >= 2) |
38641a52 AZ |
879 | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1], |
880 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ], | |
881 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]); | |
b00052e4 AZ |
882 | |
883 | /* Initialise the screen rotation related signals */ | |
884 | spitz_gpio_invert[3] = 0; /* Always open */ | |
885 | if (graphic_rotate) { /* Tablet mode */ | |
886 | spitz_gpio_invert[4] = 0; | |
887 | } else { /* Portrait mode */ | |
888 | spitz_gpio_invert[4] = 1; | |
889 | } | |
38641a52 AZ |
890 | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA], |
891 | spitz_gpio_invert[3]); | |
892 | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB], | |
893 | spitz_gpio_invert[4]); | |
b00052e4 AZ |
894 | } |
895 | ||
b00052e4 AZ |
896 | /* Board init. */ |
897 | enum spitz_model_e { spitz, akita, borzoi, terrier }; | |
898 | ||
7fb4fdcf AZ |
899 | #define SPITZ_RAM 0x04000000 |
900 | #define SPITZ_ROM 0x00800000 | |
901 | ||
f93eb9ff AZ |
902 | static struct arm_boot_info spitz_binfo = { |
903 | .loader_start = PXA2XX_SDRAM_BASE, | |
904 | .ram_size = 0x04000000, | |
905 | }; | |
906 | ||
c227f099 | 907 | static void spitz_common_init(ram_addr_t ram_size, |
3023f332 | 908 | const char *kernel_filename, |
b00052e4 | 909 | const char *kernel_cmdline, const char *initrd_filename, |
4207117c | 910 | const char *cpu_model, enum spitz_model_e model, int arm_id) |
b00052e4 | 911 | { |
bc24a225 | 912 | PXA2xxState *cpu; |
383d01c6 | 913 | DeviceState *scp0, *scp1 = NULL; |
b00052e4 | 914 | |
4207117c AZ |
915 | if (!cpu_model) |
916 | cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; | |
b00052e4 | 917 | |
d95b2f8d | 918 | /* Setup CPU & memory */ |
3023f332 | 919 | cpu = pxa270_init(spitz_binfo.ram_size, cpu_model); |
b00052e4 AZ |
920 | |
921 | sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); | |
922 | ||
7fb4fdcf | 923 | cpu_register_physical_memory(0, SPITZ_ROM, |
1724f049 | 924 | qemu_ram_alloc(NULL, "spitz.rom", SPITZ_ROM) | IO_MEM_ROM); |
b00052e4 AZ |
925 | |
926 | /* Setup peripherals */ | |
927 | spitz_keyboard_register(cpu); | |
928 | ||
929 | spitz_ssp_attach(cpu); | |
930 | ||
383d01c6 | 931 | scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); |
e33d8cdb | 932 | if (model != akita) { |
383d01c6 | 933 | scp1 = sysbus_create_simple("scoop", 0x08800040, NULL); |
e33d8cdb | 934 | } |
b00052e4 | 935 | |
e33d8cdb | 936 | spitz_scoop_gpio_setup(cpu, scp0, scp1); |
b00052e4 AZ |
937 | |
938 | spitz_gpio_setup(cpu, (model == akita) ? 1 : 2); | |
939 | ||
adb86c37 AZ |
940 | spitz_i2c_setup(cpu); |
941 | ||
942 | if (model == akita) | |
943 | spitz_akita_i2c_setup(cpu); | |
944 | ||
b00052e4 | 945 | if (model == terrier) |
bf5ee248 | 946 | /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */ |
15b18ec2 | 947 | spitz_microdrive_attach(cpu, 1); |
b00052e4 | 948 | else if (model != akita) |
15b18ec2 AZ |
949 | /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */ |
950 | spitz_microdrive_attach(cpu, 0); | |
b00052e4 | 951 | |
f93eb9ff AZ |
952 | spitz_binfo.kernel_filename = kernel_filename; |
953 | spitz_binfo.kernel_cmdline = kernel_cmdline; | |
954 | spitz_binfo.initrd_filename = initrd_filename; | |
955 | spitz_binfo.board_id = arm_id; | |
956 | arm_load_kernel(cpu->env, &spitz_binfo); | |
f78630ab | 957 | sl_bootparam_write(SL_PXA_PARAM_BASE); |
b00052e4 AZ |
958 | } |
959 | ||
c227f099 | 960 | static void spitz_init(ram_addr_t ram_size, |
3023f332 | 961 | const char *boot_device, |
b00052e4 AZ |
962 | const char *kernel_filename, const char *kernel_cmdline, |
963 | const char *initrd_filename, const char *cpu_model) | |
964 | { | |
fbe1b595 | 965 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 966 | kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9); |
b00052e4 AZ |
967 | } |
968 | ||
c227f099 | 969 | static void borzoi_init(ram_addr_t ram_size, |
3023f332 | 970 | const char *boot_device, |
b00052e4 AZ |
971 | const char *kernel_filename, const char *kernel_cmdline, |
972 | const char *initrd_filename, const char *cpu_model) | |
973 | { | |
fbe1b595 | 974 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 975 | kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f); |
b00052e4 AZ |
976 | } |
977 | ||
c227f099 | 978 | static void akita_init(ram_addr_t ram_size, |
3023f332 | 979 | const char *boot_device, |
b00052e4 AZ |
980 | const char *kernel_filename, const char *kernel_cmdline, |
981 | const char *initrd_filename, const char *cpu_model) | |
982 | { | |
fbe1b595 | 983 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 984 | kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8); |
b00052e4 AZ |
985 | } |
986 | ||
c227f099 | 987 | static void terrier_init(ram_addr_t ram_size, |
3023f332 | 988 | const char *boot_device, |
b00052e4 AZ |
989 | const char *kernel_filename, const char *kernel_cmdline, |
990 | const char *initrd_filename, const char *cpu_model) | |
991 | { | |
fbe1b595 | 992 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 993 | kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f); |
b00052e4 AZ |
994 | } |
995 | ||
11be4b3e | 996 | static QEMUMachine akitapda_machine = { |
4b32e168 AL |
997 | .name = "akita", |
998 | .desc = "Akita PDA (PXA270)", | |
999 | .init = akita_init, | |
b00052e4 AZ |
1000 | }; |
1001 | ||
f80f9ec9 | 1002 | static QEMUMachine spitzpda_machine = { |
4b32e168 AL |
1003 | .name = "spitz", |
1004 | .desc = "Spitz PDA (PXA270)", | |
1005 | .init = spitz_init, | |
b00052e4 AZ |
1006 | }; |
1007 | ||
f80f9ec9 | 1008 | static QEMUMachine borzoipda_machine = { |
4b32e168 AL |
1009 | .name = "borzoi", |
1010 | .desc = "Borzoi PDA (PXA270)", | |
1011 | .init = borzoi_init, | |
b00052e4 AZ |
1012 | }; |
1013 | ||
f80f9ec9 | 1014 | static QEMUMachine terrierpda_machine = { |
4b32e168 AL |
1015 | .name = "terrier", |
1016 | .desc = "Terrier PDA (PXA270)", | |
1017 | .init = terrier_init, | |
b00052e4 | 1018 | }; |
a984a69e | 1019 | |
f80f9ec9 AL |
1020 | static void spitz_machine_init(void) |
1021 | { | |
1022 | qemu_register_machine(&akitapda_machine); | |
1023 | qemu_register_machine(&spitzpda_machine); | |
1024 | qemu_register_machine(&borzoipda_machine); | |
1025 | qemu_register_machine(&terrierpda_machine); | |
1026 | } | |
1027 | ||
1028 | machine_init(spitz_machine_init); | |
1029 | ||
34f9f0b5 DES |
1030 | static VMStateDescription vmstate_sl_nand_info = { |
1031 | .name = "sl-nand", | |
1032 | .version_id = 0, | |
1033 | .minimum_version_id = 0, | |
1034 | .minimum_version_id_old = 0, | |
1035 | .fields = (VMStateField []) { | |
1036 | VMSTATE_UINT8(ctl, SLNANDState), | |
1037 | VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState), | |
1038 | VMSTATE_END_OF_LIST(), | |
1039 | }, | |
1040 | }; | |
1041 | ||
1042 | static SysBusDeviceInfo sl_nand_info = { | |
1043 | .init = sl_nand_init, | |
1044 | .qdev.name = "sl-nand", | |
1045 | .qdev.size = sizeof(SLNANDState), | |
1046 | .qdev.vmsd = &vmstate_sl_nand_info, | |
1047 | .qdev.props = (Property []) { | |
1048 | DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG), | |
1049 | DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1), | |
1050 | DEFINE_PROP_END_OF_LIST(), | |
1051 | }, | |
1052 | }; | |
1053 | ||
43842120 DES |
1054 | static const VMStateDescription vmstate_corgi_ssp_regs = { |
1055 | .name = "corgi-ssp", | |
1056 | .version_id = 1, | |
1057 | .minimum_version_id = 1, | |
1058 | .minimum_version_id_old = 1, | |
1059 | .fields = (VMStateField []) { | |
1060 | VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3), | |
1061 | VMSTATE_END_OF_LIST(), | |
1062 | } | |
1063 | }; | |
1064 | ||
a984a69e | 1065 | static SSISlaveInfo corgi_ssp_info = { |
074f2fff GH |
1066 | .qdev.name = "corgi-ssp", |
1067 | .qdev.size = sizeof(CorgiSSPState), | |
43842120 | 1068 | .qdev.vmsd = &vmstate_corgi_ssp_regs, |
a984a69e PB |
1069 | .init = corgi_ssp_init, |
1070 | .transfer = corgi_ssp_transfer | |
1071 | }; | |
1072 | ||
43842120 DES |
1073 | static const VMStateDescription vmstate_spitz_lcdtg_regs = { |
1074 | .name = "spitz-lcdtg", | |
1075 | .version_id = 1, | |
1076 | .minimum_version_id = 1, | |
1077 | .minimum_version_id_old = 1, | |
1078 | .fields = (VMStateField []) { | |
1079 | VMSTATE_UINT32(bl_intensity, SpitzLCDTG), | |
1080 | VMSTATE_UINT32(bl_power, SpitzLCDTG), | |
1081 | VMSTATE_END_OF_LIST(), | |
1082 | } | |
1083 | }; | |
1084 | ||
a984a69e | 1085 | static SSISlaveInfo spitz_lcdtg_info = { |
074f2fff GH |
1086 | .qdev.name = "spitz-lcdtg", |
1087 | .qdev.size = sizeof(SpitzLCDTG), | |
43842120 | 1088 | .qdev.vmsd = &vmstate_spitz_lcdtg_regs, |
a984a69e PB |
1089 | .init = spitz_lcdtg_init, |
1090 | .transfer = spitz_lcdtg_transfer | |
1091 | }; | |
1092 | ||
1093 | static void spitz_register_devices(void) | |
1094 | { | |
074f2fff GH |
1095 | ssi_register_slave(&corgi_ssp_info); |
1096 | ssi_register_slave(&spitz_lcdtg_info); | |
34f9f0b5 | 1097 | sysbus_register_withprop(&sl_nand_info); |
a984a69e PB |
1098 | } |
1099 | ||
1100 | device_init(spitz_register_devices) |