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Convert PXA2xx GPIOs and SCOOP GPIOs to a qemu_irq based api (similar to omap, max731...
[qemu.git] / hw / spitz.c
CommitLineData
b00052e4
AZ		 1/*
2 * PXA270-based Clamshell PDA platforms.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GNU GPL v2.
8 */
9
10#include "vl.h"
11
12#define spitz_printf(format, ...) \
13 fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
14#undef REG_FMT
444ce241
FB		 15#if TARGET_PHYS_ADDR_BITS == 32
16#define REG_FMT "0x%02x"
17#else
b00052e4 18#define REG_FMT "0x%02lx"
444ce241 19#endif
b00052e4
AZ		 20
21/* Spitz Flash */
22#define FLASH_BASE 0x0c000000
23#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
24#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
25#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
26#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
27#define FLASH_ECCCLRR 0x10 /* Clear ECC */
28#define FLASH_FLASHIO 0x14 /* Flash I/O */
29#define FLASH_FLASHCTL 0x18 /* Flash Control */
30
31#define FLASHCTL_CE0 (1 << 0)
32#define FLASHCTL_CLE (1 << 1)
33#define FLASHCTL_ALE (1 << 2)
34#define FLASHCTL_WP (1 << 3)
35#define FLASHCTL_CE1 (1 << 4)
36#define FLASHCTL_RYBY (1 << 5)
37#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
38
39struct sl_nand_s {
40 target_phys_addr_t target_base;
41 struct nand_flash_s *nand;
42 uint8_t ctl;
43 struct ecc_state_s ecc;
44};
45
46static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
47{
48 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
49 int ryby;
50 addr -= s->target_base;
51
52 switch (addr) {
53#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
54 case FLASH_ECCLPLB:
55 return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
56 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
57
58#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
59 case FLASH_ECCLPUB:
60 return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
61 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
62
63 case FLASH_ECCCP:
64 return s->ecc.cp;
65
66 case FLASH_ECCCNTR:
67 return s->ecc.count & 0xff;
68
69 case FLASH_FLASHCTL:
70 nand_getpins(s->nand, &ryby);
71 if (ryby)
72 return s->ctl | FLASHCTL_RYBY;
73 else
74 return s->ctl;
75
76 case FLASH_FLASHIO:
77 return ecc_digest(&s->ecc, nand_getio(s->nand));
78
79 default:
80 spitz_printf("Bad register offset " REG_FMT "\n", addr);
81 }
82 return 0;
83}
84
a5236105
AZ		 85static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
86{
87 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
88 addr -= s->target_base;
89
90 if (addr == FLASH_FLASHIO)
91 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
92 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
93
94 return sl_readb(opaque, addr);
95}
96
b00052e4
AZ		 97static void sl_writeb(void *opaque, target_phys_addr_t addr,
98 uint32_t value)
99{
100 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
101 addr -= s->target_base;
102
103 switch (addr) {
104 case FLASH_ECCCLRR:
105 /* Value is ignored. */
106 ecc_reset(&s->ecc);
107 break;
108
109 case FLASH_FLASHCTL:
110 s->ctl = value & 0xff & ~FLASHCTL_RYBY;
111 nand_setpins(s->nand,
112 s->ctl & FLASHCTL_CLE,
113 s->ctl & FLASHCTL_ALE,
114 s->ctl & FLASHCTL_NCE,
115 s->ctl & FLASHCTL_WP,
116 0);
117 break;
118
119 case FLASH_FLASHIO:
120 nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
121 break;
122
123 default:
124 spitz_printf("Bad register offset " REG_FMT "\n", addr);
125 }
126}
127
aa941b94
AZ		 128static void sl_save(QEMUFile *f, void *opaque)
129{
130 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
131
132 qemu_put_8s(f, &s->ctl);
133 ecc_put(f, &s->ecc);
134}
135
136static int sl_load(QEMUFile *f, void *opaque, int version_id)
137{
138 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
139
140 qemu_get_8s(f, &s->ctl);
141 ecc_get(f, &s->ecc);
142
143 return 0;
144}
145
b00052e4
AZ		 146enum {
147 FLASH_128M,
148 FLASH_1024M,
149};
150
151static void sl_flash_register(struct pxa2xx_state_s *cpu, int size)
152{
153 int iomemtype;
154 struct sl_nand_s *s;
155 CPUReadMemoryFunc *sl_readfn[] = {
156 sl_readb,
157 sl_readb,
a5236105 158 sl_readl,
b00052e4
AZ		 159 };
160 CPUWriteMemoryFunc *sl_writefn[] = {
161 sl_writeb,
162 sl_writeb,
163 sl_writeb,
164 };
165
166 s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s));
167 s->target_base = FLASH_BASE;
168 s->ctl = 0;
169 if (size == FLASH_128M)
170 s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
171 else if (size == FLASH_1024M)
172 s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
173
174 iomemtype = cpu_register_io_memory(0, sl_readfn,
175 sl_writefn, s);
176 cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
aa941b94
AZ		 177
178 register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
b00052e4
AZ		 179}
180
181/* Spitz Keyboard */
182
183#define SPITZ_KEY_STROBE_NUM 11
184#define SPITZ_KEY_SENSE_NUM 7
185
186static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
187 12, 17, 91, 34, 36, 38, 39
188};
189
190static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
191 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
192};
193
194/* Eighth additional row maps the special keys */
195static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
196 { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
197 { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
198 { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
199 { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
200 { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
2b76bdc9
AZ		 201 { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
202 { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
b00052e4
AZ		 203 { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
204};
205
206#define SPITZ_GPIO_AK_INT 13 /* Remote control */
207#define SPITZ_GPIO_SYNC 16 /* Sync button */
208#define SPITZ_GPIO_ON_KEY 95 /* Power button */
209#define SPITZ_GPIO_SWA 97 /* Lid */
210#define SPITZ_GPIO_SWB 96 /* Tablet mode */
211
212/* The special buttons are mapped to unused keys */
213static const int spitz_gpiomap[5] = {
214 SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
215 SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
216};
217static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
218
219struct spitz_keyboard_s {
38641a52
AZ		 220 qemu_irq sense[SPITZ_KEY_SENSE_NUM];
221 qemu_irq *strobe;
222 qemu_irq gpiomap[5];
b00052e4
AZ		 223 int keymap[0x80];
224 uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
225 uint16_t strobe_state;
226 uint16_t sense_state;
227
228 uint16_t pre_map[0x100];
229 uint16_t modifiers;
230 uint16_t imodifiers;
231 uint8_t fifo[16];
232 int fifopos, fifolen;
233 QEMUTimer *kbdtimer;
234};
235
236static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s)
237{
238 int i;
239 uint16_t strobe, sense = 0;
240 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
241 strobe = s->keyrow[i] & s->strobe_state;
242 if (strobe) {
243 sense |= 1 << i;
244 if (!(s->sense_state & (1 << i)))
38641a52 245 qemu_irq_raise(s->sense[i]);
b00052e4 246 } else if (s->sense_state & (1 << i))
38641a52 247 qemu_irq_lower(s->sense[i]);
b00052e4
AZ		 248 }
249
250 s->sense_state = sense;
251}
252
38641a52 253static void spitz_keyboard_strobe(void *opaque, int line, int level)
b00052e4 254{
38641a52
AZ		 255 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
256
257 if (level)
258 s->strobe_state |= 1 << line;
259 else
260 s->strobe_state &= ~(1 << line);
261 spitz_keyboard_sense_update(s);
b00052e4
AZ		 262}
263
264static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
265{
266 int spitz_keycode = s->keymap[keycode & 0x7f];
267 if (spitz_keycode == -1)
268 return;
269
270 /* Handle the additional keys */
271 if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
38641a52 272 qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^
b00052e4
AZ		 273 spitz_gpio_invert[spitz_keycode & 0xf]);
274 return;
275 }
276
277 if (keycode & 0x80)
278 s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
279 else
280 s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
281
282 spitz_keyboard_sense_update(s);
283}
284
285#define SHIFT (1 << 7)
286#define CTRL (1 << 8)
287#define FN (1 << 9)
288
289#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
290
291static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode)
292{
293 uint16_t code;
294 int mapcode;
295 switch (keycode) {
296 case 0x2a: /* Left Shift */
297 s->modifiers |= 1;
298 break;
299 case 0xaa:
300 s->modifiers &= ~1;
301 break;
302 case 0x36: /* Right Shift */
303 s->modifiers |= 2;
304 break;
305 case 0xb6:
306 s->modifiers &= ~2;
307 break;
308 case 0x1d: /* Control */
309 s->modifiers |= 4;
310 break;
311 case 0x9d:
312 s->modifiers &= ~4;
313 break;
314 case 0x38: /* Alt */
315 s->modifiers |= 8;
316 break;
317 case 0xb8:
318 s->modifiers &= ~8;
319 break;
320 }
321
322 code = s->pre_map[mapcode = ((s->modifiers & 3) ?
323 (keycode | SHIFT) :
324 (keycode & ~SHIFT))];
325
326 if (code != mapcode) {
327#if 0
328 if ((code & SHIFT) && !(s->modifiers & 1))
329 QUEUE_KEY(0x2a | (keycode & 0x80));
330 if ((code & CTRL ) && !(s->modifiers & 4))
331 QUEUE_KEY(0x1d | (keycode & 0x80));
332 if ((code & FN ) && !(s->modifiers & 8))
333 QUEUE_KEY(0x38 | (keycode & 0x80));
334 if ((code & FN ) && (s->modifiers & 1))
335 QUEUE_KEY(0x2a | (~keycode & 0x80));
336 if ((code & FN ) && (s->modifiers & 2))
337 QUEUE_KEY(0x36 | (~keycode & 0x80));
338#else
339 if (keycode & 0x80) {
340 if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
341 QUEUE_KEY(0x2a | 0x80);
342 if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
343 QUEUE_KEY(0x1d | 0x80);
344 if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
345 QUEUE_KEY(0x38 | 0x80);
346 if ((s->imodifiers & 0x10) && (s->modifiers & 1))
347 QUEUE_KEY(0x2a);
348 if ((s->imodifiers & 0x20) && (s->modifiers & 2))
349 QUEUE_KEY(0x36);
350 s->imodifiers = 0;
351 } else {
352 if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
353 QUEUE_KEY(0x2a);
354 s->imodifiers |= 1;
355 }
356 if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
357 QUEUE_KEY(0x1d);
358 s->imodifiers |= 4;
359 }
360 if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
361 QUEUE_KEY(0x38);
362 s->imodifiers |= 8;
363 }
364 if ((code & FN ) && (s->modifiers & 1) &&
365 !(s->imodifiers & 0x10)) {
366 QUEUE_KEY(0x2a | 0x80);
367 s->imodifiers |= 0x10;
368 }
369 if ((code & FN ) && (s->modifiers & 2) &&
370 !(s->imodifiers & 0x20)) {
371 QUEUE_KEY(0x36 | 0x80);
372 s->imodifiers |= 0x20;
373 }
374 }
375#endif
376 }
377
378 QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
379}
380
381static void spitz_keyboard_tick(void *opaque)
382{
383 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
384
385 if (s->fifolen) {
386 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
387 s->fifolen --;
388 if (s->fifopos >= 16)
389 s->fifopos = 0;
390 }
391
392 qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
393}
394
395static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s)
396{
397 int i;
398 for (i = 0; i < 0x100; i ++)
399 s->pre_map[i] = i;
400 s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
401 s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
402 s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
403 s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
404 s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
405 s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
406 s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
407 s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
408 s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
409 s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
410 s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
411 s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
412 s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
413 s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
414 s->pre_map[0x0d ] = 0x12 | FN; /* equal */
415 s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
416 s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
417 s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
2b76bdc9
AZ		 418 s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
419 s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
b00052e4
AZ		 420 s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
421 s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
422 s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
423 s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
424 s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
425 s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
2b76bdc9 426 s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
b00052e4 427 s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
2b76bdc9 428 s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
b00052e4
AZ		 429 s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
430 s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
431 s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
432
433 s->modifiers = 0;
434 s->imodifiers = 0;
435 s->fifopos = 0;
436 s->fifolen = 0;
437 s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
438 spitz_keyboard_tick(s);
439}
440
441#undef SHIFT
442#undef CTRL
443#undef FN
444
aa941b94
AZ		 445static void spitz_keyboard_save(QEMUFile *f, void *opaque)
446{
447 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
448 int i;
449
450 qemu_put_be16s(f, &s->sense_state);
451 qemu_put_be16s(f, &s->strobe_state);
452 for (i = 0; i < 5; i ++)
453 qemu_put_byte(f, spitz_gpio_invert[i]);
454}
455
456static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
457{
458 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
459 int i;
460
461 qemu_get_be16s(f, &s->sense_state);
462 qemu_get_be16s(f, &s->strobe_state);
463 for (i = 0; i < 5; i ++)
464 spitz_gpio_invert[i] = qemu_get_byte(f);
465
466 /* Release all pressed keys */
467 memset(s->keyrow, 0, sizeof(s->keyrow));
468 spitz_keyboard_sense_update(s);
469 s->modifiers = 0;
470 s->imodifiers = 0;
471 s->fifopos = 0;
472 s->fifolen = 0;
473
474 return 0;
475}
476
b00052e4
AZ		 477static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
478{
479 int i, j;
480 struct spitz_keyboard_s *s;
481
482 s = (struct spitz_keyboard_s *)
483 qemu_mallocz(sizeof(struct spitz_keyboard_s));
484 memset(s, 0, sizeof(struct spitz_keyboard_s));
b00052e4
AZ		 485
486 for (i = 0; i < 0x80; i ++)
487 s->keymap[i] = -1;
488 for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
489 for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
490 if (spitz_keymap[i][j] != -1)
491 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
492
38641a52
AZ		 493 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
494 s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]];
495
496 for (i = 0; i < 5; i ++)
497 s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]];
498
499 s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s,
500 SPITZ_KEY_STROBE_NUM);
b00052e4 501 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
38641a52 502 pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]);
b00052e4
AZ		 503
504 spitz_keyboard_pre_map(s);
505 qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
aa941b94
AZ		 506
507 register_savevm("spitz_keyboard", 0, 0,
508 spitz_keyboard_save, spitz_keyboard_load, s);
b00052e4
AZ		 509}
510
511/* SCOOP devices */
512
513struct scoop_info_s {
514 target_phys_addr_t target_base;
38641a52
AZ		 515 qemu_irq handler[16];
516 qemu_irq *in;
b00052e4
AZ		 517 uint16_t status;
518 uint16_t power;
519 uint32_t gpio_level;
520 uint32_t gpio_dir;
521 uint32_t prev_level;
b00052e4
AZ		 522
523 uint16_t mcr;
524 uint16_t cdr;
525 uint16_t ccr;
526 uint16_t irr;
527 uint16_t imr;
528 uint16_t isr;
529 uint16_t gprr;
530};
531
532#define SCOOP_MCR 0x00
533#define SCOOP_CDR 0x04
534#define SCOOP_CSR 0x08
535#define SCOOP_CPR 0x0c
536#define SCOOP_CCR 0x10
537#define SCOOP_IRR_IRM 0x14
538#define SCOOP_IMR 0x18
539#define SCOOP_ISR 0x1c
540#define SCOOP_GPCR 0x20
541#define SCOOP_GPWR 0x24
542#define SCOOP_GPRR 0x28
543
544static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
545 uint32_t level, diff;
546 int bit;
547 level = s->gpio_level & s->gpio_dir;
548
549 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
550 bit = ffs(diff) - 1;
38641a52 551 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
b00052e4
AZ		 552 }
553
554 s->prev_level = level;
555}
556
557static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
558{
559 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
560 addr -= s->target_base;
561
562 switch (addr) {
563 case SCOOP_MCR:
564 return s->mcr;
565 case SCOOP_CDR:
566 return s->cdr;
567 case SCOOP_CSR:
568 return s->status;
569 case SCOOP_CPR:
570 return s->power;
571 case SCOOP_CCR:
572 return s->ccr;
573 case SCOOP_IRR_IRM:
574 return s->irr;
575 case SCOOP_IMR:
576 return s->imr;
577 case SCOOP_ISR:
578 return s->isr;
579 case SCOOP_GPCR:
580 return s->gpio_dir;
581 case SCOOP_GPWR:
582 return s->gpio_level;
583 case SCOOP_GPRR:
584 return s->gprr;
585 default:
586 spitz_printf("Bad register offset " REG_FMT "\n", addr);
587 }
588
589 return 0;
590}
591
592static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
593{
594 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
595 addr -= s->target_base;
596 value &= 0xffff;
597
598 switch (addr) {
599 case SCOOP_MCR:
600 s->mcr = value;
601 break;
602 case SCOOP_CDR:
603 s->cdr = value;
604 break;
605 case SCOOP_CPR:
606 s->power = value;
607 if (value & 0x80)
608 s->power |= 0x8040;
609 break;
610 case SCOOP_CCR:
611 s->ccr = value;
612 break;
613 case SCOOP_IRR_IRM:
614 s->irr = value;
615 break;
616 case SCOOP_IMR:
617 s->imr = value;
618 break;
619 case SCOOP_ISR:
620 s->isr = value;
621 break;
622 case SCOOP_GPCR:
623 s->gpio_dir = value;
624 scoop_gpio_handler_update(s);
625 break;
626 case SCOOP_GPWR:
627 s->gpio_level = value & s->gpio_dir;
628 scoop_gpio_handler_update(s);
629 break;
630 case SCOOP_GPRR:
631 s->gprr = value;
632 break;
633 default:
634 spitz_printf("Bad register offset " REG_FMT "\n", addr);
635 }
636}
637
638CPUReadMemoryFunc *scoop_readfn[] = {
639 scoop_readb,
640 scoop_readb,
641 scoop_readb,
642};
643CPUWriteMemoryFunc *scoop_writefn[] = {
644 scoop_writeb,
645 scoop_writeb,
646 scoop_writeb,
647};
648
38641a52 649static void scoop_gpio_set(void *opaque, int line, int level)
b00052e4 650{
38641a52 651 struct scoop_info_s *s = (struct scoop_info_s *) s;
b00052e4
AZ		 652
653 if (level)
654 s->gpio_level |= (1 << line);
655 else
656 s->gpio_level &= ~(1 << line);
657}
658
38641a52
AZ		 659static inline qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
660{
661 return s->in;
662}
663
664static inline void scoop_gpio_out_set(struct scoop_info_s *s, int line,
665 qemu_irq handler) {
b00052e4
AZ		 666 if (line >= 16) {
667 spitz_printf("No GPIO pin %i\n", line);
668 return;
669 }
670
38641a52 671 s->handler[line] = handler;
b00052e4
AZ		 672}
673
aa941b94
AZ		 674static void scoop_save(QEMUFile *f, void *opaque)
675{
676 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
677 qemu_put_be16s(f, &s->status);
678 qemu_put_be16s(f, &s->power);
679 qemu_put_be32s(f, &s->gpio_level);
680 qemu_put_be32s(f, &s->gpio_dir);
681 qemu_put_be32s(f, &s->prev_level);
682 qemu_put_be16s(f, &s->mcr);
683 qemu_put_be16s(f, &s->cdr);
684 qemu_put_be16s(f, &s->ccr);
685 qemu_put_be16s(f, &s->irr);
686 qemu_put_be16s(f, &s->imr);
687 qemu_put_be16s(f, &s->isr);
688 qemu_put_be16s(f, &s->gprr);
689}
690
691static int scoop_load(QEMUFile *f, void *opaque, int version_id)
692{
693 struct scoop_info_s *s = (struct scoop_info_s *) opaque;
694 qemu_get_be16s(f, &s->status);
695 qemu_get_be16s(f, &s->power);
696 qemu_get_be32s(f, &s->gpio_level);
697 qemu_get_be32s(f, &s->gpio_dir);
698 qemu_get_be32s(f, &s->prev_level);
699 qemu_get_be16s(f, &s->mcr);
700 qemu_get_be16s(f, &s->cdr);
701 qemu_get_be16s(f, &s->ccr);
702 qemu_get_be16s(f, &s->irr);
703 qemu_get_be16s(f, &s->imr);
704 qemu_get_be16s(f, &s->isr);
705 qemu_get_be16s(f, &s->gprr);
706
707 return 0;
708}
709
b00052e4
AZ		 710static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu,
711 int count) {
712 int iomemtype;
713 struct scoop_info_s *s;
714
715 s = (struct scoop_info_s *)
716 qemu_mallocz(sizeof(struct scoop_info_s) * 2);
717 memset(s, 0, sizeof(struct scoop_info_s) * count);
718 s[0].target_base = 0x10800000;
719 s[1].target_base = 0x08800040;
720
721 /* Ready */
722 s[0].status = 0x02;
723 s[1].status = 0x02;
724
38641a52 725 s[0].in = qemu_allocate_irqs(scoop_gpio_set, &s[0], 16);
b00052e4
AZ		 726 iomemtype = cpu_register_io_memory(0, scoop_readfn,
727 scoop_writefn, &s[0]);
187337f8 728 cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype);
aa941b94 729 register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]);
b00052e4
AZ		 730
731 if (count < 2)
732 return s;
733
38641a52 734 s[1].in = qemu_allocate_irqs(scoop_gpio_set, &s[1], 16);
b00052e4
AZ		 735 iomemtype = cpu_register_io_memory(0, scoop_readfn,
736 scoop_writefn, &s[1]);
187337f8 737 cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype);
aa941b94 738 register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]);
b00052e4
AZ		 739
740 return s;
741}
742
743/* LCD backlight controller */
744
745#define LCDTG_RESCTL 0x00
746#define LCDTG_PHACTRL 0x01
747#define LCDTG_DUTYCTRL 0x02
748#define LCDTG_POWERREG0 0x03
749#define LCDTG_POWERREG1 0x04
750#define LCDTG_GPOR3 0x05
751#define LCDTG_PICTRL 0x06
752#define LCDTG_POLCTRL 0x07
753
754static int bl_intensity, bl_power;
755
756static void spitz_bl_update(struct pxa2xx_state_s *s)
757{
758 if (bl_power && bl_intensity)
759 spitz_printf("LCD Backlight now at %i/63\n", bl_intensity);
760 else
761 spitz_printf("LCD Backlight now off\n");
762}
763
38641a52 764static inline void spitz_bl_bit5(void *opaque, int line, int level)
b00052e4
AZ		 765{
766 int prev = bl_intensity;
767
768 if (level)
769 bl_intensity &= ~0x20;
770 else
771 bl_intensity |= 0x20;
772
773 if (bl_power && prev != bl_intensity)
774 spitz_bl_update((struct pxa2xx_state_s *) opaque);
775}
776
38641a52 777static inline void spitz_bl_power(void *opaque, int line, int level)
b00052e4
AZ		 778{
779 bl_power = !!level;
780 spitz_bl_update((struct pxa2xx_state_s *) opaque);
781}
782
783static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
784{
785 int addr, value;
786 addr = cmd >> 5;
787 value = cmd & 0x1f;
788
789 switch (addr) {
790 case LCDTG_RESCTL:
791 if (value)
792 spitz_printf("LCD in QVGA mode\n");
793 else
794 spitz_printf("LCD in VGA mode\n");
795 break;
796
797 case LCDTG_DUTYCTRL:
798 bl_intensity &= ~0x1f;
799 bl_intensity |= value;
800 if (bl_power)
801 spitz_bl_update((struct pxa2xx_state_s *) opaque);
802 break;
803
804 case LCDTG_POWERREG0:
805 /* Set common voltage to M62332FP */
806 break;
807 }
808}
809
810/* SSP devices */
811
812#define CORGI_SSP_PORT 2
813
814#define SPITZ_GPIO_LCDCON_CS 53
815#define SPITZ_GPIO_ADS7846_CS 14
816#define SPITZ_GPIO_MAX1111_CS 20
817#define SPITZ_GPIO_TP_INT 11
818
819static int lcd_en, ads_en, max_en;
820static struct max111x_s *max1111;
821static struct ads7846_state_s *ads7846;
822
823/* "Demux" the signal based on current chipselect */
824static uint32_t corgi_ssp_read(void *opaque)
825{
826 if (lcd_en)
827 return 0;
828 if (ads_en)
829 return ads7846_read(ads7846);
830 if (max_en)
831 return max111x_read(max1111);
832 return 0;
833}
834
835static void corgi_ssp_write(void *opaque, uint32_t value)
836{
837 if (lcd_en)
838 spitz_lcdtg_dac_put(opaque, value);
839 if (ads_en)
840 ads7846_write(ads7846, value);
841 if (max_en)
842 max111x_write(max1111, value);
843}
844
38641a52 845static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
b00052e4 846{
38641a52
AZ		 847 switch (line) {
848 case 0:
b00052e4 849 lcd_en = !level;
38641a52
AZ		 850 break;
851 case 1:
b00052e4 852 ads_en = !level;
38641a52
AZ		 853 break;
854 case 2:
b00052e4 855 max_en = !level;
38641a52
AZ		 856 break;
857 }
b00052e4
AZ		 858}
859
860#define MAX1111_BATT_VOLT 1
861#define MAX1111_BATT_TEMP 2
862#define MAX1111_ACIN_VOLT 3
863
864#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
865#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
866#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
867
38641a52 868static void spitz_adc_temp_on(void *opaque, int line, int level)
b00052e4
AZ		 869{
870 if (!max1111)
871 return;
872
873 if (level)
874 max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
875 else
876 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
877}
878
aa941b94
AZ		 879static void spitz_ssp_save(QEMUFile *f, void *opaque)
880{
881 qemu_put_be32(f, lcd_en);
882 qemu_put_be32(f, ads_en);
883 qemu_put_be32(f, max_en);
884 qemu_put_be32(f, bl_intensity);
885 qemu_put_be32(f, bl_power);
886}
887
888static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
889{
890 lcd_en = qemu_get_be32(f);
891 ads_en = qemu_get_be32(f);
892 max_en = qemu_get_be32(f);
893 bl_intensity = qemu_get_be32(f);
894 bl_power = qemu_get_be32(f);
895
896 return 0;
897}
898
b00052e4
AZ		 899static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
900{
38641a52
AZ		 901 qemu_irq *chipselects;
902
b00052e4
AZ		 903 lcd_en = ads_en = max_en = 0;
904
38641a52 905 ads7846 = ads7846_init(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]);
b00052e4
AZ		 906
907 max1111 = max1111_init(0);
908 max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
909 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
910 max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
911
912 pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
913 corgi_ssp_write, cpu);
914
38641a52
AZ		 915 chipselects = qemu_allocate_irqs(corgi_ssp_gpio_cs, cpu, 3);
916 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, chipselects[0]);
917 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, chipselects[1]);
918 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, chipselects[2]);
b00052e4
AZ		 919
920 bl_intensity = 0x20;
921 bl_power = 0;
aa941b94
AZ		 922
923 register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu);
b00052e4
AZ		 924}
925
926/* CF Microdrive */
927
928static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu)
929{
930 struct pcmcia_card_s *md;
931 BlockDriverState *bs = bs_table[0];
932
933 if (bs && bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
934 md = dscm1xxxx_init(bs);
bf5ee248 935 pxa2xx_pcmcia_attach(cpu->pcmcia[1], md);
b00052e4
AZ		 936 }
937}
938
adb86c37
AZ		 939/* Wm8750 and Max7310 on I2C */
940
941#define AKITA_MAX_ADDR 0x18
611d7189
AZ		 942#define SPITZ_WM_ADDRL 0x1b
943#define SPITZ_WM_ADDRH 0x1a
adb86c37
AZ		 944
945#define SPITZ_GPIO_WM 5
946
947#ifdef HAS_AUDIO
38641a52 948static void spitz_wm8750_addr(void *opaque, int line, int level)
adb86c37
AZ		 949{
950 i2c_slave *wm = (i2c_slave *) opaque;
951 if (level)
952 i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
953 else
954 i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
955}
956#endif
957
958static void spitz_i2c_setup(struct pxa2xx_state_s *cpu)
959{
960 /* Attach the CPU on one end of our I2C bus. */
961 i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
962
963#ifdef HAS_AUDIO
964 AudioState *audio;
965 i2c_slave *wm;
966
967 audio = AUD_init();
968 if (!audio)
969 return;
970 /* Attach a WM8750 to the bus */
971 wm = wm8750_init(bus, audio);
972
38641a52
AZ		 973 spitz_wm8750_addr(wm, 0, 0);
974 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
975 qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
adb86c37
AZ		 976 /* .. and to the sound interface. */
977 cpu->i2s->opaque = wm;
978 cpu->i2s->codec_out = wm8750_dac_dat;
979 cpu->i2s->codec_in = wm8750_adc_dat;
980 wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
981#endif
982}
983
984static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu)
985{
986 /* Attach a Max7310 to Akita I2C bus. */
987 i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
988 AKITA_MAX_ADDR);
989}
990
b00052e4
AZ		 991/* Other peripherals */
992
38641a52 993static void spitz_out_switch(void *opaque, int line, int level)
b00052e4 994{
38641a52
AZ		 995 switch (line) {
996 case 0:
997 spitz_printf("Charging %s.\n", level ? "off" : "on");
998 break;
999 case 1:
1000 spitz_printf("Discharging %s.\n", level ? "on" : "off");
1001 break;
1002 case 2:
1003 spitz_printf("Green LED %s.\n", level ? "on" : "off");
1004 break;
1005 case 3:
1006 spitz_printf("Orange LED %s.\n", level ? "on" : "off");
1007 break;
1008 case 4:
1009 spitz_bl_bit5(opaque, line, level);
1010 break;
1011 case 5:
1012 spitz_bl_power(opaque, line, level);
1013 break;
1014 case 6:
1015 spitz_adc_temp_on(opaque, line, level);
1016 break;
1017 }
b00052e4
AZ		 1018}
1019
1020#define SPITZ_SCP_LED_GREEN 1
1021#define SPITZ_SCP_JK_B 2
1022#define SPITZ_SCP_CHRG_ON 3
1023#define SPITZ_SCP_MUTE_L 4
1024#define SPITZ_SCP_MUTE_R 5
1025#define SPITZ_SCP_CF_POWER 6
1026#define SPITZ_SCP_LED_ORANGE 7
1027#define SPITZ_SCP_JK_A 8
1028#define SPITZ_SCP_ADC_TEMP_ON 9
1029#define SPITZ_SCP2_IR_ON 1
1030#define SPITZ_SCP2_AKIN_PULLUP 2
1031#define SPITZ_SCP2_BACKLIGHT_CONT 7
1032#define SPITZ_SCP2_BACKLIGHT_ON 8
1033#define SPITZ_SCP2_MIC_BIAS 9
1034
1035static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
1036 struct scoop_info_s *scp, int num)
1037{
38641a52
AZ		 1038 qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
1039
1040 scoop_gpio_out_set(&scp[0], SPITZ_SCP_CHRG_ON, outsignals[0]);
1041 scoop_gpio_out_set(&scp[0], SPITZ_SCP_JK_B, outsignals[1]);
1042 scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_GREEN, outsignals[2]);
1043 scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_ORANGE, outsignals[3]);
b00052e4
AZ		 1044
1045 if (num >= 2) {
38641a52
AZ		 1046 scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
1047 scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
b00052e4
AZ		 1048 }
1049
38641a52 1050 scoop_gpio_out_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
b00052e4
AZ		 1051}
1052
1053#define SPITZ_GPIO_HSYNC 22
1054#define SPITZ_GPIO_SD_DETECT 9
1055#define SPITZ_GPIO_SD_WP 81
1056#define SPITZ_GPIO_ON_RESET 89
1057#define SPITZ_GPIO_BAT_COVER 90
1058#define SPITZ_GPIO_CF1_IRQ 105
1059#define SPITZ_GPIO_CF1_CD 94
1060#define SPITZ_GPIO_CF2_IRQ 106
1061#define SPITZ_GPIO_CF2_CD 93
1062
38641a52 1063static int spitz_hsync;
b00052e4 1064
38641a52 1065static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
b00052e4
AZ		 1066{
1067 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
38641a52 1068 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
b00052e4
AZ		 1069 spitz_hsync ^= 1;
1070}
1071
1072static void spitz_mmc_coverswitch_change(void *opaque, int in)
1073{
1074 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
38641a52 1075 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT], in);
b00052e4
AZ		 1076}
1077
1078static void spitz_mmc_writeprotect_change(void *opaque, int wp)
1079{
1080 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
38641a52 1081 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP], wp);
b00052e4
AZ		 1082}
1083
1084static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
1085{
38641a52 1086 qemu_irq lcd_hsync;
b00052e4
AZ		 1087 /*
1088 * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
1089 * read to satisfy broken guests that poll-wait for hsync.
1090 * Simulating a real hsync event would be less practical and
1091 * wouldn't guarantee that a guest ever exits the loop.
1092 */
1093 spitz_hsync = 0;
38641a52
AZ		 1094 lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
1095 pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
1096 pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
b00052e4
AZ		 1097
1098 /* MMC/SD host */
1099 pxa2xx_mmci_handlers(cpu->mmc, cpu, spitz_mmc_writeprotect_change,
1100 spitz_mmc_coverswitch_change);
1101
1102 /* Battery lock always closed */
38641a52 1103 qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]);
b00052e4
AZ		 1104
1105 /* Handle reset */
38641a52 1106 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
b00052e4
AZ		 1107
1108 /* PCMCIA signals: card's IRQ and Card-Detect */
b00052e4 1109 if (slots >= 1)
38641a52
AZ		 1110 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
1111 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ],
1112 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]);
b00052e4 1113 if (slots >= 2)
38641a52
AZ		 1114 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
1115 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ],
1116 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]);
b00052e4
AZ		 1117
1118 /* Initialise the screen rotation related signals */
1119 spitz_gpio_invert[3] = 0; /* Always open */
1120 if (graphic_rotate) { /* Tablet mode */
1121 spitz_gpio_invert[4] = 0;
1122 } else { /* Portrait mode */
1123 spitz_gpio_invert[4] = 1;
1124 }
38641a52
AZ		 1125 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA],
1126 spitz_gpio_invert[3]);
1127 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB],
1128 spitz_gpio_invert[4]);
b00052e4
AZ		 1129}
1130
1131/* Write the bootloader parameters memory area. */
1132
1133#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
1134
1135struct __attribute__ ((__packed__)) sl_param_info {
1136 uint32_t comadj_keyword;
1137 int32_t comadj;
1138
1139 uint32_t uuid_keyword;
1140 char uuid[16];
1141
1142 uint32_t touch_keyword;
1143 int32_t touch_xp;
1144 int32_t touch_yp;
1145 int32_t touch_xd;
1146 int32_t touch_yd;
1147
1148 uint32_t adadj_keyword;
1149 int32_t adadj;
1150
1151 uint32_t phad_keyword;
1152 int32_t phadadj;
1153} spitz_bootparam = {
1154 .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
1155 .comadj = 125,
1156 .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
1157 .uuid = { -1 },
1158 .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
1159 .touch_xp = -1,
1160 .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
1161 .adadj = -1,
1162 .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
1163 .phadadj = 0x01,
1164};
1165
1166static void sl_bootparam_write(uint32_t ptr)
1167{
1168 memcpy(phys_ram_base + ptr, &spitz_bootparam,
1169 sizeof(struct sl_param_info));
1170}
1171
1172#define SL_PXA_PARAM_BASE 0xa0000a00
1173
1174/* Board init. */
1175enum spitz_model_e { spitz, akita, borzoi, terrier };
1176
1177static void spitz_common_init(int ram_size, int vga_ram_size,
1178 DisplayState *ds, const char *kernel_filename,
1179 const char *kernel_cmdline, const char *initrd_filename,
4207117c 1180 const char *cpu_model, enum spitz_model_e model, int arm_id)
b00052e4
AZ		 1181{
1182 uint32_t spitz_ram = 0x04000000;
1183 uint32_t spitz_rom = 0x00800000;
1184 struct pxa2xx_state_s *cpu;
1185 struct scoop_info_s *scp;
1186
4207117c
AZ		 1187 if (!cpu_model)
1188 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
b00052e4 1189
d95b2f8d 1190 /* Setup CPU & memory */
a07dec22 1191 if (ram_size < spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE) {
b00052e4 1192 fprintf(stderr, "This platform requires %i bytes of memory\n",
a07dec22 1193 spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE);
b00052e4
AZ		 1194 exit(1);
1195 }
d95b2f8d 1196 cpu = pxa270_init(spitz_ram, ds, cpu_model);
b00052e4
AZ		 1197
1198 sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
1199
d95b2f8d
AZ		 1200 cpu_register_physical_memory(0, spitz_rom,
1201 qemu_ram_alloc(spitz_rom) | IO_MEM_ROM);
b00052e4
AZ		 1202
1203 /* Setup peripherals */
1204 spitz_keyboard_register(cpu);
1205
1206 spitz_ssp_attach(cpu);
1207
1208 scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2);
1209
1210 spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2);
1211
1212 spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
1213
adb86c37
AZ		 1214 spitz_i2c_setup(cpu);
1215
1216 if (model == akita)
1217 spitz_akita_i2c_setup(cpu);
1218
b00052e4 1219 if (model == terrier)
bf5ee248 1220 /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
b00052e4
AZ		 1221 spitz_microdrive_attach(cpu);
1222 else if (model != akita)
bf5ee248 1223 /* A 4.0 GB microdrive is permanently sitting in CF slot 1. */
b00052e4
AZ		 1224 spitz_microdrive_attach(cpu);
1225
1226 /* Setup initial (reset) machine state */
d95b2f8d 1227 cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
b00052e4 1228
d95b2f8d
AZ		 1229 arm_load_kernel(cpu->env, spitz_ram, kernel_filename, kernel_cmdline,
1230 initrd_filename, arm_id, PXA2XX_SDRAM_BASE);
1231 sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);
b00052e4
AZ		 1232}
1233
6ac0e82d
AZ		 1234static void spitz_init(int ram_size, int vga_ram_size,
1235 const char *boot_device, DisplayState *ds,
1236 const char **fd_filename, int snapshot,
b00052e4
AZ		 1237 const char *kernel_filename, const char *kernel_cmdline,
1238 const char *initrd_filename, const char *cpu_model)
1239{
1240 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
4207117c 1241 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
b00052e4
AZ		 1242}
1243
6ac0e82d
AZ		 1244static void borzoi_init(int ram_size, int vga_ram_size,
1245 const char *boot_device, DisplayState *ds,
1246 const char **fd_filename, int snapshot,
b00052e4
AZ		 1247 const char *kernel_filename, const char *kernel_cmdline,
1248 const char *initrd_filename, const char *cpu_model)
1249{
1250 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
4207117c 1251 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
b00052e4
AZ		 1252}
1253
6ac0e82d
AZ		 1254static void akita_init(int ram_size, int vga_ram_size,
1255 const char *boot_device, DisplayState *ds,
1256 const char **fd_filename, int snapshot,
b00052e4
AZ		 1257 const char *kernel_filename, const char *kernel_cmdline,
1258 const char *initrd_filename, const char *cpu_model)
1259{
1260 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
4207117c 1261 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
b00052e4
AZ		 1262}
1263
6ac0e82d
AZ		 1264static void terrier_init(int ram_size, int vga_ram_size,
1265 const char *boot_device, DisplayState *ds,
1266 const char **fd_filename, int snapshot,
b00052e4
AZ		 1267 const char *kernel_filename, const char *kernel_cmdline,
1268 const char *initrd_filename, const char *cpu_model)
1269{
1270 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
4207117c 1271 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
b00052e4
AZ		 1272}
1273
1274QEMUMachine akitapda_machine = {
1275 "akita",
1276 "Akita PDA (PXA270)",
1277 akita_init,
1278};
1279
1280QEMUMachine spitzpda_machine = {
1281 "spitz",
1282 "Spitz PDA (PXA270)",
1283 spitz_init,
1284};
1285
1286QEMUMachine borzoipda_machine = {
1287 "borzoi",
1288 "Borzoi PDA (PXA270)",
1289 borzoi_init,
1290};
1291
1292QEMUMachine terrierpda_machine = {
1293 "terrier",
1294 "Terrier PDA (PXA270)",
1295 terrier_init,
1296};
Qemu copy for testing