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b00052e4
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1/*
2 * PXA270-based Clamshell PDA platforms.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GNU GPL v2.
8 */
9
87ecb68b
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10#include "hw.h"
11#include "pxa.h"
12#include "arm-misc.h"
13#include "sysemu.h"
14#include "pcmcia.h"
15#include "i2c.h"
a984a69e 16#include "ssi.h"
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17#include "flash.h"
18#include "qemu-timer.h"
19#include "devices.h"
e33d8cdb 20#include "sharpsl.h"
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21#include "console.h"
22#include "block.h"
23#include "audio/audio.h"
24#include "boards.h"
2446333c 25#include "blockdev.h"
383d01c6 26#include "sysbus.h"
a6dc4c2d 27#include "exec-memory.h"
b00052e4 28
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29#undef REG_FMT
30#define REG_FMT "0x%02lx"
31
32/* Spitz Flash */
33#define FLASH_BASE 0x0c000000
34#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
35#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
36#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
37#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
38#define FLASH_ECCCLRR 0x10 /* Clear ECC */
39#define FLASH_FLASHIO 0x14 /* Flash I/O */
40#define FLASH_FLASHCTL 0x18 /* Flash Control */
41
42#define FLASHCTL_CE0 (1 << 0)
43#define FLASHCTL_CLE (1 << 1)
44#define FLASHCTL_ALE (1 << 2)
45#define FLASHCTL_WP (1 << 3)
46#define FLASHCTL_CE1 (1 << 4)
47#define FLASHCTL_RYBY (1 << 5)
48#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
49
bc24a225 50typedef struct {
34f9f0b5 51 SysBusDevice busdev;
7cc09e6c 52 MemoryRegion iomem;
d4220389 53 DeviceState *nand;
b00052e4 54 uint8_t ctl;
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DES
55 uint8_t manf_id;
56 uint8_t chip_id;
bc24a225
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57 ECCState ecc;
58} SLNANDState;
b00052e4 59
7cc09e6c 60static uint64_t sl_read(void *opaque, target_phys_addr_t addr, unsigned size)
b00052e4 61{
bc24a225 62 SLNANDState *s = (SLNANDState *) opaque;
b00052e4 63 int ryby;
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64
65 switch (addr) {
66#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
67 case FLASH_ECCLPLB:
68 return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
69 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
70
71#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
72 case FLASH_ECCLPUB:
73 return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
74 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
75
76 case FLASH_ECCCP:
77 return s->ecc.cp;
78
79 case FLASH_ECCCNTR:
80 return s->ecc.count & 0xff;
81
82 case FLASH_FLASHCTL:
83 nand_getpins(s->nand, &ryby);
84 if (ryby)
85 return s->ctl | FLASHCTL_RYBY;
86 else
87 return s->ctl;
88
89 case FLASH_FLASHIO:
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90 if (size == 4) {
91 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
92 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
93 }
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94 return ecc_digest(&s->ecc, nand_getio(s->nand));
95
96 default:
a8b7063b 97 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
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98 }
99 return 0;
100}
101
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102static void sl_write(void *opaque, target_phys_addr_t addr,
103 uint64_t value, unsigned size)
b00052e4 104{
bc24a225 105 SLNANDState *s = (SLNANDState *) opaque;
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106
107 switch (addr) {
108 case FLASH_ECCCLRR:
109 /* Value is ignored. */
110 ecc_reset(&s->ecc);
111 break;
112
113 case FLASH_FLASHCTL:
114 s->ctl = value & 0xff & ~FLASHCTL_RYBY;
115 nand_setpins(s->nand,
116 s->ctl & FLASHCTL_CLE,
117 s->ctl & FLASHCTL_ALE,
118 s->ctl & FLASHCTL_NCE,
119 s->ctl & FLASHCTL_WP,
120 0);
121 break;
122
123 case FLASH_FLASHIO:
124 nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
125 break;
126
127 default:
a8b7063b 128 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
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129 }
130}
131
132enum {
133 FLASH_128M,
134 FLASH_1024M,
135};
136
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137static const MemoryRegionOps sl_ops = {
138 .read = sl_read,
139 .write = sl_write,
140 .endianness = DEVICE_NATIVE_ENDIAN,
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141};
142
bc24a225 143static void sl_flash_register(PXA2xxState *cpu, int size)
b00052e4 144{
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145 DeviceState *dev;
146
147 dev = qdev_create(NULL, "sl-nand");
148
149 qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
150 if (size == FLASH_128M)
151 qdev_prop_set_uint8(dev, "chip_id", 0x73);
152 else if (size == FLASH_1024M)
153 qdev_prop_set_uint8(dev, "chip_id", 0xf1);
154
155 qdev_init_nofail(dev);
156 sysbus_mmio_map(sysbus_from_qdev(dev), 0, FLASH_BASE);
157}
158
159static int sl_nand_init(SysBusDevice *dev) {
bc24a225 160 SLNANDState *s;
522f253c 161 DriveInfo *nand;
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162
163 s = FROM_SYSBUS(SLNANDState, dev);
164
b00052e4 165 s->ctl = 0;
522f253c
PM
166 nand = drive_get(IF_MTD, 0, 0);
167 s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id);
b00052e4 168
7cc09e6c 169 memory_region_init_io(&s->iomem, &sl_ops, s, "sl", 0x40);
750ecd44 170 sysbus_init_mmio(dev, &s->iomem);
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171
172 return 0;
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173}
174
175/* Spitz Keyboard */
176
177#define SPITZ_KEY_STROBE_NUM 11
178#define SPITZ_KEY_SENSE_NUM 7
179
180static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
181 12, 17, 91, 34, 36, 38, 39
182};
183
184static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
185 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
186};
187
188/* Eighth additional row maps the special keys */
189static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
190 { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
191 { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
192 { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
193 { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
194 { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
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195 { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
196 { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
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197 { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
198};
199
200#define SPITZ_GPIO_AK_INT 13 /* Remote control */
201#define SPITZ_GPIO_SYNC 16 /* Sync button */
202#define SPITZ_GPIO_ON_KEY 95 /* Power button */
203#define SPITZ_GPIO_SWA 97 /* Lid */
204#define SPITZ_GPIO_SWB 96 /* Tablet mode */
205
206/* The special buttons are mapped to unused keys */
207static const int spitz_gpiomap[5] = {
208 SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
209 SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
210};
b00052e4 211
bc24a225 212typedef struct {
7ef4227b 213 SysBusDevice busdev;
38641a52 214 qemu_irq sense[SPITZ_KEY_SENSE_NUM];
38641a52 215 qemu_irq gpiomap[5];
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216 int keymap[0x80];
217 uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
218 uint16_t strobe_state;
219 uint16_t sense_state;
220
221 uint16_t pre_map[0x100];
222 uint16_t modifiers;
223 uint16_t imodifiers;
224 uint8_t fifo[16];
225 int fifopos, fifolen;
226 QEMUTimer *kbdtimer;
bc24a225 227} SpitzKeyboardState;
b00052e4 228
bc24a225 229static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
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230{
231 int i;
232 uint16_t strobe, sense = 0;
233 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
234 strobe = s->keyrow[i] & s->strobe_state;
235 if (strobe) {
236 sense |= 1 << i;
237 if (!(s->sense_state & (1 << i)))
38641a52 238 qemu_irq_raise(s->sense[i]);
b00052e4 239 } else if (s->sense_state & (1 << i))
38641a52 240 qemu_irq_lower(s->sense[i]);
b00052e4
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241 }
242
243 s->sense_state = sense;
244}
245
38641a52 246static void spitz_keyboard_strobe(void *opaque, int line, int level)
b00052e4 247{
bc24a225 248 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
38641a52
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249
250 if (level)
251 s->strobe_state |= 1 << line;
252 else
253 s->strobe_state &= ~(1 << line);
254 spitz_keyboard_sense_update(s);
b00052e4
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255}
256
bc24a225 257static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
b00052e4
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258{
259 int spitz_keycode = s->keymap[keycode & 0x7f];
260 if (spitz_keycode == -1)
261 return;
262
263 /* Handle the additional keys */
264 if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
7ef4227b 265 qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80));
b00052e4
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266 return;
267 }
268
269 if (keycode & 0x80)
270 s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
271 else
272 s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
273
274 spitz_keyboard_sense_update(s);
275}
276
277#define SHIFT (1 << 7)
278#define CTRL (1 << 8)
279#define FN (1 << 9)
280
281#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
282
7ef4227b 283static void spitz_keyboard_handler(void *opaque, int keycode)
b00052e4 284{
7ef4227b 285 SpitzKeyboardState *s = opaque;
b00052e4
AZ
286 uint16_t code;
287 int mapcode;
288 switch (keycode) {
289 case 0x2a: /* Left Shift */
290 s->modifiers |= 1;
291 break;
292 case 0xaa:
293 s->modifiers &= ~1;
294 break;
295 case 0x36: /* Right Shift */
296 s->modifiers |= 2;
297 break;
298 case 0xb6:
299 s->modifiers &= ~2;
300 break;
301 case 0x1d: /* Control */
302 s->modifiers |= 4;
303 break;
304 case 0x9d:
305 s->modifiers &= ~4;
306 break;
307 case 0x38: /* Alt */
308 s->modifiers |= 8;
309 break;
310 case 0xb8:
311 s->modifiers &= ~8;
312 break;
313 }
314
315 code = s->pre_map[mapcode = ((s->modifiers & 3) ?
316 (keycode | SHIFT) :
317 (keycode & ~SHIFT))];
318
319 if (code != mapcode) {
320#if 0
321 if ((code & SHIFT) && !(s->modifiers & 1))
322 QUEUE_KEY(0x2a | (keycode & 0x80));
323 if ((code & CTRL ) && !(s->modifiers & 4))
324 QUEUE_KEY(0x1d | (keycode & 0x80));
325 if ((code & FN ) && !(s->modifiers & 8))
326 QUEUE_KEY(0x38 | (keycode & 0x80));
327 if ((code & FN ) && (s->modifiers & 1))
328 QUEUE_KEY(0x2a | (~keycode & 0x80));
329 if ((code & FN ) && (s->modifiers & 2))
330 QUEUE_KEY(0x36 | (~keycode & 0x80));
331#else
332 if (keycode & 0x80) {
333 if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
334 QUEUE_KEY(0x2a | 0x80);
335 if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
336 QUEUE_KEY(0x1d | 0x80);
337 if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
338 QUEUE_KEY(0x38 | 0x80);
339 if ((s->imodifiers & 0x10) && (s->modifiers & 1))
340 QUEUE_KEY(0x2a);
341 if ((s->imodifiers & 0x20) && (s->modifiers & 2))
342 QUEUE_KEY(0x36);
343 s->imodifiers = 0;
344 } else {
345 if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
346 QUEUE_KEY(0x2a);
347 s->imodifiers |= 1;
348 }
349 if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
350 QUEUE_KEY(0x1d);
351 s->imodifiers |= 4;
352 }
353 if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
354 QUEUE_KEY(0x38);
355 s->imodifiers |= 8;
356 }
357 if ((code & FN ) && (s->modifiers & 1) &&
358 !(s->imodifiers & 0x10)) {
359 QUEUE_KEY(0x2a | 0x80);
360 s->imodifiers |= 0x10;
361 }
362 if ((code & FN ) && (s->modifiers & 2) &&
363 !(s->imodifiers & 0x20)) {
364 QUEUE_KEY(0x36 | 0x80);
365 s->imodifiers |= 0x20;
366 }
367 }
368#endif
369 }
370
371 QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
372}
373
374static void spitz_keyboard_tick(void *opaque)
375{
bc24a225 376 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
b00052e4
AZ
377
378 if (s->fifolen) {
379 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
380 s->fifolen --;
381 if (s->fifopos >= 16)
382 s->fifopos = 0;
383 }
384
74475455 385 qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock) +
6ee093c9 386 get_ticks_per_sec() / 32);
b00052e4
AZ
387}
388
bc24a225 389static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
b00052e4
AZ
390{
391 int i;
392 for (i = 0; i < 0x100; i ++)
393 s->pre_map[i] = i;
394 s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
395 s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
396 s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
397 s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
398 s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
399 s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
400 s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
401 s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
402 s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
403 s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
404 s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
405 s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
406 s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
407 s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
408 s->pre_map[0x0d ] = 0x12 | FN; /* equal */
409 s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
410 s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
411 s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
2b76bdc9
AZ
412 s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
413 s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
b00052e4
AZ
414 s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
415 s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
416 s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
417 s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
418 s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
419 s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
2b76bdc9 420 s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
b00052e4 421 s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
2b76bdc9 422 s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
b00052e4
AZ
423 s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
424 s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
425 s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
426
427 s->modifiers = 0;
428 s->imodifiers = 0;
429 s->fifopos = 0;
430 s->fifolen = 0;
b00052e4
AZ
431}
432
433#undef SHIFT
434#undef CTRL
435#undef FN
436
7ef4227b 437static int spitz_keyboard_post_load(void *opaque, int version_id)
aa941b94 438{
bc24a225 439 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
aa941b94
AZ
440
441 /* Release all pressed keys */
442 memset(s->keyrow, 0, sizeof(s->keyrow));
443 spitz_keyboard_sense_update(s);
444 s->modifiers = 0;
445 s->imodifiers = 0;
446 s->fifopos = 0;
447 s->fifolen = 0;
448
449 return 0;
450}
451
bc24a225 452static void spitz_keyboard_register(PXA2xxState *cpu)
b00052e4 453{
7ef4227b
DES
454 int i;
455 DeviceState *dev;
bc24a225 456 SpitzKeyboardState *s;
b00052e4 457
7ef4227b
DES
458 dev = sysbus_create_simple("spitz-keyboard", -1, NULL);
459 s = FROM_SYSBUS(SpitzKeyboardState, sysbus_from_qdev(dev));
b00052e4 460
38641a52 461 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
0bb53337 462 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(cpu->gpio, spitz_gpio_key_sense[i]));
38641a52
AZ
463
464 for (i = 0; i < 5; i ++)
0bb53337 465 s->gpiomap[i] = qdev_get_gpio_in(cpu->gpio, spitz_gpiomap[i]);
38641a52 466
7ef4227b
DES
467 if (!graphic_rotate)
468 s->gpiomap[4] = qemu_irq_invert(s->gpiomap[4]);
469
470 for (i = 0; i < 5; i++)
471 qemu_set_irq(s->gpiomap[i], 0);
472
b00052e4 473 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
0bb53337 474 qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
7ef4227b
DES
475 qdev_get_gpio_in(dev, i));
476
74475455 477 qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock));
7ef4227b
DES
478
479 qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
480}
481
482static int spitz_keyboard_init(SysBusDevice *dev)
483{
484 SpitzKeyboardState *s;
485 int i, j;
486
487 s = FROM_SYSBUS(SpitzKeyboardState, dev);
488
489 for (i = 0; i < 0x80; i ++)
490 s->keymap[i] = -1;
491 for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
492 for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
493 if (spitz_keymap[i][j] != -1)
494 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
b00052e4
AZ
495
496 spitz_keyboard_pre_map(s);
aa941b94 497
74475455 498 s->kbdtimer = qemu_new_timer_ns(vm_clock, spitz_keyboard_tick, s);
7ef4227b
DES
499 qdev_init_gpio_in(&dev->qdev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
500 qdev_init_gpio_out(&dev->qdev, s->sense, SPITZ_KEY_SENSE_NUM);
501
502 return 0;
b00052e4
AZ
503}
504
b00052e4
AZ
505/* LCD backlight controller */
506
507#define LCDTG_RESCTL 0x00
508#define LCDTG_PHACTRL 0x01
509#define LCDTG_DUTYCTRL 0x02
510#define LCDTG_POWERREG0 0x03
511#define LCDTG_POWERREG1 0x04
512#define LCDTG_GPOR3 0x05
513#define LCDTG_PICTRL 0x06
514#define LCDTG_POLCTRL 0x07
515
a984a69e
PB
516typedef struct {
517 SSISlave ssidev;
43842120
DES
518 uint32_t bl_intensity;
519 uint32_t bl_power;
a984a69e 520} SpitzLCDTG;
b00052e4 521
a984a69e 522static void spitz_bl_update(SpitzLCDTG *s)
b00052e4 523{
a984a69e
PB
524 if (s->bl_power && s->bl_intensity)
525 zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
b00052e4 526 else
89cdb6af 527 zaurus_printf("LCD Backlight now off\n");
b00052e4
AZ
528}
529
a984a69e
PB
530/* FIXME: Implement GPIO properly and remove this hack. */
531static SpitzLCDTG *spitz_lcdtg;
532
38641a52 533static inline void spitz_bl_bit5(void *opaque, int line, int level)
b00052e4 534{
a984a69e
PB
535 SpitzLCDTG *s = spitz_lcdtg;
536 int prev = s->bl_intensity;
b00052e4
AZ
537
538 if (level)
a984a69e 539 s->bl_intensity &= ~0x20;
b00052e4 540 else
a984a69e 541 s->bl_intensity |= 0x20;
b00052e4 542
a984a69e
PB
543 if (s->bl_power && prev != s->bl_intensity)
544 spitz_bl_update(s);
b00052e4
AZ
545}
546
38641a52 547static inline void spitz_bl_power(void *opaque, int line, int level)
b00052e4 548{
a984a69e
PB
549 SpitzLCDTG *s = spitz_lcdtg;
550 s->bl_power = !!level;
551 spitz_bl_update(s);
b00052e4
AZ
552}
553
a984a69e 554static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
b00052e4 555{
a984a69e
PB
556 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
557 int addr;
558 addr = value >> 5;
559 value &= 0x1f;
b00052e4
AZ
560
561 switch (addr) {
562 case LCDTG_RESCTL:
563 if (value)
89cdb6af 564 zaurus_printf("LCD in QVGA mode\n");
b00052e4 565 else
89cdb6af 566 zaurus_printf("LCD in VGA mode\n");
b00052e4
AZ
567 break;
568
569 case LCDTG_DUTYCTRL:
a984a69e
PB
570 s->bl_intensity &= ~0x1f;
571 s->bl_intensity |= value;
572 if (s->bl_power)
573 spitz_bl_update(s);
b00052e4
AZ
574 break;
575
576 case LCDTG_POWERREG0:
577 /* Set common voltage to M62332FP */
578 break;
579 }
a984a69e
PB
580 return 0;
581}
582
81a322d4 583static int spitz_lcdtg_init(SSISlave *dev)
a984a69e
PB
584{
585 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
586
587 spitz_lcdtg = s;
588 s->bl_power = 0;
589 s->bl_intensity = 0x20;
590
81a322d4 591 return 0;
b00052e4
AZ
592}
593
594/* SSP devices */
595
596#define CORGI_SSP_PORT 2
597
598#define SPITZ_GPIO_LCDCON_CS 53
599#define SPITZ_GPIO_ADS7846_CS 14
600#define SPITZ_GPIO_MAX1111_CS 20
601#define SPITZ_GPIO_TP_INT 11
602
a984a69e 603static DeviceState *max1111;
b00052e4
AZ
604
605/* "Demux" the signal based on current chipselect */
a984a69e
PB
606typedef struct {
607 SSISlave ssidev;
608 SSIBus *bus[3];
43842120 609 uint32_t enable[3];
a984a69e 610} CorgiSSPState;
b00052e4 611
a984a69e 612static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
b00052e4 613{
a984a69e
PB
614 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
615 int i;
616
617 for (i = 0; i < 3; i++) {
618 if (s->enable[i]) {
619 return ssi_transfer(s->bus[i], value);
620 }
621 }
622 return 0;
b00052e4
AZ
623}
624
38641a52 625static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
b00052e4 626{
a984a69e
PB
627 CorgiSSPState *s = (CorgiSSPState *)opaque;
628 assert(line >= 0 && line < 3);
629 s->enable[line] = !level;
b00052e4
AZ
630}
631
632#define MAX1111_BATT_VOLT 1
633#define MAX1111_BATT_TEMP 2
634#define MAX1111_ACIN_VOLT 3
635
636#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
637#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
638#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
639
38641a52 640static void spitz_adc_temp_on(void *opaque, int line, int level)
b00052e4
AZ
641{
642 if (!max1111)
643 return;
644
645 if (level)
646 max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
647 else
648 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
649}
650
81a322d4 651static int corgi_ssp_init(SSISlave *dev)
a984a69e
PB
652{
653 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
654
655 qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);
02e2da45
PB
656 s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
657 s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
658 s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
a984a69e 659
81a322d4 660 return 0;
a984a69e
PB
661}
662
bc24a225 663static void spitz_ssp_attach(PXA2xxState *cpu)
b00052e4 664{
a984a69e
PB
665 DeviceState *mux;
666 DeviceState *dev;
667 void *bus;
668
669 mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
38641a52 670
a984a69e 671 bus = qdev_get_child_bus(mux, "ssi0");
22ed1d34 672 ssi_create_slave(bus, "spitz-lcdtg");
b00052e4 673
a984a69e
PB
674 bus = qdev_get_child_bus(mux, "ssi1");
675 dev = ssi_create_slave(bus, "ads7846");
676 qdev_connect_gpio_out(dev, 0,
0bb53337 677 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
b00052e4 678
a984a69e
PB
679 bus = qdev_get_child_bus(mux, "ssi2");
680 max1111 = ssi_create_slave(bus, "max1111");
b00052e4
AZ
681 max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
682 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
683 max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
684
0bb53337 685 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
a984a69e 686 qdev_get_gpio_in(mux, 0));
0bb53337 687 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
a984a69e 688 qdev_get_gpio_in(mux, 1));
0bb53337 689 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
a984a69e 690 qdev_get_gpio_in(mux, 2));
b00052e4
AZ
691}
692
693/* CF Microdrive */
694
bc24a225 695static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
b00052e4 696{
bc24a225 697 PCMCIACardState *md;
751c6a17 698 DriveInfo *dinfo;
b00052e4 699
751c6a17 700 dinfo = drive_get(IF_IDE, 0, 0);
124386cc 701 if (!dinfo || dinfo->media_cd)
e4bcb14c 702 return;
124386cc
MA
703 md = dscm1xxxx_init(dinfo);
704 pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
b00052e4
AZ
705}
706
adb86c37
AZ
707/* Wm8750 and Max7310 on I2C */
708
709#define AKITA_MAX_ADDR 0x18
611d7189
AZ
710#define SPITZ_WM_ADDRL 0x1b
711#define SPITZ_WM_ADDRH 0x1a
adb86c37
AZ
712
713#define SPITZ_GPIO_WM 5
714
38641a52 715static void spitz_wm8750_addr(void *opaque, int line, int level)
adb86c37
AZ
716{
717 i2c_slave *wm = (i2c_slave *) opaque;
718 if (level)
719 i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
720 else
721 i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
722}
adb86c37 723
bc24a225 724static void spitz_i2c_setup(PXA2xxState *cpu)
adb86c37
AZ
725{
726 /* Attach the CPU on one end of our I2C bus. */
727 i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
728
cdbe40ca 729 DeviceState *wm;
adb86c37 730
adb86c37 731 /* Attach a WM8750 to the bus */
cdbe40ca 732 wm = i2c_create_slave(bus, "wm8750", 0);
adb86c37 733
38641a52 734 spitz_wm8750_addr(wm, 0, 0);
0bb53337 735 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_WM,
38641a52 736 qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
adb86c37
AZ
737 /* .. and to the sound interface. */
738 cpu->i2s->opaque = wm;
739 cpu->i2s->codec_out = wm8750_dac_dat;
740 cpu->i2s->codec_in = wm8750_adc_dat;
741 wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
adb86c37
AZ
742}
743
bc24a225 744static void spitz_akita_i2c_setup(PXA2xxState *cpu)
adb86c37
AZ
745{
746 /* Attach a Max7310 to Akita I2C bus. */
6c0bd6bd
PB
747 i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
748 AKITA_MAX_ADDR);
adb86c37
AZ
749}
750
b00052e4
AZ
751/* Other peripherals */
752
38641a52 753static void spitz_out_switch(void *opaque, int line, int level)
b00052e4 754{
38641a52
AZ
755 switch (line) {
756 case 0:
89cdb6af 757 zaurus_printf("Charging %s.\n", level ? "off" : "on");
38641a52
AZ
758 break;
759 case 1:
89cdb6af 760 zaurus_printf("Discharging %s.\n", level ? "on" : "off");
38641a52
AZ
761 break;
762 case 2:
89cdb6af 763 zaurus_printf("Green LED %s.\n", level ? "on" : "off");
38641a52
AZ
764 break;
765 case 3:
89cdb6af 766 zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
38641a52
AZ
767 break;
768 case 4:
769 spitz_bl_bit5(opaque, line, level);
770 break;
771 case 5:
772 spitz_bl_power(opaque, line, level);
773 break;
774 case 6:
775 spitz_adc_temp_on(opaque, line, level);
776 break;
777 }
b00052e4
AZ
778}
779
780#define SPITZ_SCP_LED_GREEN 1
781#define SPITZ_SCP_JK_B 2
782#define SPITZ_SCP_CHRG_ON 3
783#define SPITZ_SCP_MUTE_L 4
784#define SPITZ_SCP_MUTE_R 5
785#define SPITZ_SCP_CF_POWER 6
786#define SPITZ_SCP_LED_ORANGE 7
787#define SPITZ_SCP_JK_A 8
788#define SPITZ_SCP_ADC_TEMP_ON 9
789#define SPITZ_SCP2_IR_ON 1
790#define SPITZ_SCP2_AKIN_PULLUP 2
791#define SPITZ_SCP2_BACKLIGHT_CONT 7
792#define SPITZ_SCP2_BACKLIGHT_ON 8
793#define SPITZ_SCP2_MIC_BIAS 9
794
bc24a225 795static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
383d01c6 796 DeviceState *scp0, DeviceState *scp1)
b00052e4 797{
38641a52
AZ
798 qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
799
383d01c6
DES
800 qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
801 qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
802 qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
803 qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
b00052e4 804
e33d8cdb 805 if (scp1) {
383d01c6
DES
806 qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
807 qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
b00052e4
AZ
808 }
809
383d01c6 810 qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
b00052e4
AZ
811}
812
813#define SPITZ_GPIO_HSYNC 22
814#define SPITZ_GPIO_SD_DETECT 9
815#define SPITZ_GPIO_SD_WP 81
816#define SPITZ_GPIO_ON_RESET 89
817#define SPITZ_GPIO_BAT_COVER 90
818#define SPITZ_GPIO_CF1_IRQ 105
819#define SPITZ_GPIO_CF1_CD 94
820#define SPITZ_GPIO_CF2_IRQ 106
821#define SPITZ_GPIO_CF2_CD 93
822
38641a52 823static int spitz_hsync;
b00052e4 824
38641a52 825static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
b00052e4 826{
bc24a225 827 PXA2xxState *cpu = (PXA2xxState *) opaque;
0bb53337 828 qemu_set_irq(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_HSYNC), spitz_hsync);
b00052e4
AZ
829 spitz_hsync ^= 1;
830}
831
bc24a225 832static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
b00052e4 833{
38641a52 834 qemu_irq lcd_hsync;
b00052e4
AZ
835 /*
836 * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
837 * read to satisfy broken guests that poll-wait for hsync.
838 * Simulating a real hsync event would be less practical and
839 * wouldn't guarantee that a guest ever exits the loop.
840 */
841 spitz_hsync = 0;
38641a52
AZ
842 lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
843 pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
844 pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
b00052e4
AZ
845
846 /* MMC/SD host */
02ce600c 847 pxa2xx_mmci_handlers(cpu->mmc,
0bb53337
DES
848 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_WP),
849 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_DETECT));
b00052e4
AZ
850
851 /* Battery lock always closed */
0bb53337 852 qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
b00052e4
AZ
853
854 /* Handle reset */
0bb53337 855 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
b00052e4
AZ
856
857 /* PCMCIA signals: card's IRQ and Card-Detect */
b00052e4 858 if (slots >= 1)
38641a52 859 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
0bb53337
DES
860 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_IRQ),
861 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_CD));
b00052e4 862 if (slots >= 2)
38641a52 863 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
0bb53337
DES
864 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_IRQ),
865 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_CD));
b00052e4
AZ
866}
867
b00052e4
AZ
868/* Board init. */
869enum spitz_model_e { spitz, akita, borzoi, terrier };
870
7fb4fdcf
AZ
871#define SPITZ_RAM 0x04000000
872#define SPITZ_ROM 0x00800000
873
f93eb9ff
AZ
874static struct arm_boot_info spitz_binfo = {
875 .loader_start = PXA2XX_SDRAM_BASE,
876 .ram_size = 0x04000000,
877};
878
c227f099 879static void spitz_common_init(ram_addr_t ram_size,
3023f332 880 const char *kernel_filename,
b00052e4 881 const char *kernel_cmdline, const char *initrd_filename,
4207117c 882 const char *cpu_model, enum spitz_model_e model, int arm_id)
b00052e4 883{
bc24a225 884 PXA2xxState *cpu;
383d01c6 885 DeviceState *scp0, *scp1 = NULL;
a6dc4c2d 886 MemoryRegion *address_space_mem = get_system_memory();
7cc09e6c 887 MemoryRegion *rom = g_new(MemoryRegion, 1);
b00052e4 888
4207117c
AZ
889 if (!cpu_model)
890 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
b00052e4 891
d95b2f8d 892 /* Setup CPU & memory */
a6dc4c2d 893 cpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
b00052e4
AZ
894
895 sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
896
7cc09e6c
AK
897 memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM);
898 memory_region_set_readonly(rom, true);
899 memory_region_add_subregion(address_space_mem, 0, rom);
b00052e4
AZ
900
901 /* Setup peripherals */
902 spitz_keyboard_register(cpu);
903
904 spitz_ssp_attach(cpu);
905
383d01c6 906 scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
e33d8cdb 907 if (model != akita) {
383d01c6 908 scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
e33d8cdb 909 }
b00052e4 910
e33d8cdb 911 spitz_scoop_gpio_setup(cpu, scp0, scp1);
b00052e4
AZ
912
913 spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
914
adb86c37
AZ
915 spitz_i2c_setup(cpu);
916
917 if (model == akita)
918 spitz_akita_i2c_setup(cpu);
919
b00052e4 920 if (model == terrier)
bf5ee248 921 /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
15b18ec2 922 spitz_microdrive_attach(cpu, 1);
b00052e4 923 else if (model != akita)
15b18ec2
AZ
924 /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
925 spitz_microdrive_attach(cpu, 0);
b00052e4 926
f93eb9ff
AZ
927 spitz_binfo.kernel_filename = kernel_filename;
928 spitz_binfo.kernel_cmdline = kernel_cmdline;
929 spitz_binfo.initrd_filename = initrd_filename;
930 spitz_binfo.board_id = arm_id;
931 arm_load_kernel(cpu->env, &spitz_binfo);
f78630ab 932 sl_bootparam_write(SL_PXA_PARAM_BASE);
b00052e4
AZ
933}
934
c227f099 935static void spitz_init(ram_addr_t ram_size,
3023f332 936 const char *boot_device,
b00052e4
AZ
937 const char *kernel_filename, const char *kernel_cmdline,
938 const char *initrd_filename, const char *cpu_model)
939{
fbe1b595 940 spitz_common_init(ram_size, kernel_filename,
4207117c 941 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
b00052e4
AZ
942}
943
c227f099 944static void borzoi_init(ram_addr_t ram_size,
3023f332 945 const char *boot_device,
b00052e4
AZ
946 const char *kernel_filename, const char *kernel_cmdline,
947 const char *initrd_filename, const char *cpu_model)
948{
fbe1b595 949 spitz_common_init(ram_size, kernel_filename,
4207117c 950 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
b00052e4
AZ
951}
952
c227f099 953static void akita_init(ram_addr_t ram_size,
3023f332 954 const char *boot_device,
b00052e4
AZ
955 const char *kernel_filename, const char *kernel_cmdline,
956 const char *initrd_filename, const char *cpu_model)
957{
fbe1b595 958 spitz_common_init(ram_size, kernel_filename,
4207117c 959 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
b00052e4
AZ
960}
961
c227f099 962static void terrier_init(ram_addr_t ram_size,
3023f332 963 const char *boot_device,
b00052e4
AZ
964 const char *kernel_filename, const char *kernel_cmdline,
965 const char *initrd_filename, const char *cpu_model)
966{
fbe1b595 967 spitz_common_init(ram_size, kernel_filename,
4207117c 968 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
b00052e4
AZ
969}
970
11be4b3e 971static QEMUMachine akitapda_machine = {
4b32e168
AL
972 .name = "akita",
973 .desc = "Akita PDA (PXA270)",
974 .init = akita_init,
b00052e4
AZ
975};
976
f80f9ec9 977static QEMUMachine spitzpda_machine = {
4b32e168
AL
978 .name = "spitz",
979 .desc = "Spitz PDA (PXA270)",
980 .init = spitz_init,
b00052e4
AZ
981};
982
f80f9ec9 983static QEMUMachine borzoipda_machine = {
4b32e168
AL
984 .name = "borzoi",
985 .desc = "Borzoi PDA (PXA270)",
986 .init = borzoi_init,
b00052e4
AZ
987};
988
f80f9ec9 989static QEMUMachine terrierpda_machine = {
4b32e168
AL
990 .name = "terrier",
991 .desc = "Terrier PDA (PXA270)",
992 .init = terrier_init,
b00052e4 993};
a984a69e 994
f80f9ec9
AL
995static void spitz_machine_init(void)
996{
997 qemu_register_machine(&akitapda_machine);
998 qemu_register_machine(&spitzpda_machine);
999 qemu_register_machine(&borzoipda_machine);
1000 qemu_register_machine(&terrierpda_machine);
1001}
1002
1003machine_init(spitz_machine_init);
1004
7ef4227b
DES
1005static bool is_version_0(void *opaque, int version_id)
1006{
1007 return version_id == 0;
1008}
1009
34f9f0b5
DES
1010static VMStateDescription vmstate_sl_nand_info = {
1011 .name = "sl-nand",
1012 .version_id = 0,
1013 .minimum_version_id = 0,
1014 .minimum_version_id_old = 0,
1015 .fields = (VMStateField []) {
1016 VMSTATE_UINT8(ctl, SLNANDState),
1017 VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
1018 VMSTATE_END_OF_LIST(),
1019 },
1020};
1021
1022static SysBusDeviceInfo sl_nand_info = {
1023 .init = sl_nand_init,
1024 .qdev.name = "sl-nand",
1025 .qdev.size = sizeof(SLNANDState),
1026 .qdev.vmsd = &vmstate_sl_nand_info,
1027 .qdev.props = (Property []) {
1028 DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG),
1029 DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1),
1030 DEFINE_PROP_END_OF_LIST(),
1031 },
1032};
1033
7ef4227b
DES
1034static VMStateDescription vmstate_spitz_kbd = {
1035 .name = "spitz-keyboard",
1036 .version_id = 1,
1037 .minimum_version_id = 0,
1038 .minimum_version_id_old = 0,
1039 .post_load = spitz_keyboard_post_load,
1040 .fields = (VMStateField []) {
1041 VMSTATE_UINT16(sense_state, SpitzKeyboardState),
1042 VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
1043 VMSTATE_UNUSED_TEST(is_version_0, 5),
1044 VMSTATE_END_OF_LIST(),
1045 },
1046};
1047
1048static SysBusDeviceInfo spitz_keyboard_info = {
1049 .init = spitz_keyboard_init,
1050 .qdev.name = "spitz-keyboard",
1051 .qdev.size = sizeof(SpitzKeyboardState),
1052 .qdev.vmsd = &vmstate_spitz_kbd,
1053 .qdev.props = (Property []) {
1054 DEFINE_PROP_END_OF_LIST(),
1055 },
1056};
1057
43842120
DES
1058static const VMStateDescription vmstate_corgi_ssp_regs = {
1059 .name = "corgi-ssp",
1060 .version_id = 1,
1061 .minimum_version_id = 1,
1062 .minimum_version_id_old = 1,
1063 .fields = (VMStateField []) {
1064 VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
1065 VMSTATE_END_OF_LIST(),
1066 }
1067};
1068
a984a69e 1069static SSISlaveInfo corgi_ssp_info = {
074f2fff
GH
1070 .qdev.name = "corgi-ssp",
1071 .qdev.size = sizeof(CorgiSSPState),
43842120 1072 .qdev.vmsd = &vmstate_corgi_ssp_regs,
a984a69e
PB
1073 .init = corgi_ssp_init,
1074 .transfer = corgi_ssp_transfer
1075};
1076
43842120
DES
1077static const VMStateDescription vmstate_spitz_lcdtg_regs = {
1078 .name = "spitz-lcdtg",
1079 .version_id = 1,
1080 .minimum_version_id = 1,
1081 .minimum_version_id_old = 1,
1082 .fields = (VMStateField []) {
1083 VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
1084 VMSTATE_UINT32(bl_power, SpitzLCDTG),
1085 VMSTATE_END_OF_LIST(),
1086 }
1087};
1088
a984a69e 1089static SSISlaveInfo spitz_lcdtg_info = {
074f2fff
GH
1090 .qdev.name = "spitz-lcdtg",
1091 .qdev.size = sizeof(SpitzLCDTG),
43842120 1092 .qdev.vmsd = &vmstate_spitz_lcdtg_regs,
a984a69e
PB
1093 .init = spitz_lcdtg_init,
1094 .transfer = spitz_lcdtg_transfer
1095};
1096
1097static void spitz_register_devices(void)
1098{
074f2fff
GH
1099 ssi_register_slave(&corgi_ssp_info);
1100 ssi_register_slave(&spitz_lcdtg_info);
7ef4227b 1101 sysbus_register_withprop(&spitz_keyboard_info);
34f9f0b5 1102 sysbus_register_withprop(&sl_nand_info);
a984a69e
PB
1103}
1104
1105device_init(spitz_register_devices)