]> git.proxmox.com Git - qemu.git/blame - hw/spitz.c
qdev/pci: hook up i440fx.
[qemu.git] / hw / spitz.c
CommitLineData
b00052e4
AZ
1/*
2 * PXA270-based Clamshell PDA platforms.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GNU GPL v2.
8 */
9
87ecb68b
PB
10#include "hw.h"
11#include "pxa.h"
12#include "arm-misc.h"
13#include "sysemu.h"
14#include "pcmcia.h"
15#include "i2c.h"
a984a69e 16#include "ssi.h"
87ecb68b
PB
17#include "flash.h"
18#include "qemu-timer.h"
19#include "devices.h"
e33d8cdb 20#include "sharpsl.h"
87ecb68b
PB
21#include "console.h"
22#include "block.h"
23#include "audio/audio.h"
24#include "boards.h"
b00052e4 25
b00052e4
AZ
26#undef REG_FMT
27#define REG_FMT "0x%02lx"
28
29/* Spitz Flash */
30#define FLASH_BASE 0x0c000000
31#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
32#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
33#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
34#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
35#define FLASH_ECCCLRR 0x10 /* Clear ECC */
36#define FLASH_FLASHIO 0x14 /* Flash I/O */
37#define FLASH_FLASHCTL 0x18 /* Flash Control */
38
39#define FLASHCTL_CE0 (1 << 0)
40#define FLASHCTL_CLE (1 << 1)
41#define FLASHCTL_ALE (1 << 2)
42#define FLASHCTL_WP (1 << 3)
43#define FLASHCTL_CE1 (1 << 4)
44#define FLASHCTL_RYBY (1 << 5)
45#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
46
bc24a225
PB
47typedef struct {
48 NANDFlashState *nand;
b00052e4 49 uint8_t ctl;
bc24a225
PB
50 ECCState ecc;
51} SLNANDState;
b00052e4
AZ
52
53static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
54{
bc24a225 55 SLNANDState *s = (SLNANDState *) opaque;
b00052e4 56 int ryby;
b00052e4
AZ
57
58 switch (addr) {
59#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
60 case FLASH_ECCLPLB:
61 return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
62 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
63
64#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
65 case FLASH_ECCLPUB:
66 return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
67 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
68
69 case FLASH_ECCCP:
70 return s->ecc.cp;
71
72 case FLASH_ECCCNTR:
73 return s->ecc.count & 0xff;
74
75 case FLASH_FLASHCTL:
76 nand_getpins(s->nand, &ryby);
77 if (ryby)
78 return s->ctl | FLASHCTL_RYBY;
79 else
80 return s->ctl;
81
82 case FLASH_FLASHIO:
83 return ecc_digest(&s->ecc, nand_getio(s->nand));
84
85 default:
a8b7063b 86 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
b00052e4
AZ
87 }
88 return 0;
89}
90
a5236105
AZ
91static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
92{
bc24a225 93 SLNANDState *s = (SLNANDState *) opaque;
a5236105
AZ
94
95 if (addr == FLASH_FLASHIO)
96 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
97 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
98
99 return sl_readb(opaque, addr);
100}
101
b00052e4
AZ
102static void sl_writeb(void *opaque, target_phys_addr_t addr,
103 uint32_t value)
104{
bc24a225 105 SLNANDState *s = (SLNANDState *) opaque;
b00052e4
AZ
106
107 switch (addr) {
108 case FLASH_ECCCLRR:
109 /* Value is ignored. */
110 ecc_reset(&s->ecc);
111 break;
112
113 case FLASH_FLASHCTL:
114 s->ctl = value & 0xff & ~FLASHCTL_RYBY;
115 nand_setpins(s->nand,
116 s->ctl & FLASHCTL_CLE,
117 s->ctl & FLASHCTL_ALE,
118 s->ctl & FLASHCTL_NCE,
119 s->ctl & FLASHCTL_WP,
120 0);
121 break;
122
123 case FLASH_FLASHIO:
124 nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
125 break;
126
127 default:
a8b7063b 128 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
b00052e4
AZ
129 }
130}
131
aa941b94
AZ
132static void sl_save(QEMUFile *f, void *opaque)
133{
bc24a225 134 SLNANDState *s = (SLNANDState *) opaque;
aa941b94
AZ
135
136 qemu_put_8s(f, &s->ctl);
137 ecc_put(f, &s->ecc);
138}
139
140static int sl_load(QEMUFile *f, void *opaque, int version_id)
141{
bc24a225 142 SLNANDState *s = (SLNANDState *) opaque;
aa941b94
AZ
143
144 qemu_get_8s(f, &s->ctl);
145 ecc_get(f, &s->ecc);
146
147 return 0;
148}
149
b00052e4
AZ
150enum {
151 FLASH_128M,
152 FLASH_1024M,
153};
154
bc24a225 155static void sl_flash_register(PXA2xxState *cpu, int size)
b00052e4
AZ
156{
157 int iomemtype;
bc24a225 158 SLNANDState *s;
b00052e4
AZ
159 CPUReadMemoryFunc *sl_readfn[] = {
160 sl_readb,
161 sl_readb,
a5236105 162 sl_readl,
b00052e4
AZ
163 };
164 CPUWriteMemoryFunc *sl_writefn[] = {
165 sl_writeb,
166 sl_writeb,
167 sl_writeb,
168 };
169
bc24a225 170 s = (SLNANDState *) qemu_mallocz(sizeof(SLNANDState));
b00052e4
AZ
171 s->ctl = 0;
172 if (size == FLASH_128M)
173 s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
174 else if (size == FLASH_1024M)
175 s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
176
1eed09cb 177 iomemtype = cpu_register_io_memory(sl_readfn,
b00052e4 178 sl_writefn, s);
8da3ff18 179 cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);
aa941b94
AZ
180
181 register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
b00052e4
AZ
182}
183
184/* Spitz Keyboard */
185
186#define SPITZ_KEY_STROBE_NUM 11
187#define SPITZ_KEY_SENSE_NUM 7
188
189static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
190 12, 17, 91, 34, 36, 38, 39
191};
192
193static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
194 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
195};
196
197/* Eighth additional row maps the special keys */
198static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
199 { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
200 { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
201 { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
202 { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
203 { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
2b76bdc9
AZ
204 { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
205 { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
b00052e4
AZ
206 { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
207};
208
209#define SPITZ_GPIO_AK_INT 13 /* Remote control */
210#define SPITZ_GPIO_SYNC 16 /* Sync button */
211#define SPITZ_GPIO_ON_KEY 95 /* Power button */
212#define SPITZ_GPIO_SWA 97 /* Lid */
213#define SPITZ_GPIO_SWB 96 /* Tablet mode */
214
215/* The special buttons are mapped to unused keys */
216static const int spitz_gpiomap[5] = {
217 SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
218 SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
219};
220static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
221
bc24a225 222typedef struct {
38641a52
AZ
223 qemu_irq sense[SPITZ_KEY_SENSE_NUM];
224 qemu_irq *strobe;
225 qemu_irq gpiomap[5];
b00052e4
AZ
226 int keymap[0x80];
227 uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
228 uint16_t strobe_state;
229 uint16_t sense_state;
230
231 uint16_t pre_map[0x100];
232 uint16_t modifiers;
233 uint16_t imodifiers;
234 uint8_t fifo[16];
235 int fifopos, fifolen;
236 QEMUTimer *kbdtimer;
bc24a225 237} SpitzKeyboardState;
b00052e4 238
bc24a225 239static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
b00052e4
AZ
240{
241 int i;
242 uint16_t strobe, sense = 0;
243 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
244 strobe = s->keyrow[i] & s->strobe_state;
245 if (strobe) {
246 sense |= 1 << i;
247 if (!(s->sense_state & (1 << i)))
38641a52 248 qemu_irq_raise(s->sense[i]);
b00052e4 249 } else if (s->sense_state & (1 << i))
38641a52 250 qemu_irq_lower(s->sense[i]);
b00052e4
AZ
251 }
252
253 s->sense_state = sense;
254}
255
38641a52 256static void spitz_keyboard_strobe(void *opaque, int line, int level)
b00052e4 257{
bc24a225 258 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
38641a52
AZ
259
260 if (level)
261 s->strobe_state |= 1 << line;
262 else
263 s->strobe_state &= ~(1 << line);
264 spitz_keyboard_sense_update(s);
b00052e4
AZ
265}
266
bc24a225 267static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
b00052e4
AZ
268{
269 int spitz_keycode = s->keymap[keycode & 0x7f];
270 if (spitz_keycode == -1)
271 return;
272
273 /* Handle the additional keys */
274 if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
38641a52 275 qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^
b00052e4
AZ
276 spitz_gpio_invert[spitz_keycode & 0xf]);
277 return;
278 }
279
280 if (keycode & 0x80)
281 s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
282 else
283 s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
284
285 spitz_keyboard_sense_update(s);
286}
287
288#define SHIFT (1 << 7)
289#define CTRL (1 << 8)
290#define FN (1 << 9)
291
292#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
293
bc24a225 294static void spitz_keyboard_handler(SpitzKeyboardState *s, int keycode)
b00052e4
AZ
295{
296 uint16_t code;
297 int mapcode;
298 switch (keycode) {
299 case 0x2a: /* Left Shift */
300 s->modifiers |= 1;
301 break;
302 case 0xaa:
303 s->modifiers &= ~1;
304 break;
305 case 0x36: /* Right Shift */
306 s->modifiers |= 2;
307 break;
308 case 0xb6:
309 s->modifiers &= ~2;
310 break;
311 case 0x1d: /* Control */
312 s->modifiers |= 4;
313 break;
314 case 0x9d:
315 s->modifiers &= ~4;
316 break;
317 case 0x38: /* Alt */
318 s->modifiers |= 8;
319 break;
320 case 0xb8:
321 s->modifiers &= ~8;
322 break;
323 }
324
325 code = s->pre_map[mapcode = ((s->modifiers & 3) ?
326 (keycode | SHIFT) :
327 (keycode & ~SHIFT))];
328
329 if (code != mapcode) {
330#if 0
331 if ((code & SHIFT) && !(s->modifiers & 1))
332 QUEUE_KEY(0x2a | (keycode & 0x80));
333 if ((code & CTRL ) && !(s->modifiers & 4))
334 QUEUE_KEY(0x1d | (keycode & 0x80));
335 if ((code & FN ) && !(s->modifiers & 8))
336 QUEUE_KEY(0x38 | (keycode & 0x80));
337 if ((code & FN ) && (s->modifiers & 1))
338 QUEUE_KEY(0x2a | (~keycode & 0x80));
339 if ((code & FN ) && (s->modifiers & 2))
340 QUEUE_KEY(0x36 | (~keycode & 0x80));
341#else
342 if (keycode & 0x80) {
343 if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
344 QUEUE_KEY(0x2a | 0x80);
345 if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
346 QUEUE_KEY(0x1d | 0x80);
347 if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
348 QUEUE_KEY(0x38 | 0x80);
349 if ((s->imodifiers & 0x10) && (s->modifiers & 1))
350 QUEUE_KEY(0x2a);
351 if ((s->imodifiers & 0x20) && (s->modifiers & 2))
352 QUEUE_KEY(0x36);
353 s->imodifiers = 0;
354 } else {
355 if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
356 QUEUE_KEY(0x2a);
357 s->imodifiers |= 1;
358 }
359 if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
360 QUEUE_KEY(0x1d);
361 s->imodifiers |= 4;
362 }
363 if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
364 QUEUE_KEY(0x38);
365 s->imodifiers |= 8;
366 }
367 if ((code & FN ) && (s->modifiers & 1) &&
368 !(s->imodifiers & 0x10)) {
369 QUEUE_KEY(0x2a | 0x80);
370 s->imodifiers |= 0x10;
371 }
372 if ((code & FN ) && (s->modifiers & 2) &&
373 !(s->imodifiers & 0x20)) {
374 QUEUE_KEY(0x36 | 0x80);
375 s->imodifiers |= 0x20;
376 }
377 }
378#endif
379 }
380
381 QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
382}
383
384static void spitz_keyboard_tick(void *opaque)
385{
bc24a225 386 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
b00052e4
AZ
387
388 if (s->fifolen) {
389 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
390 s->fifolen --;
391 if (s->fifopos >= 16)
392 s->fifopos = 0;
393 }
394
395 qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
396}
397
bc24a225 398static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
b00052e4
AZ
399{
400 int i;
401 for (i = 0; i < 0x100; i ++)
402 s->pre_map[i] = i;
403 s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
404 s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
405 s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
406 s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
407 s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
408 s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
409 s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
410 s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
411 s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
412 s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
413 s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
414 s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
415 s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
416 s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
417 s->pre_map[0x0d ] = 0x12 | FN; /* equal */
418 s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
419 s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
420 s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
2b76bdc9
AZ
421 s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
422 s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
b00052e4
AZ
423 s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
424 s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
425 s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
426 s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
427 s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
428 s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
2b76bdc9 429 s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
b00052e4 430 s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
2b76bdc9 431 s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
b00052e4
AZ
432 s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
433 s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
434 s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
435
436 s->modifiers = 0;
437 s->imodifiers = 0;
438 s->fifopos = 0;
439 s->fifolen = 0;
440 s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
441 spitz_keyboard_tick(s);
442}
443
444#undef SHIFT
445#undef CTRL
446#undef FN
447
aa941b94
AZ
448static void spitz_keyboard_save(QEMUFile *f, void *opaque)
449{
bc24a225 450 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
aa941b94
AZ
451 int i;
452
453 qemu_put_be16s(f, &s->sense_state);
454 qemu_put_be16s(f, &s->strobe_state);
455 for (i = 0; i < 5; i ++)
456 qemu_put_byte(f, spitz_gpio_invert[i]);
457}
458
459static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
460{
bc24a225 461 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
aa941b94
AZ
462 int i;
463
464 qemu_get_be16s(f, &s->sense_state);
465 qemu_get_be16s(f, &s->strobe_state);
466 for (i = 0; i < 5; i ++)
467 spitz_gpio_invert[i] = qemu_get_byte(f);
468
469 /* Release all pressed keys */
470 memset(s->keyrow, 0, sizeof(s->keyrow));
471 spitz_keyboard_sense_update(s);
472 s->modifiers = 0;
473 s->imodifiers = 0;
474 s->fifopos = 0;
475 s->fifolen = 0;
476
477 return 0;
478}
479
bc24a225 480static void spitz_keyboard_register(PXA2xxState *cpu)
b00052e4
AZ
481{
482 int i, j;
bc24a225 483 SpitzKeyboardState *s;
b00052e4 484
bc24a225
PB
485 s = (SpitzKeyboardState *)
486 qemu_mallocz(sizeof(SpitzKeyboardState));
487 memset(s, 0, sizeof(SpitzKeyboardState));
b00052e4
AZ
488
489 for (i = 0; i < 0x80; i ++)
490 s->keymap[i] = -1;
491 for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
492 for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
493 if (spitz_keymap[i][j] != -1)
494 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
495
38641a52
AZ
496 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
497 s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]];
498
499 for (i = 0; i < 5; i ++)
500 s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]];
501
502 s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s,
503 SPITZ_KEY_STROBE_NUM);
b00052e4 504 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
38641a52 505 pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]);
b00052e4
AZ
506
507 spitz_keyboard_pre_map(s);
508 qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
aa941b94
AZ
509
510 register_savevm("spitz_keyboard", 0, 0,
511 spitz_keyboard_save, spitz_keyboard_load, s);
b00052e4
AZ
512}
513
b00052e4
AZ
514/* LCD backlight controller */
515
516#define LCDTG_RESCTL 0x00
517#define LCDTG_PHACTRL 0x01
518#define LCDTG_DUTYCTRL 0x02
519#define LCDTG_POWERREG0 0x03
520#define LCDTG_POWERREG1 0x04
521#define LCDTG_GPOR3 0x05
522#define LCDTG_PICTRL 0x06
523#define LCDTG_POLCTRL 0x07
524
a984a69e
PB
525typedef struct {
526 SSISlave ssidev;
527 int bl_intensity;
528 int bl_power;
529} SpitzLCDTG;
b00052e4 530
a984a69e 531static void spitz_bl_update(SpitzLCDTG *s)
b00052e4 532{
a984a69e
PB
533 if (s->bl_power && s->bl_intensity)
534 zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
b00052e4 535 else
89cdb6af 536 zaurus_printf("LCD Backlight now off\n");
b00052e4
AZ
537}
538
a984a69e
PB
539/* FIXME: Implement GPIO properly and remove this hack. */
540static SpitzLCDTG *spitz_lcdtg;
541
38641a52 542static inline void spitz_bl_bit5(void *opaque, int line, int level)
b00052e4 543{
a984a69e
PB
544 SpitzLCDTG *s = spitz_lcdtg;
545 int prev = s->bl_intensity;
b00052e4
AZ
546
547 if (level)
a984a69e 548 s->bl_intensity &= ~0x20;
b00052e4 549 else
a984a69e 550 s->bl_intensity |= 0x20;
b00052e4 551
a984a69e
PB
552 if (s->bl_power && prev != s->bl_intensity)
553 spitz_bl_update(s);
b00052e4
AZ
554}
555
38641a52 556static inline void spitz_bl_power(void *opaque, int line, int level)
b00052e4 557{
a984a69e
PB
558 SpitzLCDTG *s = spitz_lcdtg;
559 s->bl_power = !!level;
560 spitz_bl_update(s);
b00052e4
AZ
561}
562
a984a69e 563static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
b00052e4 564{
a984a69e
PB
565 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
566 int addr;
567 addr = value >> 5;
568 value &= 0x1f;
b00052e4
AZ
569
570 switch (addr) {
571 case LCDTG_RESCTL:
572 if (value)
89cdb6af 573 zaurus_printf("LCD in QVGA mode\n");
b00052e4 574 else
89cdb6af 575 zaurus_printf("LCD in VGA mode\n");
b00052e4
AZ
576 break;
577
578 case LCDTG_DUTYCTRL:
a984a69e
PB
579 s->bl_intensity &= ~0x1f;
580 s->bl_intensity |= value;
581 if (s->bl_power)
582 spitz_bl_update(s);
b00052e4
AZ
583 break;
584
585 case LCDTG_POWERREG0:
586 /* Set common voltage to M62332FP */
587 break;
588 }
a984a69e
PB
589 return 0;
590}
591
592static void spitz_lcdtg_save(QEMUFile *f, void *opaque)
593{
594 SpitzLCDTG *s = (SpitzLCDTG *)opaque;
595 qemu_put_be32(f, s->bl_intensity);
596 qemu_put_be32(f, s->bl_power);
597}
598
599static int spitz_lcdtg_load(QEMUFile *f, void *opaque, int version_id)
600{
601 SpitzLCDTG *s = (SpitzLCDTG *)opaque;
602 s->bl_intensity = qemu_get_be32(f);
603 s->bl_power = qemu_get_be32(f);
604 return 0;
605}
606
607static void spitz_lcdtg_init(SSISlave *dev)
608{
609 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
610
611 spitz_lcdtg = s;
612 s->bl_power = 0;
613 s->bl_intensity = 0x20;
614
615 register_savevm("spitz-lcdtg", -1, 1,
616 spitz_lcdtg_save, spitz_lcdtg_load, s);
b00052e4
AZ
617}
618
619/* SSP devices */
620
621#define CORGI_SSP_PORT 2
622
623#define SPITZ_GPIO_LCDCON_CS 53
624#define SPITZ_GPIO_ADS7846_CS 14
625#define SPITZ_GPIO_MAX1111_CS 20
626#define SPITZ_GPIO_TP_INT 11
627
a984a69e 628static DeviceState *max1111;
b00052e4
AZ
629
630/* "Demux" the signal based on current chipselect */
a984a69e
PB
631typedef struct {
632 SSISlave ssidev;
633 SSIBus *bus[3];
634 int enable[3];
635} CorgiSSPState;
b00052e4 636
a984a69e 637static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
b00052e4 638{
a984a69e
PB
639 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
640 int i;
641
642 for (i = 0; i < 3; i++) {
643 if (s->enable[i]) {
644 return ssi_transfer(s->bus[i], value);
645 }
646 }
647 return 0;
b00052e4
AZ
648}
649
38641a52 650static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
b00052e4 651{
a984a69e
PB
652 CorgiSSPState *s = (CorgiSSPState *)opaque;
653 assert(line >= 0 && line < 3);
654 s->enable[line] = !level;
b00052e4
AZ
655}
656
657#define MAX1111_BATT_VOLT 1
658#define MAX1111_BATT_TEMP 2
659#define MAX1111_ACIN_VOLT 3
660
661#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
662#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
663#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
664
38641a52 665static void spitz_adc_temp_on(void *opaque, int line, int level)
b00052e4
AZ
666{
667 if (!max1111)
668 return;
669
670 if (level)
671 max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
672 else
673 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
674}
675
aa941b94
AZ
676static void spitz_ssp_save(QEMUFile *f, void *opaque)
677{
a984a69e
PB
678 CorgiSSPState *s = (CorgiSSPState *)opaque;
679 int i;
680
681 for (i = 0; i < 3; i++) {
682 qemu_put_be32(f, s->enable[i]);
683 }
aa941b94
AZ
684}
685
686static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
687{
a984a69e
PB
688 CorgiSSPState *s = (CorgiSSPState *)opaque;
689 int i;
aa941b94 690
a984a69e
PB
691 if (version_id != 1) {
692 return -EINVAL;
693 }
694 for (i = 0; i < 3; i++) {
695 s->enable[i] = qemu_get_be32(f);
696 }
aa941b94
AZ
697 return 0;
698}
699
a984a69e
PB
700static void corgi_ssp_init(SSISlave *dev)
701{
702 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
703
704 qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);
02e2da45
PB
705 s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
706 s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
707 s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
a984a69e
PB
708
709 register_savevm("spitz_ssp", -1, 1, spitz_ssp_save, spitz_ssp_load, s);
710}
711
bc24a225 712static void spitz_ssp_attach(PXA2xxState *cpu)
b00052e4 713{
a984a69e
PB
714 DeviceState *mux;
715 DeviceState *dev;
716 void *bus;
717
718 mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
38641a52 719
a984a69e
PB
720 bus = qdev_get_child_bus(mux, "ssi0");
721 dev = ssi_create_slave(bus, "spitz-lcdtg");
b00052e4 722
a984a69e
PB
723 bus = qdev_get_child_bus(mux, "ssi1");
724 dev = ssi_create_slave(bus, "ads7846");
725 qdev_connect_gpio_out(dev, 0,
726 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]);
b00052e4 727
a984a69e
PB
728 bus = qdev_get_child_bus(mux, "ssi2");
729 max1111 = ssi_create_slave(bus, "max1111");
b00052e4
AZ
730 max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
731 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
732 max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
733
a984a69e
PB
734 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
735 qdev_get_gpio_in(mux, 0));
736 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
737 qdev_get_gpio_in(mux, 1));
738 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
739 qdev_get_gpio_in(mux, 2));
b00052e4
AZ
740}
741
742/* CF Microdrive */
743
bc24a225 744static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
b00052e4 745{
bc24a225 746 PCMCIACardState *md;
e4bcb14c
TS
747 int index;
748 BlockDriverState *bs;
b00052e4 749
e4bcb14c
TS
750 index = drive_get_index(IF_IDE, 0, 0);
751 if (index == -1)
752 return;
753 bs = drives_table[index].bdrv;
754 if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
b00052e4 755 md = dscm1xxxx_init(bs);
15b18ec2 756 pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
b00052e4
AZ
757 }
758}
759
adb86c37
AZ
760/* Wm8750 and Max7310 on I2C */
761
762#define AKITA_MAX_ADDR 0x18
611d7189
AZ
763#define SPITZ_WM_ADDRL 0x1b
764#define SPITZ_WM_ADDRH 0x1a
adb86c37
AZ
765
766#define SPITZ_GPIO_WM 5
767
768#ifdef HAS_AUDIO
38641a52 769static void spitz_wm8750_addr(void *opaque, int line, int level)
adb86c37
AZ
770{
771 i2c_slave *wm = (i2c_slave *) opaque;
772 if (level)
773 i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
774 else
775 i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
776}
777#endif
778
bc24a225 779static void spitz_i2c_setup(PXA2xxState *cpu)
adb86c37
AZ
780{
781 /* Attach the CPU on one end of our I2C bus. */
782 i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
783
784#ifdef HAS_AUDIO
cdbe40ca 785 DeviceState *wm;
adb86c37 786
adb86c37 787 /* Attach a WM8750 to the bus */
cdbe40ca 788 wm = i2c_create_slave(bus, "wm8750", 0);
adb86c37 789
38641a52
AZ
790 spitz_wm8750_addr(wm, 0, 0);
791 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
792 qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
adb86c37
AZ
793 /* .. and to the sound interface. */
794 cpu->i2s->opaque = wm;
795 cpu->i2s->codec_out = wm8750_dac_dat;
796 cpu->i2s->codec_in = wm8750_adc_dat;
797 wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
798#endif
799}
800
bc24a225 801static void spitz_akita_i2c_setup(PXA2xxState *cpu)
adb86c37
AZ
802{
803 /* Attach a Max7310 to Akita I2C bus. */
6c0bd6bd
PB
804 i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
805 AKITA_MAX_ADDR);
adb86c37
AZ
806}
807
b00052e4
AZ
808/* Other peripherals */
809
38641a52 810static void spitz_out_switch(void *opaque, int line, int level)
b00052e4 811{
38641a52
AZ
812 switch (line) {
813 case 0:
89cdb6af 814 zaurus_printf("Charging %s.\n", level ? "off" : "on");
38641a52
AZ
815 break;
816 case 1:
89cdb6af 817 zaurus_printf("Discharging %s.\n", level ? "on" : "off");
38641a52
AZ
818 break;
819 case 2:
89cdb6af 820 zaurus_printf("Green LED %s.\n", level ? "on" : "off");
38641a52
AZ
821 break;
822 case 3:
89cdb6af 823 zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
38641a52
AZ
824 break;
825 case 4:
826 spitz_bl_bit5(opaque, line, level);
827 break;
828 case 5:
829 spitz_bl_power(opaque, line, level);
830 break;
831 case 6:
832 spitz_adc_temp_on(opaque, line, level);
833 break;
834 }
b00052e4
AZ
835}
836
837#define SPITZ_SCP_LED_GREEN 1
838#define SPITZ_SCP_JK_B 2
839#define SPITZ_SCP_CHRG_ON 3
840#define SPITZ_SCP_MUTE_L 4
841#define SPITZ_SCP_MUTE_R 5
842#define SPITZ_SCP_CF_POWER 6
843#define SPITZ_SCP_LED_ORANGE 7
844#define SPITZ_SCP_JK_A 8
845#define SPITZ_SCP_ADC_TEMP_ON 9
846#define SPITZ_SCP2_IR_ON 1
847#define SPITZ_SCP2_AKIN_PULLUP 2
848#define SPITZ_SCP2_BACKLIGHT_CONT 7
849#define SPITZ_SCP2_BACKLIGHT_ON 8
850#define SPITZ_SCP2_MIC_BIAS 9
851
bc24a225
PB
852static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
853 ScoopInfo *scp0, ScoopInfo *scp1)
b00052e4 854{
38641a52
AZ
855 qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
856
e33d8cdb
AZ
857 scoop_gpio_out_set(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
858 scoop_gpio_out_set(scp0, SPITZ_SCP_JK_B, outsignals[1]);
859 scoop_gpio_out_set(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
860 scoop_gpio_out_set(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
b00052e4 861
e33d8cdb
AZ
862 if (scp1) {
863 scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
864 scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
b00052e4
AZ
865 }
866
e33d8cdb 867 scoop_gpio_out_set(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
b00052e4
AZ
868}
869
870#define SPITZ_GPIO_HSYNC 22
871#define SPITZ_GPIO_SD_DETECT 9
872#define SPITZ_GPIO_SD_WP 81
873#define SPITZ_GPIO_ON_RESET 89
874#define SPITZ_GPIO_BAT_COVER 90
875#define SPITZ_GPIO_CF1_IRQ 105
876#define SPITZ_GPIO_CF1_CD 94
877#define SPITZ_GPIO_CF2_IRQ 106
878#define SPITZ_GPIO_CF2_CD 93
879
38641a52 880static int spitz_hsync;
b00052e4 881
38641a52 882static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
b00052e4 883{
bc24a225 884 PXA2xxState *cpu = (PXA2xxState *) opaque;
38641a52 885 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
b00052e4
AZ
886 spitz_hsync ^= 1;
887}
888
bc24a225 889static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
b00052e4 890{
38641a52 891 qemu_irq lcd_hsync;
b00052e4
AZ
892 /*
893 * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
894 * read to satisfy broken guests that poll-wait for hsync.
895 * Simulating a real hsync event would be less practical and
896 * wouldn't guarantee that a guest ever exits the loop.
897 */
898 spitz_hsync = 0;
38641a52
AZ
899 lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
900 pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
901 pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
b00052e4
AZ
902
903 /* MMC/SD host */
02ce600c
AZ
904 pxa2xx_mmci_handlers(cpu->mmc,
905 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP],
906 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]);
b00052e4
AZ
907
908 /* Battery lock always closed */
38641a52 909 qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]);
b00052e4
AZ
910
911 /* Handle reset */
38641a52 912 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
b00052e4
AZ
913
914 /* PCMCIA signals: card's IRQ and Card-Detect */
b00052e4 915 if (slots >= 1)
38641a52
AZ
916 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
917 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ],
918 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]);
b00052e4 919 if (slots >= 2)
38641a52
AZ
920 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
921 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ],
922 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]);
b00052e4
AZ
923
924 /* Initialise the screen rotation related signals */
925 spitz_gpio_invert[3] = 0; /* Always open */
926 if (graphic_rotate) { /* Tablet mode */
927 spitz_gpio_invert[4] = 0;
928 } else { /* Portrait mode */
929 spitz_gpio_invert[4] = 1;
930 }
38641a52
AZ
931 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA],
932 spitz_gpio_invert[3]);
933 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB],
934 spitz_gpio_invert[4]);
b00052e4
AZ
935}
936
b00052e4
AZ
937/* Board init. */
938enum spitz_model_e { spitz, akita, borzoi, terrier };
939
7fb4fdcf
AZ
940#define SPITZ_RAM 0x04000000
941#define SPITZ_ROM 0x00800000
942
f93eb9ff
AZ
943static struct arm_boot_info spitz_binfo = {
944 .loader_start = PXA2XX_SDRAM_BASE,
945 .ram_size = 0x04000000,
946};
947
fbe1b595 948static void spitz_common_init(ram_addr_t ram_size,
3023f332 949 const char *kernel_filename,
b00052e4 950 const char *kernel_cmdline, const char *initrd_filename,
4207117c 951 const char *cpu_model, enum spitz_model_e model, int arm_id)
b00052e4 952{
bc24a225
PB
953 PXA2xxState *cpu;
954 ScoopInfo *scp0, *scp1 = NULL;
b00052e4 955
4207117c
AZ
956 if (!cpu_model)
957 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
b00052e4 958
d95b2f8d 959 /* Setup CPU & memory */
3023f332 960 cpu = pxa270_init(spitz_binfo.ram_size, cpu_model);
b00052e4
AZ
961
962 sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
963
7fb4fdcf
AZ
964 cpu_register_physical_memory(0, SPITZ_ROM,
965 qemu_ram_alloc(SPITZ_ROM) | IO_MEM_ROM);
b00052e4
AZ
966
967 /* Setup peripherals */
968 spitz_keyboard_register(cpu);
969
970 spitz_ssp_attach(cpu);
971
e33d8cdb
AZ
972 scp0 = scoop_init(cpu, 0, 0x10800000);
973 if (model != akita) {
974 scp1 = scoop_init(cpu, 1, 0x08800040);
975 }
b00052e4 976
e33d8cdb 977 spitz_scoop_gpio_setup(cpu, scp0, scp1);
b00052e4
AZ
978
979 spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
980
adb86c37
AZ
981 spitz_i2c_setup(cpu);
982
983 if (model == akita)
984 spitz_akita_i2c_setup(cpu);
985
b00052e4 986 if (model == terrier)
bf5ee248 987 /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
15b18ec2 988 spitz_microdrive_attach(cpu, 1);
b00052e4 989 else if (model != akita)
15b18ec2
AZ
990 /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
991 spitz_microdrive_attach(cpu, 0);
b00052e4
AZ
992
993 /* Setup initial (reset) machine state */
f93eb9ff 994 cpu->env->regs[15] = spitz_binfo.loader_start;
b00052e4 995
f93eb9ff
AZ
996 spitz_binfo.kernel_filename = kernel_filename;
997 spitz_binfo.kernel_cmdline = kernel_cmdline;
998 spitz_binfo.initrd_filename = initrd_filename;
999 spitz_binfo.board_id = arm_id;
1000 arm_load_kernel(cpu->env, &spitz_binfo);
f78630ab 1001 sl_bootparam_write(SL_PXA_PARAM_BASE);
b00052e4
AZ
1002}
1003
fbe1b595 1004static void spitz_init(ram_addr_t ram_size,
3023f332 1005 const char *boot_device,
b00052e4
AZ
1006 const char *kernel_filename, const char *kernel_cmdline,
1007 const char *initrd_filename, const char *cpu_model)
1008{
fbe1b595 1009 spitz_common_init(ram_size, kernel_filename,
4207117c 1010 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
b00052e4
AZ
1011}
1012
fbe1b595 1013static void borzoi_init(ram_addr_t ram_size,
3023f332 1014 const char *boot_device,
b00052e4
AZ
1015 const char *kernel_filename, const char *kernel_cmdline,
1016 const char *initrd_filename, const char *cpu_model)
1017{
fbe1b595 1018 spitz_common_init(ram_size, kernel_filename,
4207117c 1019 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
b00052e4
AZ
1020}
1021
fbe1b595 1022static void akita_init(ram_addr_t ram_size,
3023f332 1023 const char *boot_device,
b00052e4
AZ
1024 const char *kernel_filename, const char *kernel_cmdline,
1025 const char *initrd_filename, const char *cpu_model)
1026{
fbe1b595 1027 spitz_common_init(ram_size, kernel_filename,
4207117c 1028 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
b00052e4
AZ
1029}
1030
fbe1b595 1031static void terrier_init(ram_addr_t ram_size,
3023f332 1032 const char *boot_device,
b00052e4
AZ
1033 const char *kernel_filename, const char *kernel_cmdline,
1034 const char *initrd_filename, const char *cpu_model)
1035{
fbe1b595 1036 spitz_common_init(ram_size, kernel_filename,
4207117c 1037 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
b00052e4
AZ
1038}
1039
11be4b3e 1040static QEMUMachine akitapda_machine = {
4b32e168
AL
1041 .name = "akita",
1042 .desc = "Akita PDA (PXA270)",
1043 .init = akita_init,
b00052e4
AZ
1044};
1045
f80f9ec9 1046static QEMUMachine spitzpda_machine = {
4b32e168
AL
1047 .name = "spitz",
1048 .desc = "Spitz PDA (PXA270)",
1049 .init = spitz_init,
b00052e4
AZ
1050};
1051
f80f9ec9 1052static QEMUMachine borzoipda_machine = {
4b32e168
AL
1053 .name = "borzoi",
1054 .desc = "Borzoi PDA (PXA270)",
1055 .init = borzoi_init,
b00052e4
AZ
1056};
1057
f80f9ec9 1058static QEMUMachine terrierpda_machine = {
4b32e168
AL
1059 .name = "terrier",
1060 .desc = "Terrier PDA (PXA270)",
1061 .init = terrier_init,
b00052e4 1062};
a984a69e 1063
f80f9ec9
AL
1064static void spitz_machine_init(void)
1065{
1066 qemu_register_machine(&akitapda_machine);
1067 qemu_register_machine(&spitzpda_machine);
1068 qemu_register_machine(&borzoipda_machine);
1069 qemu_register_machine(&terrierpda_machine);
1070}
1071
1072machine_init(spitz_machine_init);
1073
a984a69e 1074static SSISlaveInfo corgi_ssp_info = {
074f2fff
GH
1075 .qdev.name = "corgi-ssp",
1076 .qdev.size = sizeof(CorgiSSPState),
a984a69e
PB
1077 .init = corgi_ssp_init,
1078 .transfer = corgi_ssp_transfer
1079};
1080
1081static SSISlaveInfo spitz_lcdtg_info = {
074f2fff
GH
1082 .qdev.name = "spitz-lcdtg",
1083 .qdev.size = sizeof(SpitzLCDTG),
a984a69e
PB
1084 .init = spitz_lcdtg_init,
1085 .transfer = spitz_lcdtg_transfer
1086};
1087
1088static void spitz_register_devices(void)
1089{
074f2fff
GH
1090 ssi_register_slave(&corgi_ssp_info);
1091 ssi_register_slave(&spitz_lcdtg_info);
a984a69e
PB
1092}
1093
1094device_init(spitz_register_devices)