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1/*
2 * PXA270-based Clamshell PDA platforms.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GNU GPL v2.
8 */
9
87ecb68b
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10#include "hw.h"
11#include "pxa.h"
12#include "arm-misc.h"
13#include "sysemu.h"
14#include "pcmcia.h"
15#include "i2c.h"
a984a69e 16#include "ssi.h"
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17#include "flash.h"
18#include "qemu-timer.h"
19#include "devices.h"
e33d8cdb 20#include "sharpsl.h"
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21#include "console.h"
22#include "block.h"
23#include "audio/audio.h"
24#include "boards.h"
2446333c 25#include "blockdev.h"
383d01c6 26#include "sysbus.h"
a6dc4c2d 27#include "exec-memory.h"
b00052e4 28
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29#undef REG_FMT
30#define REG_FMT "0x%02lx"
31
32/* Spitz Flash */
33#define FLASH_BASE 0x0c000000
34#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
35#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
36#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
37#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
38#define FLASH_ECCCLRR 0x10 /* Clear ECC */
39#define FLASH_FLASHIO 0x14 /* Flash I/O */
40#define FLASH_FLASHCTL 0x18 /* Flash Control */
41
42#define FLASHCTL_CE0 (1 << 0)
43#define FLASHCTL_CLE (1 << 1)
44#define FLASHCTL_ALE (1 << 2)
45#define FLASHCTL_WP (1 << 3)
46#define FLASHCTL_CE1 (1 << 4)
47#define FLASHCTL_RYBY (1 << 5)
48#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
49
bc24a225 50typedef struct {
34f9f0b5 51 SysBusDevice busdev;
d4220389 52 DeviceState *nand;
b00052e4 53 uint8_t ctl;
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DES
54 uint8_t manf_id;
55 uint8_t chip_id;
bc24a225
PB
56 ECCState ecc;
57} SLNANDState;
b00052e4 58
c227f099 59static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
b00052e4 60{
bc24a225 61 SLNANDState *s = (SLNANDState *) opaque;
b00052e4 62 int ryby;
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63
64 switch (addr) {
65#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
66 case FLASH_ECCLPLB:
67 return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
68 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
69
70#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
71 case FLASH_ECCLPUB:
72 return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
73 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
74
75 case FLASH_ECCCP:
76 return s->ecc.cp;
77
78 case FLASH_ECCCNTR:
79 return s->ecc.count & 0xff;
80
81 case FLASH_FLASHCTL:
82 nand_getpins(s->nand, &ryby);
83 if (ryby)
84 return s->ctl | FLASHCTL_RYBY;
85 else
86 return s->ctl;
87
88 case FLASH_FLASHIO:
89 return ecc_digest(&s->ecc, nand_getio(s->nand));
90
91 default:
a8b7063b 92 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
b00052e4
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93 }
94 return 0;
95}
96
c227f099 97static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
a5236105 98{
bc24a225 99 SLNANDState *s = (SLNANDState *) opaque;
a5236105
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100
101 if (addr == FLASH_FLASHIO)
102 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
103 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
104
105 return sl_readb(opaque, addr);
106}
107
c227f099 108static void sl_writeb(void *opaque, target_phys_addr_t addr,
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109 uint32_t value)
110{
bc24a225 111 SLNANDState *s = (SLNANDState *) opaque;
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112
113 switch (addr) {
114 case FLASH_ECCCLRR:
115 /* Value is ignored. */
116 ecc_reset(&s->ecc);
117 break;
118
119 case FLASH_FLASHCTL:
120 s->ctl = value & 0xff & ~FLASHCTL_RYBY;
121 nand_setpins(s->nand,
122 s->ctl & FLASHCTL_CLE,
123 s->ctl & FLASHCTL_ALE,
124 s->ctl & FLASHCTL_NCE,
125 s->ctl & FLASHCTL_WP,
126 0);
127 break;
128
129 case FLASH_FLASHIO:
130 nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
131 break;
132
133 default:
a8b7063b 134 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
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135 }
136}
137
138enum {
139 FLASH_128M,
140 FLASH_1024M,
141};
142
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DES
143static CPUReadMemoryFunc * const sl_readfn[] = {
144 sl_readb,
145 sl_readb,
146 sl_readl,
147};
148static CPUWriteMemoryFunc * const sl_writefn[] = {
149 sl_writeb,
150 sl_writeb,
151 sl_writeb,
152};
153
bc24a225 154static void sl_flash_register(PXA2xxState *cpu, int size)
b00052e4 155{
34f9f0b5
DES
156 DeviceState *dev;
157
158 dev = qdev_create(NULL, "sl-nand");
159
160 qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
161 if (size == FLASH_128M)
162 qdev_prop_set_uint8(dev, "chip_id", 0x73);
163 else if (size == FLASH_1024M)
164 qdev_prop_set_uint8(dev, "chip_id", 0xf1);
165
166 qdev_init_nofail(dev);
167 sysbus_mmio_map(sysbus_from_qdev(dev), 0, FLASH_BASE);
168}
169
170static int sl_nand_init(SysBusDevice *dev) {
b00052e4 171 int iomemtype;
bc24a225 172 SLNANDState *s;
522f253c 173 DriveInfo *nand;
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DES
174
175 s = FROM_SYSBUS(SLNANDState, dev);
176
b00052e4 177 s->ctl = 0;
522f253c
PM
178 nand = drive_get(IF_MTD, 0, 0);
179 s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id);
b00052e4 180
1eed09cb 181 iomemtype = cpu_register_io_memory(sl_readfn,
2507c12a 182 sl_writefn, s, DEVICE_NATIVE_ENDIAN);
aa941b94 183
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184 sysbus_init_mmio(dev, 0x40, iomemtype);
185
186 return 0;
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187}
188
189/* Spitz Keyboard */
190
191#define SPITZ_KEY_STROBE_NUM 11
192#define SPITZ_KEY_SENSE_NUM 7
193
194static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
195 12, 17, 91, 34, 36, 38, 39
196};
197
198static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
199 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
200};
201
202/* Eighth additional row maps the special keys */
203static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
204 { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
205 { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
206 { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
207 { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
208 { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
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209 { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
210 { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
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211 { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
212};
213
214#define SPITZ_GPIO_AK_INT 13 /* Remote control */
215#define SPITZ_GPIO_SYNC 16 /* Sync button */
216#define SPITZ_GPIO_ON_KEY 95 /* Power button */
217#define SPITZ_GPIO_SWA 97 /* Lid */
218#define SPITZ_GPIO_SWB 96 /* Tablet mode */
219
220/* The special buttons are mapped to unused keys */
221static const int spitz_gpiomap[5] = {
222 SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
223 SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
224};
b00052e4 225
bc24a225 226typedef struct {
7ef4227b 227 SysBusDevice busdev;
38641a52 228 qemu_irq sense[SPITZ_KEY_SENSE_NUM];
38641a52 229 qemu_irq gpiomap[5];
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230 int keymap[0x80];
231 uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
232 uint16_t strobe_state;
233 uint16_t sense_state;
234
235 uint16_t pre_map[0x100];
236 uint16_t modifiers;
237 uint16_t imodifiers;
238 uint8_t fifo[16];
239 int fifopos, fifolen;
240 QEMUTimer *kbdtimer;
bc24a225 241} SpitzKeyboardState;
b00052e4 242
bc24a225 243static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
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244{
245 int i;
246 uint16_t strobe, sense = 0;
247 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
248 strobe = s->keyrow[i] & s->strobe_state;
249 if (strobe) {
250 sense |= 1 << i;
251 if (!(s->sense_state & (1 << i)))
38641a52 252 qemu_irq_raise(s->sense[i]);
b00052e4 253 } else if (s->sense_state & (1 << i))
38641a52 254 qemu_irq_lower(s->sense[i]);
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255 }
256
257 s->sense_state = sense;
258}
259
38641a52 260static void spitz_keyboard_strobe(void *opaque, int line, int level)
b00052e4 261{
bc24a225 262 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
38641a52
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263
264 if (level)
265 s->strobe_state |= 1 << line;
266 else
267 s->strobe_state &= ~(1 << line);
268 spitz_keyboard_sense_update(s);
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269}
270
bc24a225 271static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
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272{
273 int spitz_keycode = s->keymap[keycode & 0x7f];
274 if (spitz_keycode == -1)
275 return;
276
277 /* Handle the additional keys */
278 if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
7ef4227b 279 qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80));
b00052e4
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280 return;
281 }
282
283 if (keycode & 0x80)
284 s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
285 else
286 s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
287
288 spitz_keyboard_sense_update(s);
289}
290
291#define SHIFT (1 << 7)
292#define CTRL (1 << 8)
293#define FN (1 << 9)
294
295#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
296
7ef4227b 297static void spitz_keyboard_handler(void *opaque, int keycode)
b00052e4 298{
7ef4227b 299 SpitzKeyboardState *s = opaque;
b00052e4
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300 uint16_t code;
301 int mapcode;
302 switch (keycode) {
303 case 0x2a: /* Left Shift */
304 s->modifiers |= 1;
305 break;
306 case 0xaa:
307 s->modifiers &= ~1;
308 break;
309 case 0x36: /* Right Shift */
310 s->modifiers |= 2;
311 break;
312 case 0xb6:
313 s->modifiers &= ~2;
314 break;
315 case 0x1d: /* Control */
316 s->modifiers |= 4;
317 break;
318 case 0x9d:
319 s->modifiers &= ~4;
320 break;
321 case 0x38: /* Alt */
322 s->modifiers |= 8;
323 break;
324 case 0xb8:
325 s->modifiers &= ~8;
326 break;
327 }
328
329 code = s->pre_map[mapcode = ((s->modifiers & 3) ?
330 (keycode | SHIFT) :
331 (keycode & ~SHIFT))];
332
333 if (code != mapcode) {
334#if 0
335 if ((code & SHIFT) && !(s->modifiers & 1))
336 QUEUE_KEY(0x2a | (keycode & 0x80));
337 if ((code & CTRL ) && !(s->modifiers & 4))
338 QUEUE_KEY(0x1d | (keycode & 0x80));
339 if ((code & FN ) && !(s->modifiers & 8))
340 QUEUE_KEY(0x38 | (keycode & 0x80));
341 if ((code & FN ) && (s->modifiers & 1))
342 QUEUE_KEY(0x2a | (~keycode & 0x80));
343 if ((code & FN ) && (s->modifiers & 2))
344 QUEUE_KEY(0x36 | (~keycode & 0x80));
345#else
346 if (keycode & 0x80) {
347 if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
348 QUEUE_KEY(0x2a | 0x80);
349 if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
350 QUEUE_KEY(0x1d | 0x80);
351 if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
352 QUEUE_KEY(0x38 | 0x80);
353 if ((s->imodifiers & 0x10) && (s->modifiers & 1))
354 QUEUE_KEY(0x2a);
355 if ((s->imodifiers & 0x20) && (s->modifiers & 2))
356 QUEUE_KEY(0x36);
357 s->imodifiers = 0;
358 } else {
359 if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
360 QUEUE_KEY(0x2a);
361 s->imodifiers |= 1;
362 }
363 if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
364 QUEUE_KEY(0x1d);
365 s->imodifiers |= 4;
366 }
367 if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
368 QUEUE_KEY(0x38);
369 s->imodifiers |= 8;
370 }
371 if ((code & FN ) && (s->modifiers & 1) &&
372 !(s->imodifiers & 0x10)) {
373 QUEUE_KEY(0x2a | 0x80);
374 s->imodifiers |= 0x10;
375 }
376 if ((code & FN ) && (s->modifiers & 2) &&
377 !(s->imodifiers & 0x20)) {
378 QUEUE_KEY(0x36 | 0x80);
379 s->imodifiers |= 0x20;
380 }
381 }
382#endif
383 }
384
385 QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
386}
387
388static void spitz_keyboard_tick(void *opaque)
389{
bc24a225 390 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
b00052e4
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391
392 if (s->fifolen) {
393 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
394 s->fifolen --;
395 if (s->fifopos >= 16)
396 s->fifopos = 0;
397 }
398
74475455 399 qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock) +
6ee093c9 400 get_ticks_per_sec() / 32);
b00052e4
AZ
401}
402
bc24a225 403static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
b00052e4
AZ
404{
405 int i;
406 for (i = 0; i < 0x100; i ++)
407 s->pre_map[i] = i;
408 s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
409 s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
410 s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
411 s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
412 s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
413 s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
414 s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
415 s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
416 s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
417 s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
418 s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
419 s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
420 s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
421 s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
422 s->pre_map[0x0d ] = 0x12 | FN; /* equal */
423 s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
424 s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
425 s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
2b76bdc9
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426 s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
427 s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
b00052e4
AZ
428 s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
429 s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
430 s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
431 s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
432 s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
433 s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
2b76bdc9 434 s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
b00052e4 435 s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
2b76bdc9 436 s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
b00052e4
AZ
437 s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
438 s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
439 s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
440
441 s->modifiers = 0;
442 s->imodifiers = 0;
443 s->fifopos = 0;
444 s->fifolen = 0;
b00052e4
AZ
445}
446
447#undef SHIFT
448#undef CTRL
449#undef FN
450
7ef4227b 451static int spitz_keyboard_post_load(void *opaque, int version_id)
aa941b94 452{
bc24a225 453 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
aa941b94
AZ
454
455 /* Release all pressed keys */
456 memset(s->keyrow, 0, sizeof(s->keyrow));
457 spitz_keyboard_sense_update(s);
458 s->modifiers = 0;
459 s->imodifiers = 0;
460 s->fifopos = 0;
461 s->fifolen = 0;
462
463 return 0;
464}
465
bc24a225 466static void spitz_keyboard_register(PXA2xxState *cpu)
b00052e4 467{
7ef4227b
DES
468 int i;
469 DeviceState *dev;
bc24a225 470 SpitzKeyboardState *s;
b00052e4 471
7ef4227b
DES
472 dev = sysbus_create_simple("spitz-keyboard", -1, NULL);
473 s = FROM_SYSBUS(SpitzKeyboardState, sysbus_from_qdev(dev));
b00052e4 474
38641a52 475 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
0bb53337 476 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(cpu->gpio, spitz_gpio_key_sense[i]));
38641a52
AZ
477
478 for (i = 0; i < 5; i ++)
0bb53337 479 s->gpiomap[i] = qdev_get_gpio_in(cpu->gpio, spitz_gpiomap[i]);
38641a52 480
7ef4227b
DES
481 if (!graphic_rotate)
482 s->gpiomap[4] = qemu_irq_invert(s->gpiomap[4]);
483
484 for (i = 0; i < 5; i++)
485 qemu_set_irq(s->gpiomap[i], 0);
486
b00052e4 487 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
0bb53337 488 qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
7ef4227b
DES
489 qdev_get_gpio_in(dev, i));
490
74475455 491 qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock));
7ef4227b
DES
492
493 qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
494}
495
496static int spitz_keyboard_init(SysBusDevice *dev)
497{
498 SpitzKeyboardState *s;
499 int i, j;
500
501 s = FROM_SYSBUS(SpitzKeyboardState, dev);
502
503 for (i = 0; i < 0x80; i ++)
504 s->keymap[i] = -1;
505 for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
506 for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
507 if (spitz_keymap[i][j] != -1)
508 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
b00052e4
AZ
509
510 spitz_keyboard_pre_map(s);
aa941b94 511
74475455 512 s->kbdtimer = qemu_new_timer_ns(vm_clock, spitz_keyboard_tick, s);
7ef4227b
DES
513 qdev_init_gpio_in(&dev->qdev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
514 qdev_init_gpio_out(&dev->qdev, s->sense, SPITZ_KEY_SENSE_NUM);
515
516 return 0;
b00052e4
AZ
517}
518
b00052e4
AZ
519/* LCD backlight controller */
520
521#define LCDTG_RESCTL 0x00
522#define LCDTG_PHACTRL 0x01
523#define LCDTG_DUTYCTRL 0x02
524#define LCDTG_POWERREG0 0x03
525#define LCDTG_POWERREG1 0x04
526#define LCDTG_GPOR3 0x05
527#define LCDTG_PICTRL 0x06
528#define LCDTG_POLCTRL 0x07
529
a984a69e
PB
530typedef struct {
531 SSISlave ssidev;
43842120
DES
532 uint32_t bl_intensity;
533 uint32_t bl_power;
a984a69e 534} SpitzLCDTG;
b00052e4 535
a984a69e 536static void spitz_bl_update(SpitzLCDTG *s)
b00052e4 537{
a984a69e
PB
538 if (s->bl_power && s->bl_intensity)
539 zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
b00052e4 540 else
89cdb6af 541 zaurus_printf("LCD Backlight now off\n");
b00052e4
AZ
542}
543
a984a69e
PB
544/* FIXME: Implement GPIO properly and remove this hack. */
545static SpitzLCDTG *spitz_lcdtg;
546
38641a52 547static inline void spitz_bl_bit5(void *opaque, int line, int level)
b00052e4 548{
a984a69e
PB
549 SpitzLCDTG *s = spitz_lcdtg;
550 int prev = s->bl_intensity;
b00052e4
AZ
551
552 if (level)
a984a69e 553 s->bl_intensity &= ~0x20;
b00052e4 554 else
a984a69e 555 s->bl_intensity |= 0x20;
b00052e4 556
a984a69e
PB
557 if (s->bl_power && prev != s->bl_intensity)
558 spitz_bl_update(s);
b00052e4
AZ
559}
560
38641a52 561static inline void spitz_bl_power(void *opaque, int line, int level)
b00052e4 562{
a984a69e
PB
563 SpitzLCDTG *s = spitz_lcdtg;
564 s->bl_power = !!level;
565 spitz_bl_update(s);
b00052e4
AZ
566}
567
a984a69e 568static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
b00052e4 569{
a984a69e
PB
570 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
571 int addr;
572 addr = value >> 5;
573 value &= 0x1f;
b00052e4
AZ
574
575 switch (addr) {
576 case LCDTG_RESCTL:
577 if (value)
89cdb6af 578 zaurus_printf("LCD in QVGA mode\n");
b00052e4 579 else
89cdb6af 580 zaurus_printf("LCD in VGA mode\n");
b00052e4
AZ
581 break;
582
583 case LCDTG_DUTYCTRL:
a984a69e
PB
584 s->bl_intensity &= ~0x1f;
585 s->bl_intensity |= value;
586 if (s->bl_power)
587 spitz_bl_update(s);
b00052e4
AZ
588 break;
589
590 case LCDTG_POWERREG0:
591 /* Set common voltage to M62332FP */
592 break;
593 }
a984a69e
PB
594 return 0;
595}
596
81a322d4 597static int spitz_lcdtg_init(SSISlave *dev)
a984a69e
PB
598{
599 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
600
601 spitz_lcdtg = s;
602 s->bl_power = 0;
603 s->bl_intensity = 0x20;
604
81a322d4 605 return 0;
b00052e4
AZ
606}
607
608/* SSP devices */
609
610#define CORGI_SSP_PORT 2
611
612#define SPITZ_GPIO_LCDCON_CS 53
613#define SPITZ_GPIO_ADS7846_CS 14
614#define SPITZ_GPIO_MAX1111_CS 20
615#define SPITZ_GPIO_TP_INT 11
616
a984a69e 617static DeviceState *max1111;
b00052e4
AZ
618
619/* "Demux" the signal based on current chipselect */
a984a69e
PB
620typedef struct {
621 SSISlave ssidev;
622 SSIBus *bus[3];
43842120 623 uint32_t enable[3];
a984a69e 624} CorgiSSPState;
b00052e4 625
a984a69e 626static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
b00052e4 627{
a984a69e
PB
628 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
629 int i;
630
631 for (i = 0; i < 3; i++) {
632 if (s->enable[i]) {
633 return ssi_transfer(s->bus[i], value);
634 }
635 }
636 return 0;
b00052e4
AZ
637}
638
38641a52 639static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
b00052e4 640{
a984a69e
PB
641 CorgiSSPState *s = (CorgiSSPState *)opaque;
642 assert(line >= 0 && line < 3);
643 s->enable[line] = !level;
b00052e4
AZ
644}
645
646#define MAX1111_BATT_VOLT 1
647#define MAX1111_BATT_TEMP 2
648#define MAX1111_ACIN_VOLT 3
649
650#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
651#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
652#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
653
38641a52 654static void spitz_adc_temp_on(void *opaque, int line, int level)
b00052e4
AZ
655{
656 if (!max1111)
657 return;
658
659 if (level)
660 max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
661 else
662 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
663}
664
81a322d4 665static int corgi_ssp_init(SSISlave *dev)
a984a69e
PB
666{
667 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
668
669 qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);
02e2da45
PB
670 s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
671 s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
672 s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
a984a69e 673
81a322d4 674 return 0;
a984a69e
PB
675}
676
bc24a225 677static void spitz_ssp_attach(PXA2xxState *cpu)
b00052e4 678{
a984a69e
PB
679 DeviceState *mux;
680 DeviceState *dev;
681 void *bus;
682
683 mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
38641a52 684
a984a69e 685 bus = qdev_get_child_bus(mux, "ssi0");
22ed1d34 686 ssi_create_slave(bus, "spitz-lcdtg");
b00052e4 687
a984a69e
PB
688 bus = qdev_get_child_bus(mux, "ssi1");
689 dev = ssi_create_slave(bus, "ads7846");
690 qdev_connect_gpio_out(dev, 0,
0bb53337 691 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
b00052e4 692
a984a69e
PB
693 bus = qdev_get_child_bus(mux, "ssi2");
694 max1111 = ssi_create_slave(bus, "max1111");
b00052e4
AZ
695 max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
696 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
697 max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
698
0bb53337 699 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
a984a69e 700 qdev_get_gpio_in(mux, 0));
0bb53337 701 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
a984a69e 702 qdev_get_gpio_in(mux, 1));
0bb53337 703 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
a984a69e 704 qdev_get_gpio_in(mux, 2));
b00052e4
AZ
705}
706
707/* CF Microdrive */
708
bc24a225 709static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
b00052e4 710{
bc24a225 711 PCMCIACardState *md;
751c6a17 712 DriveInfo *dinfo;
b00052e4 713
751c6a17 714 dinfo = drive_get(IF_IDE, 0, 0);
124386cc 715 if (!dinfo || dinfo->media_cd)
e4bcb14c 716 return;
124386cc
MA
717 md = dscm1xxxx_init(dinfo);
718 pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
b00052e4
AZ
719}
720
adb86c37
AZ
721/* Wm8750 and Max7310 on I2C */
722
723#define AKITA_MAX_ADDR 0x18
611d7189
AZ
724#define SPITZ_WM_ADDRL 0x1b
725#define SPITZ_WM_ADDRH 0x1a
adb86c37
AZ
726
727#define SPITZ_GPIO_WM 5
728
38641a52 729static void spitz_wm8750_addr(void *opaque, int line, int level)
adb86c37
AZ
730{
731 i2c_slave *wm = (i2c_slave *) opaque;
732 if (level)
733 i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
734 else
735 i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
736}
adb86c37 737
bc24a225 738static void spitz_i2c_setup(PXA2xxState *cpu)
adb86c37
AZ
739{
740 /* Attach the CPU on one end of our I2C bus. */
741 i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
742
cdbe40ca 743 DeviceState *wm;
adb86c37 744
adb86c37 745 /* Attach a WM8750 to the bus */
cdbe40ca 746 wm = i2c_create_slave(bus, "wm8750", 0);
adb86c37 747
38641a52 748 spitz_wm8750_addr(wm, 0, 0);
0bb53337 749 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_WM,
38641a52 750 qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
adb86c37
AZ
751 /* .. and to the sound interface. */
752 cpu->i2s->opaque = wm;
753 cpu->i2s->codec_out = wm8750_dac_dat;
754 cpu->i2s->codec_in = wm8750_adc_dat;
755 wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
adb86c37
AZ
756}
757
bc24a225 758static void spitz_akita_i2c_setup(PXA2xxState *cpu)
adb86c37
AZ
759{
760 /* Attach a Max7310 to Akita I2C bus. */
6c0bd6bd
PB
761 i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
762 AKITA_MAX_ADDR);
adb86c37
AZ
763}
764
b00052e4
AZ
765/* Other peripherals */
766
38641a52 767static void spitz_out_switch(void *opaque, int line, int level)
b00052e4 768{
38641a52
AZ
769 switch (line) {
770 case 0:
89cdb6af 771 zaurus_printf("Charging %s.\n", level ? "off" : "on");
38641a52
AZ
772 break;
773 case 1:
89cdb6af 774 zaurus_printf("Discharging %s.\n", level ? "on" : "off");
38641a52
AZ
775 break;
776 case 2:
89cdb6af 777 zaurus_printf("Green LED %s.\n", level ? "on" : "off");
38641a52
AZ
778 break;
779 case 3:
89cdb6af 780 zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
38641a52
AZ
781 break;
782 case 4:
783 spitz_bl_bit5(opaque, line, level);
784 break;
785 case 5:
786 spitz_bl_power(opaque, line, level);
787 break;
788 case 6:
789 spitz_adc_temp_on(opaque, line, level);
790 break;
791 }
b00052e4
AZ
792}
793
794#define SPITZ_SCP_LED_GREEN 1
795#define SPITZ_SCP_JK_B 2
796#define SPITZ_SCP_CHRG_ON 3
797#define SPITZ_SCP_MUTE_L 4
798#define SPITZ_SCP_MUTE_R 5
799#define SPITZ_SCP_CF_POWER 6
800#define SPITZ_SCP_LED_ORANGE 7
801#define SPITZ_SCP_JK_A 8
802#define SPITZ_SCP_ADC_TEMP_ON 9
803#define SPITZ_SCP2_IR_ON 1
804#define SPITZ_SCP2_AKIN_PULLUP 2
805#define SPITZ_SCP2_BACKLIGHT_CONT 7
806#define SPITZ_SCP2_BACKLIGHT_ON 8
807#define SPITZ_SCP2_MIC_BIAS 9
808
bc24a225 809static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
383d01c6 810 DeviceState *scp0, DeviceState *scp1)
b00052e4 811{
38641a52
AZ
812 qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
813
383d01c6
DES
814 qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
815 qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
816 qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
817 qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
b00052e4 818
e33d8cdb 819 if (scp1) {
383d01c6
DES
820 qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
821 qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
b00052e4
AZ
822 }
823
383d01c6 824 qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
b00052e4
AZ
825}
826
827#define SPITZ_GPIO_HSYNC 22
828#define SPITZ_GPIO_SD_DETECT 9
829#define SPITZ_GPIO_SD_WP 81
830#define SPITZ_GPIO_ON_RESET 89
831#define SPITZ_GPIO_BAT_COVER 90
832#define SPITZ_GPIO_CF1_IRQ 105
833#define SPITZ_GPIO_CF1_CD 94
834#define SPITZ_GPIO_CF2_IRQ 106
835#define SPITZ_GPIO_CF2_CD 93
836
38641a52 837static int spitz_hsync;
b00052e4 838
38641a52 839static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
b00052e4 840{
bc24a225 841 PXA2xxState *cpu = (PXA2xxState *) opaque;
0bb53337 842 qemu_set_irq(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_HSYNC), spitz_hsync);
b00052e4
AZ
843 spitz_hsync ^= 1;
844}
845
bc24a225 846static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
b00052e4 847{
38641a52 848 qemu_irq lcd_hsync;
b00052e4
AZ
849 /*
850 * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
851 * read to satisfy broken guests that poll-wait for hsync.
852 * Simulating a real hsync event would be less practical and
853 * wouldn't guarantee that a guest ever exits the loop.
854 */
855 spitz_hsync = 0;
38641a52
AZ
856 lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
857 pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
858 pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
b00052e4
AZ
859
860 /* MMC/SD host */
02ce600c 861 pxa2xx_mmci_handlers(cpu->mmc,
0bb53337
DES
862 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_WP),
863 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_DETECT));
b00052e4
AZ
864
865 /* Battery lock always closed */
0bb53337 866 qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
b00052e4
AZ
867
868 /* Handle reset */
0bb53337 869 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
b00052e4
AZ
870
871 /* PCMCIA signals: card's IRQ and Card-Detect */
b00052e4 872 if (slots >= 1)
38641a52 873 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
0bb53337
DES
874 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_IRQ),
875 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_CD));
b00052e4 876 if (slots >= 2)
38641a52 877 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
0bb53337
DES
878 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_IRQ),
879 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_CD));
b00052e4
AZ
880}
881
b00052e4
AZ
882/* Board init. */
883enum spitz_model_e { spitz, akita, borzoi, terrier };
884
7fb4fdcf
AZ
885#define SPITZ_RAM 0x04000000
886#define SPITZ_ROM 0x00800000
887
f93eb9ff
AZ
888static struct arm_boot_info spitz_binfo = {
889 .loader_start = PXA2XX_SDRAM_BASE,
890 .ram_size = 0x04000000,
891};
892
c227f099 893static void spitz_common_init(ram_addr_t ram_size,
3023f332 894 const char *kernel_filename,
b00052e4 895 const char *kernel_cmdline, const char *initrd_filename,
4207117c 896 const char *cpu_model, enum spitz_model_e model, int arm_id)
b00052e4 897{
bc24a225 898 PXA2xxState *cpu;
383d01c6 899 DeviceState *scp0, *scp1 = NULL;
a6dc4c2d 900 MemoryRegion *address_space_mem = get_system_memory();
b00052e4 901
4207117c
AZ
902 if (!cpu_model)
903 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
b00052e4 904
d95b2f8d 905 /* Setup CPU & memory */
a6dc4c2d 906 cpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
b00052e4
AZ
907
908 sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
909
7fb4fdcf 910 cpu_register_physical_memory(0, SPITZ_ROM,
1724f049 911 qemu_ram_alloc(NULL, "spitz.rom", SPITZ_ROM) | IO_MEM_ROM);
b00052e4
AZ
912
913 /* Setup peripherals */
914 spitz_keyboard_register(cpu);
915
916 spitz_ssp_attach(cpu);
917
383d01c6 918 scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
e33d8cdb 919 if (model != akita) {
383d01c6 920 scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
e33d8cdb 921 }
b00052e4 922
e33d8cdb 923 spitz_scoop_gpio_setup(cpu, scp0, scp1);
b00052e4
AZ
924
925 spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
926
adb86c37
AZ
927 spitz_i2c_setup(cpu);
928
929 if (model == akita)
930 spitz_akita_i2c_setup(cpu);
931
b00052e4 932 if (model == terrier)
bf5ee248 933 /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
15b18ec2 934 spitz_microdrive_attach(cpu, 1);
b00052e4 935 else if (model != akita)
15b18ec2
AZ
936 /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
937 spitz_microdrive_attach(cpu, 0);
b00052e4 938
f93eb9ff
AZ
939 spitz_binfo.kernel_filename = kernel_filename;
940 spitz_binfo.kernel_cmdline = kernel_cmdline;
941 spitz_binfo.initrd_filename = initrd_filename;
942 spitz_binfo.board_id = arm_id;
943 arm_load_kernel(cpu->env, &spitz_binfo);
f78630ab 944 sl_bootparam_write(SL_PXA_PARAM_BASE);
b00052e4
AZ
945}
946
c227f099 947static void spitz_init(ram_addr_t ram_size,
3023f332 948 const char *boot_device,
b00052e4
AZ
949 const char *kernel_filename, const char *kernel_cmdline,
950 const char *initrd_filename, const char *cpu_model)
951{
fbe1b595 952 spitz_common_init(ram_size, kernel_filename,
4207117c 953 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
b00052e4
AZ
954}
955
c227f099 956static void borzoi_init(ram_addr_t ram_size,
3023f332 957 const char *boot_device,
b00052e4
AZ
958 const char *kernel_filename, const char *kernel_cmdline,
959 const char *initrd_filename, const char *cpu_model)
960{
fbe1b595 961 spitz_common_init(ram_size, kernel_filename,
4207117c 962 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
b00052e4
AZ
963}
964
c227f099 965static void akita_init(ram_addr_t ram_size,
3023f332 966 const char *boot_device,
b00052e4
AZ
967 const char *kernel_filename, const char *kernel_cmdline,
968 const char *initrd_filename, const char *cpu_model)
969{
fbe1b595 970 spitz_common_init(ram_size, kernel_filename,
4207117c 971 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
b00052e4
AZ
972}
973
c227f099 974static void terrier_init(ram_addr_t ram_size,
3023f332 975 const char *boot_device,
b00052e4
AZ
976 const char *kernel_filename, const char *kernel_cmdline,
977 const char *initrd_filename, const char *cpu_model)
978{
fbe1b595 979 spitz_common_init(ram_size, kernel_filename,
4207117c 980 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
b00052e4
AZ
981}
982
11be4b3e 983static QEMUMachine akitapda_machine = {
4b32e168
AL
984 .name = "akita",
985 .desc = "Akita PDA (PXA270)",
986 .init = akita_init,
b00052e4
AZ
987};
988
f80f9ec9 989static QEMUMachine spitzpda_machine = {
4b32e168
AL
990 .name = "spitz",
991 .desc = "Spitz PDA (PXA270)",
992 .init = spitz_init,
b00052e4
AZ
993};
994
f80f9ec9 995static QEMUMachine borzoipda_machine = {
4b32e168
AL
996 .name = "borzoi",
997 .desc = "Borzoi PDA (PXA270)",
998 .init = borzoi_init,
b00052e4
AZ
999};
1000
f80f9ec9 1001static QEMUMachine terrierpda_machine = {
4b32e168
AL
1002 .name = "terrier",
1003 .desc = "Terrier PDA (PXA270)",
1004 .init = terrier_init,
b00052e4 1005};
a984a69e 1006
f80f9ec9
AL
1007static void spitz_machine_init(void)
1008{
1009 qemu_register_machine(&akitapda_machine);
1010 qemu_register_machine(&spitzpda_machine);
1011 qemu_register_machine(&borzoipda_machine);
1012 qemu_register_machine(&terrierpda_machine);
1013}
1014
1015machine_init(spitz_machine_init);
1016
7ef4227b
DES
1017static bool is_version_0(void *opaque, int version_id)
1018{
1019 return version_id == 0;
1020}
1021
34f9f0b5
DES
1022static VMStateDescription vmstate_sl_nand_info = {
1023 .name = "sl-nand",
1024 .version_id = 0,
1025 .minimum_version_id = 0,
1026 .minimum_version_id_old = 0,
1027 .fields = (VMStateField []) {
1028 VMSTATE_UINT8(ctl, SLNANDState),
1029 VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
1030 VMSTATE_END_OF_LIST(),
1031 },
1032};
1033
1034static SysBusDeviceInfo sl_nand_info = {
1035 .init = sl_nand_init,
1036 .qdev.name = "sl-nand",
1037 .qdev.size = sizeof(SLNANDState),
1038 .qdev.vmsd = &vmstate_sl_nand_info,
1039 .qdev.props = (Property []) {
1040 DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG),
1041 DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1),
1042 DEFINE_PROP_END_OF_LIST(),
1043 },
1044};
1045
7ef4227b
DES
1046static VMStateDescription vmstate_spitz_kbd = {
1047 .name = "spitz-keyboard",
1048 .version_id = 1,
1049 .minimum_version_id = 0,
1050 .minimum_version_id_old = 0,
1051 .post_load = spitz_keyboard_post_load,
1052 .fields = (VMStateField []) {
1053 VMSTATE_UINT16(sense_state, SpitzKeyboardState),
1054 VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
1055 VMSTATE_UNUSED_TEST(is_version_0, 5),
1056 VMSTATE_END_OF_LIST(),
1057 },
1058};
1059
1060static SysBusDeviceInfo spitz_keyboard_info = {
1061 .init = spitz_keyboard_init,
1062 .qdev.name = "spitz-keyboard",
1063 .qdev.size = sizeof(SpitzKeyboardState),
1064 .qdev.vmsd = &vmstate_spitz_kbd,
1065 .qdev.props = (Property []) {
1066 DEFINE_PROP_END_OF_LIST(),
1067 },
1068};
1069
43842120
DES
1070static const VMStateDescription vmstate_corgi_ssp_regs = {
1071 .name = "corgi-ssp",
1072 .version_id = 1,
1073 .minimum_version_id = 1,
1074 .minimum_version_id_old = 1,
1075 .fields = (VMStateField []) {
1076 VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
1077 VMSTATE_END_OF_LIST(),
1078 }
1079};
1080
a984a69e 1081static SSISlaveInfo corgi_ssp_info = {
074f2fff
GH
1082 .qdev.name = "corgi-ssp",
1083 .qdev.size = sizeof(CorgiSSPState),
43842120 1084 .qdev.vmsd = &vmstate_corgi_ssp_regs,
a984a69e
PB
1085 .init = corgi_ssp_init,
1086 .transfer = corgi_ssp_transfer
1087};
1088
43842120
DES
1089static const VMStateDescription vmstate_spitz_lcdtg_regs = {
1090 .name = "spitz-lcdtg",
1091 .version_id = 1,
1092 .minimum_version_id = 1,
1093 .minimum_version_id_old = 1,
1094 .fields = (VMStateField []) {
1095 VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
1096 VMSTATE_UINT32(bl_power, SpitzLCDTG),
1097 VMSTATE_END_OF_LIST(),
1098 }
1099};
1100
a984a69e 1101static SSISlaveInfo spitz_lcdtg_info = {
074f2fff
GH
1102 .qdev.name = "spitz-lcdtg",
1103 .qdev.size = sizeof(SpitzLCDTG),
43842120 1104 .qdev.vmsd = &vmstate_spitz_lcdtg_regs,
a984a69e
PB
1105 .init = spitz_lcdtg_init,
1106 .transfer = spitz_lcdtg_transfer
1107};
1108
1109static void spitz_register_devices(void)
1110{
074f2fff
GH
1111 ssi_register_slave(&corgi_ssp_info);
1112 ssi_register_slave(&spitz_lcdtg_info);
7ef4227b 1113 sysbus_register_withprop(&spitz_keyboard_info);
34f9f0b5 1114 sysbus_register_withprop(&sl_nand_info);
a984a69e
PB
1115}
1116
1117device_init(spitz_register_devices)