[qemu.git] / hw / ssi / omap_spi.c

/*
 * TI OMAP processor's Multichannel SPI emulation.
 *
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Original code for OMAP2 by Andrzej Zaborowski <andrew@openedhand.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) any later version of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */
#include "hw/hw.h"
#include "hw/arm/omap.h"

/* Multichannel SPI */
struct omap_mcspi_s {
    MemoryRegion iomem;
    qemu_irq irq;
    int chnum;

    uint32_t sysconfig;
    uint32_t systest;
    uint32_t irqst;
    uint32_t irqen;
    uint32_t wken;
    uint32_t control;

    struct omap_mcspi_ch_s {
        qemu_irq txdrq;
        qemu_irq rxdrq;
        uint32_t (*txrx)(void *opaque, uint32_t, int);
        void *opaque;

        uint32_t tx;
        uint32_t rx;

        uint32_t config;
        uint32_t status;
        uint32_t control;
    } ch[4];
};

static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
{
    qemu_set_irq(s->irq, s->irqst & s->irqen);
}

static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
{
    qemu_set_irq(ch->txdrq,
                    (ch->control & 1) &&		/* EN */
                    (ch->config & (1 << 14)) &&		/* DMAW */
                    (ch->status & (1 << 1)) &&		/* TXS */
                    ((ch->config >> 12) & 3) != 1);	/* TRM */
    qemu_set_irq(ch->rxdrq,
                    (ch->control & 1) &&		/* EN */
                    (ch->config & (1 << 15)) &&		/* DMAW */
                    (ch->status & (1 << 0)) &&		/* RXS */
                    ((ch->config >> 12) & 3) != 2);	/* TRM */
}

static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
{
    struct omap_mcspi_ch_s *ch = s->ch + chnum;

    if (!(ch->control & 1))				/* EN */
        return;
    if ((ch->status & (1 << 0)) &&			/* RXS */
                    ((ch->config >> 12) & 3) != 2 &&	/* TRM */
                    !(ch->config & (1 << 19)))		/* TURBO */
        goto intr_update;
    if ((ch->status & (1 << 1)) &&			/* TXS */
                    ((ch->config >> 12) & 3) != 1)	/* TRM */
        goto intr_update;

    if (!(s->control & 1) ||				/* SINGLE */
                    (ch->config & (1 << 20))) {		/* FORCE */
        if (ch->txrx)
            ch->rx = ch->txrx(ch->opaque, ch->tx,	/* WL */
                            1 + (0x1f & (ch->config >> 7)));
    }

    ch->tx = 0;
    ch->status |= 1 << 2;				/* EOT */
    ch->status |= 1 << 1;				/* TXS */
    if (((ch->config >> 12) & 3) != 2)			/* TRM */
        ch->status |= 1 << 0;				/* RXS */

intr_update:
    if ((ch->status & (1 << 0)) &&			/* RXS */
                    ((ch->config >> 12) & 3) != 2 &&	/* TRM */
                    !(ch->config & (1 << 19)))		/* TURBO */
        s->irqst |= 1 << (2 + 4 * chnum);		/* RX_FULL */
    if ((ch->status & (1 << 1)) &&			/* TXS */
                    ((ch->config >> 12) & 3) != 1)	/* TRM */
        s->irqst |= 1 << (0 + 4 * chnum);		/* TX_EMPTY */
    omap_mcspi_interrupt_update(s);
    omap_mcspi_dmarequest_update(ch);
}

void omap_mcspi_reset(struct omap_mcspi_s *s)
{
    int ch;

    s->sysconfig = 0;
    s->systest = 0;
    s->irqst = 0;
    s->irqen = 0;
    s->wken = 0;
    s->control = 4;

    for (ch = 0; ch < 4; ch ++) {
        s->ch[ch].config = 0x060000;
        s->ch[ch].status = 2;				/* TXS */
        s->ch[ch].control = 0;

        omap_mcspi_dmarequest_update(s->ch + ch);
    }

    omap_mcspi_interrupt_update(s);
}

static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
                                unsigned size)
{
    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
    int ch = 0;
    uint32_t ret;

    if (size != 4) {
        return omap_badwidth_read32(opaque, addr);
    }

    switch (addr) {
    case 0x00:	/* MCSPI_REVISION */
        return 0x91;

    case 0x10:	/* MCSPI_SYSCONFIG */
        return s->sysconfig;

    case 0x14:	/* MCSPI_SYSSTATUS */
        return 1;					/* RESETDONE */

    case 0x18:	/* MCSPI_IRQSTATUS */
        return s->irqst;

    case 0x1c:	/* MCSPI_IRQENABLE */
        return s->irqen;

    case 0x20:	/* MCSPI_WAKEUPENABLE */
        return s->wken;

    case 0x24:	/* MCSPI_SYST */
        return s->systest;

    case 0x28:	/* MCSPI_MODULCTRL */
        return s->control;

    case 0x68: ch ++;
        /* fall through */
    case 0x54: ch ++;
        /* fall through */
    case 0x40: ch ++;
        /* fall through */
    case 0x2c:	/* MCSPI_CHCONF */
        return s->ch[ch].config;

    case 0x6c: ch ++;
        /* fall through */
    case 0x58: ch ++;
        /* fall through */
    case 0x44: ch ++;
        /* fall through */
    case 0x30:	/* MCSPI_CHSTAT */
        return s->ch[ch].status;

    case 0x70: ch ++;
        /* fall through */
    case 0x5c: ch ++;
        /* fall through */
    case 0x48: ch ++;
        /* fall through */
    case 0x34:	/* MCSPI_CHCTRL */
        return s->ch[ch].control;

    case 0x74: ch ++;
        /* fall through */
    case 0x60: ch ++;
        /* fall through */
    case 0x4c: ch ++;
        /* fall through */
    case 0x38:	/* MCSPI_TX */
        return s->ch[ch].tx;

    case 0x78: ch ++;
        /* fall through */
    case 0x64: ch ++;
        /* fall through */
    case 0x50: ch ++;
        /* fall through */
    case 0x3c:	/* MCSPI_RX */
        s->ch[ch].status &= ~(1 << 0);			/* RXS */
        ret = s->ch[ch].rx;
        omap_mcspi_transfer_run(s, ch);
        return ret;
    }

    OMAP_BAD_REG(addr);
    return 0;
}

static void omap_mcspi_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
{
    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
    int ch = 0;

    if (size != 4) {
        return omap_badwidth_write32(opaque, addr, value);
    }

    switch (addr) {
    case 0x00:	/* MCSPI_REVISION */
    case 0x14:	/* MCSPI_SYSSTATUS */
    case 0x30:	/* MCSPI_CHSTAT0 */
    case 0x3c:	/* MCSPI_RX0 */
    case 0x44:	/* MCSPI_CHSTAT1 */
    case 0x50:	/* MCSPI_RX1 */
    case 0x58:	/* MCSPI_CHSTAT2 */
    case 0x64:	/* MCSPI_RX2 */
    case 0x6c:	/* MCSPI_CHSTAT3 */
    case 0x78:	/* MCSPI_RX3 */
        OMAP_RO_REG(addr);
        return;

    case 0x10:	/* MCSPI_SYSCONFIG */
        if (value & (1 << 1))				/* SOFTRESET */
            omap_mcspi_reset(s);
        s->sysconfig = value & 0x31d;
        break;

    case 0x18:	/* MCSPI_IRQSTATUS */
        if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
            s->irqst &= ~value;
            omap_mcspi_interrupt_update(s);
        }
        break;

    case 0x1c:	/* MCSPI_IRQENABLE */
        s->irqen = value & 0x1777f;
        omap_mcspi_interrupt_update(s);
        break;

    case 0x20:	/* MCSPI_WAKEUPENABLE */
        s->wken = value & 1;
        break;

    case 0x24:	/* MCSPI_SYST */
        if (s->control & (1 << 3))			/* SYSTEM_TEST */
            if (value & (1 << 11)) {			/* SSB */
                s->irqst |= 0x1777f;
                omap_mcspi_interrupt_update(s);
            }
        s->systest = value & 0xfff;
        break;

    case 0x28:	/* MCSPI_MODULCTRL */
        if (value & (1 << 3))				/* SYSTEM_TEST */
            if (s->systest & (1 << 11)) {		/* SSB */
                s->irqst |= 0x1777f;
                omap_mcspi_interrupt_update(s);
            }
        s->control = value & 0xf;
        break;

    case 0x68: ch ++;
        /* fall through */
    case 0x54: ch ++;
        /* fall through */
    case 0x40: ch ++;
        /* fall through */
    case 0x2c:	/* MCSPI_CHCONF */
        if ((value ^ s->ch[ch].config) & (3 << 14))	/* DMAR | DMAW */
            omap_mcspi_dmarequest_update(s->ch + ch);
        if (((value >> 12) & 3) == 3)			/* TRM */
            fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
        if (((value >> 7) & 0x1f) < 3)			/* WL */
            fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
                            __FUNCTION__, (value >> 7) & 0x1f);
        s->ch[ch].config = value & 0x7fffff;
        break;

    case 0x70: ch ++;
        /* fall through */
    case 0x5c: ch ++;
        /* fall through */
    case 0x48: ch ++;
        /* fall through */
    case 0x34:	/* MCSPI_CHCTRL */
        if (value & ~s->ch[ch].control & 1) {		/* EN */
            s->ch[ch].control |= 1;
            omap_mcspi_transfer_run(s, ch);
        } else
            s->ch[ch].control = value & 1;
        break;

    case 0x74: ch ++;
        /* fall through */
    case 0x60: ch ++;
        /* fall through */
    case 0x4c: ch ++;
        /* fall through */
    case 0x38:	/* MCSPI_TX */
        s->ch[ch].tx = value;
        s->ch[ch].status &= ~(1 << 1);			/* TXS */
        omap_mcspi_transfer_run(s, ch);
        break;

    default:
        OMAP_BAD_REG(addr);
        return;
    }
}

static const MemoryRegionOps omap_mcspi_ops = {
    .read = omap_mcspi_read,
    .write = omap_mcspi_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
                qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
    struct omap_mcspi_s *s = (struct omap_mcspi_s *)
            g_malloc0(sizeof(struct omap_mcspi_s));
    struct omap_mcspi_ch_s *ch = s->ch;

    s->irq = irq;
    s->chnum = chnum;
    while (chnum --) {
        ch->txdrq = *drq ++;
        ch->rxdrq = *drq ++;
        ch ++;
    }
    omap_mcspi_reset(s);

    memory_region_init_io(&s->iomem, NULL, &omap_mcspi_ops, s, "omap.mcspi",
                          omap_l4_region_size(ta, 0));
    omap_l4_attach(ta, 0, &s->iomem);

    return s;
}

void omap_mcspi_attach(struct omap_mcspi_s *s,
                uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
                int chipselect)
{
    if (chipselect < 0 || chipselect >= s->chnum)
        hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);

    s->ch[chipselect].txrx = txrx;
    s->ch[chipselect].opaque = opaque;
}
Commit	Line	Data
2d08cc7c	1	/*
	2	* TI OMAP processor's Multichannel SPI emulation.
	3	*
	4	* Copyright (C) 2007-2009 Nokia Corporation
	5	*
	6	* Original code for OMAP2 by Andrzej Zaborowski <andrew@openedhand.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 or
	11	* (at your option) any later version of the License.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, write to the Free Software Foundation, Inc.,
	20	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	21	*/
83c9f4ca	22	#include "hw/hw.h"
0d09e41a	23	#include "hw/arm/omap.h"
2d08cc7c	24
	25	/* Multichannel SPI */
	26	struct omap_mcspi_s {
1a072690	27	MemoryRegion iomem;
2d08cc7c	28	qemu_irq irq;
	29	int chnum;
	30
	31	uint32_t sysconfig;
	32	uint32_t systest;
	33	uint32_t irqst;
	34	uint32_t irqen;
	35	uint32_t wken;
	36	uint32_t control;
	37
	38	struct omap_mcspi_ch_s {
	39	qemu_irq txdrq;
	40	qemu_irq rxdrq;
	41	uint32_t (txrx)(void opaque, uint32_t, int);
	42	void *opaque;
	43
	44	uint32_t tx;
	45	uint32_t rx;
	46
	47	uint32_t config;
	48	uint32_t status;
	49	uint32_t control;
	50	} ch[4];
	51	};
	52
	53	static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
	54	{
	55	qemu_set_irq(s->irq, s->irqst & s->irqen);
	56	}
	57
	58	static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
	59	{
	60	qemu_set_irq(ch->txdrq,
	61	(ch->control & 1) && /* EN */
	62	(ch->config & (1 << 14)) && /* DMAW */
	63	(ch->status & (1 << 1)) && /* TXS */
	64	((ch->config >> 12) & 3) != 1); /* TRM */
	65	qemu_set_irq(ch->rxdrq,
	66	(ch->control & 1) && /* EN */
	67	(ch->config & (1 << 15)) && /* DMAW */
	68	(ch->status & (1 << 0)) && /* RXS */
	69	((ch->config >> 12) & 3) != 2); /* TRM */
	70	}
	71
	72	static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
	73	{
	74	struct omap_mcspi_ch_s *ch = s->ch + chnum;
	75
	76	if (!(ch->control & 1)) /* EN */
	77	return;
	78	if ((ch->status & (1 << 0)) && /* RXS */
	79	((ch->config >> 12) & 3) != 2 && /* TRM */
	80	!(ch->config & (1 << 19))) /* TURBO */
	81	goto intr_update;
	82	if ((ch->status & (1 << 1)) && /* TXS */
	83	((ch->config >> 12) & 3) != 1) /* TRM */
	84	goto intr_update;
	85
	86	if (!(s->control & 1) \|\| /* SINGLE */
	87	(ch->config & (1 << 20))) { /* FORCE */
	88	if (ch->txrx)
	89	ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
	90	1 + (0x1f & (ch->config >> 7)));
	91	}
92
93	ch->tx = 0;
94	ch->status \|= 1 << 2; /* EOT */
95	ch->status \|= 1 << 1; /* TXS */
96	if (((ch->config >> 12) & 3) != 2) /* TRM */
97	ch->status \|= 1 << 0; /* RXS */
98
99	intr_update:
100	if ((ch->status & (1 << 0)) && /* RXS */
101	((ch->config >> 12) & 3) != 2 && /* TRM */
102	!(ch->config & (1 << 19))) /* TURBO */
103	s->irqst \|= 1 << (2 + 4 * chnum); /* RX_FULL */
104	if ((ch->status & (1 << 1)) && /* TXS */
105	((ch->config >> 12) & 3) != 1) /* TRM */
106	s->irqst \|= 1 << (0 + 4 * chnum); /* TX_EMPTY */
107	omap_mcspi_interrupt_update(s);
108	omap_mcspi_dmarequest_update(ch);
109	}
110
111	void omap_mcspi_reset(struct omap_mcspi_s *s)
112	{
113	int ch;
114
115	s->sysconfig = 0;
116	s->systest = 0;
117	s->irqst = 0;
118	s->irqen = 0;
119	s->wken = 0;
120	s->control = 4;
121
122	for (ch = 0; ch < 4; ch ++) {
123	s->ch[ch].config = 0x060000;
124	s->ch[ch].status = 2; /* TXS */
125	s->ch[ch].control = 0;
126
127	omap_mcspi_dmarequest_update(s->ch + ch);
128	}
129
130	omap_mcspi_interrupt_update(s);
131	}
132
a8170e5e	133	static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
1a072690	134	unsigned size)
2d08cc7c	135	{
	136	struct omap_mcspi_s s = (struct omap_mcspi_s ) opaque;
	137	int ch = 0;
	138	uint32_t ret;
	139
1a072690 BC	140	if (size != 4) {
	141	return omap_badwidth_read32(opaque, addr);
	142	}
	143
2d08cc7c	144	switch (addr) {
	145	case 0x00: /* MCSPI_REVISION */
	146	return 0x91;
	147
	148	case 0x10: /* MCSPI_SYSCONFIG */
	149	return s->sysconfig;
	150
	151	case 0x14: /* MCSPI_SYSSTATUS */
	152	return 1; /* RESETDONE */
	153
	154	case 0x18: /* MCSPI_IRQSTATUS */
	155	return s->irqst;
	156
	157	case 0x1c: /* MCSPI_IRQENABLE */
	158	return s->irqen;
	159
	160	case 0x20: /* MCSPI_WAKEUPENABLE */
	161	return s->wken;
	162
	163	case 0x24: /* MCSPI_SYST */
	164	return s->systest;
	165
	166	case 0x28: /* MCSPI_MODULCTRL */
	167	return s->control;
	168
	169	case 0x68: ch ++;
be688dfb	170	/* fall through */
2d08cc7c	171	case 0x54: ch ++;
be688dfb	172	/* fall through */
2d08cc7c	173	case 0x40: ch ++;
be688dfb	174	/* fall through */
2d08cc7c	175	case 0x2c: /* MCSPI_CHCONF */
	176	return s->ch[ch].config;
	177
	178	case 0x6c: ch ++;
be688dfb	179	/* fall through */
2d08cc7c	180	case 0x58: ch ++;
be688dfb	181	/* fall through */
2d08cc7c	182	case 0x44: ch ++;
be688dfb	183	/* fall through */
2d08cc7c	184	case 0x30: /* MCSPI_CHSTAT */
	185	return s->ch[ch].status;
	186
	187	case 0x70: ch ++;
be688dfb	188	/* fall through */
2d08cc7c	189	case 0x5c: ch ++;
be688dfb	190	/* fall through */
2d08cc7c	191	case 0x48: ch ++;
be688dfb	192	/* fall through */
2d08cc7c	193	case 0x34: /* MCSPI_CHCTRL */
	194	return s->ch[ch].control;
	195
	196	case 0x74: ch ++;
be688dfb	197	/* fall through */
2d08cc7c	198	case 0x60: ch ++;
be688dfb	199	/* fall through */
2d08cc7c	200	case 0x4c: ch ++;
be688dfb	201	/* fall through */
2d08cc7c	202	case 0x38: /* MCSPI_TX */
	203	return s->ch[ch].tx;
	204
	205	case 0x78: ch ++;
be688dfb	206	/* fall through */
2d08cc7c	207	case 0x64: ch ++;
be688dfb	208	/* fall through */
2d08cc7c	209	case 0x50: ch ++;
be688dfb	210	/* fall through */
2d08cc7c	211	case 0x3c: /* MCSPI_RX */
	212	s->ch[ch].status &= ~(1 << 0); /* RXS */
	213	ret = s->ch[ch].rx;
	214	omap_mcspi_transfer_run(s, ch);
	215	return ret;
	216	}
	217
	218	OMAP_BAD_REG(addr);
	219	return 0;
	220	}
	221
a8170e5e	222	static void omap_mcspi_write(void *opaque, hwaddr addr,
1a072690	223	uint64_t value, unsigned size)
2d08cc7c	224	{
	225	struct omap_mcspi_s s = (struct omap_mcspi_s ) opaque;
	226	int ch = 0;
	227
1a072690 BC	228	if (size != 4) {
	229	return omap_badwidth_write32(opaque, addr, value);
	230	}
	231
2d08cc7c	232	switch (addr) {
	233	case 0x00: /* MCSPI_REVISION */
	234	case 0x14: /* MCSPI_SYSSTATUS */
	235	case 0x30: /* MCSPI_CHSTAT0 */
	236	case 0x3c: /* MCSPI_RX0 */
	237	case 0x44: /* MCSPI_CHSTAT1 */
	238	case 0x50: /* MCSPI_RX1 */
	239	case 0x58: /* MCSPI_CHSTAT2 */
	240	case 0x64: /* MCSPI_RX2 */
	241	case 0x6c: /* MCSPI_CHSTAT3 */
	242	case 0x78: /* MCSPI_RX3 */
	243	OMAP_RO_REG(addr);
	244	return;
	245
	246	case 0x10: /* MCSPI_SYSCONFIG */
	247	if (value & (1 << 1)) /* SOFTRESET */
	248	omap_mcspi_reset(s);
	249	s->sysconfig = value & 0x31d;
	250	break;
	251
	252	case 0x18: /* MCSPI_IRQSTATUS */
	253	if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
	254	s->irqst &= ~value;
	255	omap_mcspi_interrupt_update(s);
	256	}
	257	break;
	258
	259	case 0x1c: /* MCSPI_IRQENABLE */
	260	s->irqen = value & 0x1777f;
	261	omap_mcspi_interrupt_update(s);
	262	break;
	263
	264	case 0x20: /* MCSPI_WAKEUPENABLE */
	265	s->wken = value & 1;
	266	break;
	267
	268	case 0x24: /* MCSPI_SYST */
	269	if (s->control & (1 << 3)) /* SYSTEM_TEST */
	270	if (value & (1 << 11)) { /* SSB */
	271	s->irqst \|= 0x1777f;
	272	omap_mcspi_interrupt_update(s);
	273	}
	274	s->systest = value & 0xfff;
	275	break;
	276
	277	case 0x28: /* MCSPI_MODULCTRL */
	278	if (value & (1 << 3)) /* SYSTEM_TEST */
	279	if (s->systest & (1 << 11)) { /* SSB */
	280	s->irqst \|= 0x1777f;
	281	omap_mcspi_interrupt_update(s);
	282	}
	283	s->control = value & 0xf;
	284	break;
	285
	286	case 0x68: ch ++;
be688dfb	287	/* fall through */
2d08cc7c	288	case 0x54: ch ++;
be688dfb	289	/* fall through */
2d08cc7c	290	case 0x40: ch ++;
be688dfb	291	/* fall through */
2d08cc7c	292	case 0x2c: /* MCSPI_CHCONF */
	293	if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR \| DMAW */
	294	omap_mcspi_dmarequest_update(s->ch + ch);
	295	if (((value >> 12) & 3) == 3) /* TRM */
	296	fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
	297	if (((value >> 7) & 0x1f) < 3) /* WL */
1a072690	298	fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
2d08cc7c	299	__FUNCTION__, (value >> 7) & 0x1f);
	300	s->ch[ch].config = value & 0x7fffff;
	301	break;
	302
	303	case 0x70: ch ++;
be688dfb	304	/* fall through */
2d08cc7c	305	case 0x5c: ch ++;
be688dfb	306	/* fall through */
2d08cc7c	307	case 0x48: ch ++;
be688dfb	308	/* fall through */
2d08cc7c	309	case 0x34: /* MCSPI_CHCTRL */
	310	if (value & ~s->ch[ch].control & 1) { /* EN */
	311	s->ch[ch].control \|= 1;
	312	omap_mcspi_transfer_run(s, ch);
	313	} else
	314	s->ch[ch].control = value & 1;
	315	break;
	316
	317	case 0x74: ch ++;
be688dfb	318	/* fall through */
2d08cc7c	319	case 0x60: ch ++;
be688dfb	320	/* fall through */
2d08cc7c	321	case 0x4c: ch ++;
be688dfb	322	/* fall through */
2d08cc7c	323	case 0x38: /* MCSPI_TX */
	324	s->ch[ch].tx = value;
	325	s->ch[ch].status &= ~(1 << 1); /* TXS */
	326	omap_mcspi_transfer_run(s, ch);
	327	break;
	328
	329	default:
	330	OMAP_BAD_REG(addr);
	331	return;
	332	}
	333	}
	334
1a072690 BC	335	static const MemoryRegionOps omap_mcspi_ops = {
	336	.read = omap_mcspi_read,
	337	.write = omap_mcspi_write,
	338	.endianness = DEVICE_NATIVE_ENDIAN,
2d08cc7c	339	};
	340
	341	struct omap_mcspi_s omap_mcspi_init(struct omap_target_agent_s ta, int chnum,
	342	qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
	343	{
2d08cc7c	344	struct omap_mcspi_s s = (struct omap_mcspi_s )
7267c094	345	g_malloc0(sizeof(struct omap_mcspi_s));
2d08cc7c	346	struct omap_mcspi_ch_s *ch = s->ch;
	347
	348	s->irq = irq;
	349	s->chnum = chnum;
	350	while (chnum --) {
	351	ch->txdrq = *drq ++;
	352	ch->rxdrq = *drq ++;
	353	ch ++;
	354	}
	355	omap_mcspi_reset(s);
	356
2c9b15ca	357	memory_region_init_io(&s->iomem, NULL, &omap_mcspi_ops, s, "omap.mcspi",
1a072690	358	omap_l4_region_size(ta, 0));
f44336c5	359	omap_l4_attach(ta, 0, &s->iomem);
2d08cc7c	360
	361	return s;
	362	}
	363
	364	void omap_mcspi_attach(struct omap_mcspi_s *s,
	365	uint32_t (txrx)(void opaque, uint32_t, int), void *opaque,
	366	int chipselect)
	367	{
	368	if (chipselect < 0 \|\| chipselect >= s->chnum)
	369	hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
	370
	371	s->ch[chipselect].txrx = txrx;
	372	s->ch[chipselect].opaque = opaque;
	373	}