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More PowerPC debug print fixes - hardware emulation pass.
[qemu.git] / hw / stellaris.c
CommitLineData
9ee6e8bb
PB		 1/*
2 * Luminary Micro Stellaris preipherals
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licenced under the GPL.
8 */
9
87ecb68b
PB		 10#include "hw.h"
11#include "arm-misc.h"
12#include "primecell.h"
13#include "devices.h"
14#include "qemu-timer.h"
15#include "i2c.h"
16#include "sysemu.h"
17#include "boards.h"
9ee6e8bb 18
cf0dbb21
PB		 19#define GPIO_A 0
20#define GPIO_B 1
21#define GPIO_C 2
22#define GPIO_D 3
23#define GPIO_E 4
24#define GPIO_F 5
25#define GPIO_G 6
26
27#define BP_OLED_I2C 0x01
28#define BP_OLED_SSI 0x02
29#define BP_GAMEPAD 0x04
30
9ee6e8bb
PB		 31typedef const struct {
32 const char *name;
33 uint32_t did0;
34 uint32_t did1;
35 uint32_t dc0;
36 uint32_t dc1;
37 uint32_t dc2;
38 uint32_t dc3;
39 uint32_t dc4;
cf0dbb21 40 uint32_t peripherals;
9ee6e8bb
PB		 41} stellaris_board_info;
42
43/* General purpose timer module. */
44
45/* Multiplication factor to convert from GPTM timer ticks to qemu timer
46 ticks. */
47static int stellaris_clock_scale;
48
49typedef struct gptm_state {
50 uint32_t config;
51 uint32_t mode[2];
52 uint32_t control;
53 uint32_t state;
54 uint32_t mask;
55 uint32_t load[2];
56 uint32_t match[2];
57 uint32_t prescale[2];
58 uint32_t match_prescale[2];
59 uint32_t rtc;
60 int64_t tick[2];
61 struct gptm_state *opaque[2];
62 uint32_t base;
63 QEMUTimer *timer[2];
64 /* The timers have an alternate output used to trigger the ADC. */
65 qemu_irq trigger;
66 qemu_irq irq;
67} gptm_state;
68
69static void gptm_update_irq(gptm_state *s)
70{
71 int level;
72 level = (s->state & s->mask) != 0;
73 qemu_set_irq(s->irq, level);
74}
75
76static void gptm_stop(gptm_state *s, int n)
77{
78 qemu_del_timer(s->timer[n]);
79}
80
81static void gptm_reload(gptm_state *s, int n, int reset)
82{
83 int64_t tick;
84 if (reset)
85 tick = qemu_get_clock(vm_clock);
86 else
87 tick = s->tick[n];
88
89 if (s->config == 0) {
90 /* 32-bit CountDown. */
91 uint32_t count;
92 count = s->load[0] | (s->load[1] << 16);
93 tick += (int64_t)count * stellaris_clock_scale;
94 } else if (s->config == 1) {
95 /* 32-bit RTC. 1Hz tick. */
96 tick += ticks_per_sec;
97 } else if (s->mode[n] == 0xa) {
98 /* PWM mode. Not implemented. */
99 } else {
100 cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
101 s->mode[n]);
102 }
103 s->tick[n] = tick;
104 qemu_mod_timer(s->timer[n], tick);
105}
106
107static void gptm_tick(void *opaque)
108{
109 gptm_state **p = (gptm_state **)opaque;
110 gptm_state *s;
111 int n;
112
113 s = *p;
114 n = p - s->opaque;
115 if (s->config == 0) {
116 s->state |= 1;
117 if ((s->control & 0x20)) {
118 /* Output trigger. */
119 qemu_irq_raise(s->trigger);
120 qemu_irq_lower(s->trigger);
121 }
122 if (s->mode[0] & 1) {
123 /* One-shot. */
124 s->control &= ~1;
125 } else {
126 /* Periodic. */
127 gptm_reload(s, 0, 0);
128 }
129 } else if (s->config == 1) {
130 /* RTC. */
131 uint32_t match;
132 s->rtc++;
133 match = s->match[0] | (s->match[1] << 16);
134 if (s->rtc > match)
135 s->rtc = 0;
136 if (s->rtc == 0) {
137 s->state |= 8;
138 }
139 gptm_reload(s, 0, 0);
140 } else if (s->mode[n] == 0xa) {
141 /* PWM mode. Not implemented. */
142 } else {
143 cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
144 s->mode[n]);
145 }
146 gptm_update_irq(s);
147}
148
149static uint32_t gptm_read(void *opaque, target_phys_addr_t offset)
150{
151 gptm_state *s = (gptm_state *)opaque;
152
153 offset -= s->base;
154 switch (offset) {
155 case 0x00: /* CFG */
156 return s->config;
157 case 0x04: /* TAMR */
158 return s->mode[0];
159 case 0x08: /* TBMR */
160 return s->mode[1];
161 case 0x0c: /* CTL */
162 return s->control;
163 case 0x18: /* IMR */
164 return s->mask;
165 case 0x1c: /* RIS */
166 return s->state;
167 case 0x20: /* MIS */
168 return s->state & s->mask;
169 case 0x24: /* CR */
170 return 0;
171 case 0x28: /* TAILR */
172 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
173 case 0x2c: /* TBILR */
174 return s->load[1];
175 case 0x30: /* TAMARCHR */
176 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
177 case 0x34: /* TBMATCHR */
178 return s->match[1];
179 case 0x38: /* TAPR */
180 return s->prescale[0];
181 case 0x3c: /* TBPR */
182 return s->prescale[1];
183 case 0x40: /* TAPMR */
184 return s->match_prescale[0];
185 case 0x44: /* TBPMR */
186 return s->match_prescale[1];
187 case 0x48: /* TAR */
188 if (s->control == 1)
189 return s->rtc;
190 case 0x4c: /* TBR */
191 cpu_abort(cpu_single_env, "TODO: Timer value read\n");
192 default:
193 cpu_abort(cpu_single_env, "gptm_read: Bad offset 0x%x\n", (int)offset);
194 return 0;
195 }
196}
197
198static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
199{
200 gptm_state *s = (gptm_state *)opaque;
201 uint32_t oldval;
202
203 offset -= s->base;
204 /* The timers should be disabled before changing the configuration.
205 We take advantage of this and defer everything until the timer
206 is enabled. */
207 switch (offset) {
208 case 0x00: /* CFG */
209 s->config = value;
210 break;
211 case 0x04: /* TAMR */
212 s->mode[0] = value;
213 break;
214 case 0x08: /* TBMR */
215 s->mode[1] = value;
216 break;
217 case 0x0c: /* CTL */
218 oldval = s->control;
219 s->control = value;
220 /* TODO: Implement pause. */
221 if ((oldval ^ value) & 1) {
222 if (value & 1) {
223 gptm_reload(s, 0, 1);
224 } else {
225 gptm_stop(s, 0);
226 }
227 }
228 if (((oldval ^ value) & 0x100) && s->config >= 4) {
229 if (value & 0x100) {
230 gptm_reload(s, 1, 1);
231 } else {
232 gptm_stop(s, 1);
233 }
234 }
235 break;
236 case 0x18: /* IMR */
237 s->mask = value & 0x77;
238 gptm_update_irq(s);
239 break;
240 case 0x24: /* CR */
241 s->state &= ~value;
242 break;
243 case 0x28: /* TAILR */
244 s->load[0] = value & 0xffff;
245 if (s->config < 4) {
246 s->load[1] = value >> 16;
247 }
248 break;
249 case 0x2c: /* TBILR */
250 s->load[1] = value & 0xffff;
251 break;
252 case 0x30: /* TAMARCHR */
253 s->match[0] = value & 0xffff;
254 if (s->config < 4) {
255 s->match[1] = value >> 16;
256 }
257 break;
258 case 0x34: /* TBMATCHR */
259 s->match[1] = value >> 16;
260 break;
261 case 0x38: /* TAPR */
262 s->prescale[0] = value;
263 break;
264 case 0x3c: /* TBPR */
265 s->prescale[1] = value;
266 break;
267 case 0x40: /* TAPMR */
268 s->match_prescale[0] = value;
269 break;
270 case 0x44: /* TBPMR */
271 s->match_prescale[0] = value;
272 break;
273 default:
274 cpu_abort(cpu_single_env, "gptm_write: Bad offset 0x%x\n", (int)offset);
275 }
276 gptm_update_irq(s);
277}
278
279static CPUReadMemoryFunc *gptm_readfn[] = {
280 gptm_read,
281 gptm_read,
282 gptm_read
283};
284
285static CPUWriteMemoryFunc *gptm_writefn[] = {
286 gptm_write,
287 gptm_write,
288 gptm_write
289};
290
291static void stellaris_gptm_init(uint32_t base, qemu_irq irq, qemu_irq trigger)
292{
293 int iomemtype;
294 gptm_state *s;
295
296 s = (gptm_state *)qemu_mallocz(sizeof(gptm_state));
297 s->base = base;
298 s->irq = irq;
299 s->trigger = trigger;
300 s->opaque[0] = s->opaque[1] = s;
301
302 iomemtype = cpu_register_io_memory(0, gptm_readfn,
303 gptm_writefn, s);
304 cpu_register_physical_memory(base, 0x00001000, iomemtype);
305 s->timer[0] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[0]);
306 s->timer[1] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[1]);
307 /* ??? Save/restore. */
308}
309
310
311/* System controller. */
312
313typedef struct {
314 uint32_t base;
315 uint32_t pborctl;
316 uint32_t ldopctl;
317 uint32_t int_status;
318 uint32_t int_mask;
319 uint32_t resc;
320 uint32_t rcc;
321 uint32_t rcgc[3];
322 uint32_t scgc[3];
323 uint32_t dcgc[3];
324 uint32_t clkvclr;
325 uint32_t ldoarst;
326 qemu_irq irq;
327 stellaris_board_info *board;
328} ssys_state;
329
330static void ssys_update(ssys_state *s)
331{
332 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
333}
334
335static uint32_t pllcfg_sandstorm[16] = {
336 0x31c0, /* 1 Mhz */
337 0x1ae0, /* 1.8432 Mhz */
338 0x18c0, /* 2 Mhz */
339 0xd573, /* 2.4576 Mhz */
340 0x37a6, /* 3.57954 Mhz */
341 0x1ae2, /* 3.6864 Mhz */
342 0x0c40, /* 4 Mhz */
343 0x98bc, /* 4.906 Mhz */
344 0x935b, /* 4.9152 Mhz */
345 0x09c0, /* 5 Mhz */
346 0x4dee, /* 5.12 Mhz */
347 0x0c41, /* 6 Mhz */
348 0x75db, /* 6.144 Mhz */
349 0x1ae6, /* 7.3728 Mhz */
350 0x0600, /* 8 Mhz */
351 0x585b /* 8.192 Mhz */
352};
353
354static uint32_t pllcfg_fury[16] = {
355 0x3200, /* 1 Mhz */
356 0x1b20, /* 1.8432 Mhz */
357 0x1900, /* 2 Mhz */
358 0xf42b, /* 2.4576 Mhz */
359 0x37e3, /* 3.57954 Mhz */
360 0x1b21, /* 3.6864 Mhz */
361 0x0c80, /* 4 Mhz */
362 0x98ee, /* 4.906 Mhz */
363 0xd5b4, /* 4.9152 Mhz */
364 0x0a00, /* 5 Mhz */
365 0x4e27, /* 5.12 Mhz */
366 0x1902, /* 6 Mhz */
367 0xec1c, /* 6.144 Mhz */
368 0x1b23, /* 7.3728 Mhz */
369 0x0640, /* 8 Mhz */
370 0xb11c /* 8.192 Mhz */
371};
372
373static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
374{
375 ssys_state *s = (ssys_state *)opaque;
376
377 offset -= s->base;
378 switch (offset) {
379 case 0x000: /* DID0 */
380 return s->board->did0;
381 case 0x004: /* DID1 */
382 return s->board->did1;
383 case 0x008: /* DC0 */
384 return s->board->dc0;
385 case 0x010: /* DC1 */
386 return s->board->dc1;
387 case 0x014: /* DC2 */
388 return s->board->dc2;
389 case 0x018: /* DC3 */
390 return s->board->dc3;
391 case 0x01c: /* DC4 */
392 return s->board->dc4;
393 case 0x030: /* PBORCTL */
394 return s->pborctl;
395 case 0x034: /* LDOPCTL */
396 return s->ldopctl;
397 case 0x040: /* SRCR0 */
398 return 0;
399 case 0x044: /* SRCR1 */
400 return 0;
401 case 0x048: /* SRCR2 */
402 return 0;
403 case 0x050: /* RIS */
404 return s->int_status;
405 case 0x054: /* IMC */
406 return s->int_mask;
407 case 0x058: /* MISC */
408 return s->int_status & s->int_mask;
409 case 0x05c: /* RESC */
410 return s->resc;
411 case 0x060: /* RCC */
412 return s->rcc;
413 case 0x064: /* PLLCFG */
414 {
415 int xtal;
416 xtal = (s->rcc >> 6) & 0xf;
417 if (s->board->did0 & (1 << 16)) {
418 return pllcfg_fury[xtal];
419 } else {
420 return pllcfg_sandstorm[xtal];
421 }
422 }
423 case 0x100: /* RCGC0 */
424 return s->rcgc[0];
425 case 0x104: /* RCGC1 */
426 return s->rcgc[1];
427 case 0x108: /* RCGC2 */
428 return s->rcgc[2];
429 case 0x110: /* SCGC0 */
430 return s->scgc[0];
431 case 0x114: /* SCGC1 */
432 return s->scgc[1];
433 case 0x118: /* SCGC2 */
434 return s->scgc[2];
435 case 0x120: /* DCGC0 */
436 return s->dcgc[0];
437 case 0x124: /* DCGC1 */
438 return s->dcgc[1];
439 case 0x128: /* DCGC2 */
440 return s->dcgc[2];
441 case 0x150: /* CLKVCLR */
442 return s->clkvclr;
443 case 0x160: /* LDOARST */
444 return s->ldoarst;
445 default:
79b02417 446 cpu_abort(cpu_single_env, "ssys_read: Bad offset 0x%x\n", (int)offset);
9ee6e8bb
PB		 447 return 0;
448 }
449}
450
451static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value)
452{
453 ssys_state *s = (ssys_state *)opaque;
454
455 offset -= s->base;
456 switch (offset) {
457 case 0x030: /* PBORCTL */
458 s->pborctl = value & 0xffff;
459 break;
460 case 0x034: /* LDOPCTL */
461 s->ldopctl = value & 0x1f;
462 break;
463 case 0x040: /* SRCR0 */
464 case 0x044: /* SRCR1 */
465 case 0x048: /* SRCR2 */
466 fprintf(stderr, "Peripheral reset not implemented\n");
467 break;
468 case 0x054: /* IMC */
469 s->int_mask = value & 0x7f;
470 break;
471 case 0x058: /* MISC */
472 s->int_status &= ~value;
473 break;
474 case 0x05c: /* RESC */
475 s->resc = value & 0x3f;
476 break;
477 case 0x060: /* RCC */
478 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
479 /* PLL enable. */
480 s->int_status |= (1 << 6);
481 }
482 s->rcc = value;
483 stellaris_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
484 break;
485 case 0x100: /* RCGC0 */
486 s->rcgc[0] = value;
487 break;
488 case 0x104: /* RCGC1 */
489 s->rcgc[1] = value;
490 break;
491 case 0x108: /* RCGC2 */
492 s->rcgc[2] = value;
493 break;
494 case 0x110: /* SCGC0 */
495 s->scgc[0] = value;
496 break;
497 case 0x114: /* SCGC1 */
498 s->scgc[1] = value;
499 break;
500 case 0x118: /* SCGC2 */
501 s->scgc[2] = value;
502 break;
503 case 0x120: /* DCGC0 */
504 s->dcgc[0] = value;
505 break;
506 case 0x124: /* DCGC1 */
507 s->dcgc[1] = value;
508 break;
509 case 0x128: /* DCGC2 */
510 s->dcgc[2] = value;
511 break;
512 case 0x150: /* CLKVCLR */
513 s->clkvclr = value;
514 break;
515 case 0x160: /* LDOARST */
516 s->ldoarst = value;
517 break;
518 default:
79b02417 519 cpu_abort(cpu_single_env, "ssys_write: Bad offset 0x%x\n", (int)offset);
9ee6e8bb
PB		 520 }
521 ssys_update(s);
522}
523
524static CPUReadMemoryFunc *ssys_readfn[] = {
525 ssys_read,
526 ssys_read,
527 ssys_read
528};
529
530static CPUWriteMemoryFunc *ssys_writefn[] = {
531 ssys_write,
532 ssys_write,
533 ssys_write
534};
535
9596ebb7 536static void ssys_reset(void *opaque)
9ee6e8bb
PB		 537{
538 ssys_state *s = (ssys_state *)opaque;
539
540 s->pborctl = 0x7ffd;
541 s->rcc = 0x078e3ac0;
542 s->rcgc[0] = 1;
543 s->scgc[0] = 1;
544 s->dcgc[0] = 1;
545}
546
547static void stellaris_sys_init(uint32_t base, qemu_irq irq,
548 stellaris_board_info * board)
549{
550 int iomemtype;
551 ssys_state *s;
552
553 s = (ssys_state *)qemu_mallocz(sizeof(ssys_state));
554 s->base = base;
555 s->irq = irq;
556 s->board = board;
557
558 iomemtype = cpu_register_io_memory(0, ssys_readfn,
559 ssys_writefn, s);
560 cpu_register_physical_memory(base, 0x00001000, iomemtype);
561 ssys_reset(s);
562 /* ??? Save/restore. */
563}
564
565
566/* I2C controller. */
567
568typedef struct {
569 i2c_bus *bus;
570 qemu_irq irq;
571 uint32_t base;
572 uint32_t msa;
573 uint32_t mcs;
574 uint32_t mdr;
575 uint32_t mtpr;
576 uint32_t mimr;
577 uint32_t mris;
578 uint32_t mcr;
579} stellaris_i2c_state;
580
581#define STELLARIS_I2C_MCS_BUSY 0x01
582#define STELLARIS_I2C_MCS_ERROR 0x02
583#define STELLARIS_I2C_MCS_ADRACK 0x04
584#define STELLARIS_I2C_MCS_DATACK 0x08
585#define STELLARIS_I2C_MCS_ARBLST 0x10
586#define STELLARIS_I2C_MCS_IDLE 0x20
587#define STELLARIS_I2C_MCS_BUSBSY 0x40
588
589static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset)
590{
591 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
592
593 offset -= s->base;
594 switch (offset) {
595 case 0x00: /* MSA */
596 return s->msa;
597 case 0x04: /* MCS */
598 /* We don't emulate timing, so the controller is never busy. */
599 return s->mcs | STELLARIS_I2C_MCS_IDLE;
600 case 0x08: /* MDR */
601 return s->mdr;
602 case 0x0c: /* MTPR */
603 return s->mtpr;
604 case 0x10: /* MIMR */
605 return s->mimr;
606 case 0x14: /* MRIS */
607 return s->mris;
608 case 0x18: /* MMIS */
609 return s->mris & s->mimr;
610 case 0x20: /* MCR */
611 return s->mcr;
612 default:
613 cpu_abort(cpu_single_env, "strllaris_i2c_read: Bad offset 0x%x\n",
614 (int)offset);
615 return 0;
616 }
617}
618
619static void stellaris_i2c_update(stellaris_i2c_state *s)
620{
621 int level;
622
623 level = (s->mris & s->mimr) != 0;
624 qemu_set_irq(s->irq, level);
625}
626
627static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
628 uint32_t value)
629{
630 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
631
632 offset -= s->base;
633 switch (offset) {
634 case 0x00: /* MSA */
635 s->msa = value & 0xff;
636 break;
637 case 0x04: /* MCS */
638 if ((s->mcr & 0x10) == 0) {
639 /* Disabled. Do nothing. */
640 break;
641 }
642 /* Grab the bus if this is starting a transfer. */
643 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
644 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
645 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
646 } else {
647 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
648 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
649 }
650 }
651 /* If we don't have the bus then indicate an error. */
652 if (!i2c_bus_busy(s->bus)
653 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
654 s->mcs |= STELLARIS_I2C_MCS_ERROR;
655 break;
656 }
657 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
658 if (value & 1) {
659 /* Transfer a byte. */
660 /* TODO: Handle errors. */
661 if (s->msa & 1) {
662 /* Recv */
663 s->mdr = i2c_recv(s->bus) & 0xff;
664 } else {
665 /* Send */
666 i2c_send(s->bus, s->mdr);
667 }
668 /* Raise an interrupt. */
669 s->mris |= 1;
670 }
671 if (value & 4) {
672 /* Finish transfer. */
673 i2c_end_transfer(s->bus);
674 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
675 }
676 break;
677 case 0x08: /* MDR */
678 s->mdr = value & 0xff;
679 break;
680 case 0x0c: /* MTPR */
681 s->mtpr = value & 0xff;
682 break;
683 case 0x10: /* MIMR */
684 s->mimr = 1;
685 break;
686 case 0x1c: /* MICR */
687 s->mris &= ~value;
688 break;
689 case 0x20: /* MCR */
690 if (value & 1)
691 cpu_abort(cpu_single_env,
692 "stellaris_i2c_write: Loopback not implemented\n");
693 if (value & 0x20)
694 cpu_abort(cpu_single_env,
695 "stellaris_i2c_write: Slave mode not implemented\n");
696 s->mcr = value & 0x31;
697 break;
698 default:
699 cpu_abort(cpu_single_env, "stellaris_i2c_write: Bad offset 0x%x\n",
700 (int)offset);
701 }
702 stellaris_i2c_update(s);
703}
704
705static void stellaris_i2c_reset(stellaris_i2c_state *s)
706{
707 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
708 i2c_end_transfer(s->bus);
709
710 s->msa = 0;
711 s->mcs = 0;
712 s->mdr = 0;
713 s->mtpr = 1;
714 s->mimr = 0;
715 s->mris = 0;
716 s->mcr = 0;
717 stellaris_i2c_update(s);
718}
719
720static CPUReadMemoryFunc *stellaris_i2c_readfn[] = {
721 stellaris_i2c_read,
722 stellaris_i2c_read,
723 stellaris_i2c_read
724};
725
726static CPUWriteMemoryFunc *stellaris_i2c_writefn[] = {
727 stellaris_i2c_write,
728 stellaris_i2c_write,
729 stellaris_i2c_write
730};
731
732static void stellaris_i2c_init(uint32_t base, qemu_irq irq, i2c_bus *bus)
733{
734 stellaris_i2c_state *s;
735 int iomemtype;
736
737 s = (stellaris_i2c_state *)qemu_mallocz(sizeof(stellaris_i2c_state));
738 s->base = base;
739 s->irq = irq;
740 s->bus = bus;
741
742 iomemtype = cpu_register_io_memory(0, stellaris_i2c_readfn,
743 stellaris_i2c_writefn, s);
744 cpu_register_physical_memory(base, 0x00001000, iomemtype);
745 /* ??? For now we only implement the master interface. */
746 stellaris_i2c_reset(s);
747}
748
749/* Analogue to Digital Converter. This is only partially implemented,
750 enough for applications that use a combined ADC and timer tick. */
751
752#define STELLARIS_ADC_EM_CONTROLLER 0
753#define STELLARIS_ADC_EM_COMP 1
754#define STELLARIS_ADC_EM_EXTERNAL 4
755#define STELLARIS_ADC_EM_TIMER 5
756#define STELLARIS_ADC_EM_PWM0 6
757#define STELLARIS_ADC_EM_PWM1 7
758#define STELLARIS_ADC_EM_PWM2 8
759
760#define STELLARIS_ADC_FIFO_EMPTY 0x0100
761#define STELLARIS_ADC_FIFO_FULL 0x1000
762
763typedef struct
764{
765 uint32_t base;
766 uint32_t actss;
767 uint32_t ris;
768 uint32_t im;
769 uint32_t emux;
770 uint32_t ostat;
771 uint32_t ustat;
772 uint32_t sspri;
773 uint32_t sac;
774 struct {
775 uint32_t state;
776 uint32_t data[16];
777 } fifo[4];
778 uint32_t ssmux[4];
779 uint32_t ssctl[4];
780 qemu_irq irq;
781} stellaris_adc_state;
782
783static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
784{
785 int tail;
786
787 tail = s->fifo[n].state & 0xf;
788 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
789 s->ustat |= 1 << n;
790 } else {
791 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
792 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
793 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
794 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
795 }
796 return s->fifo[n].data[tail];
797}
798
799static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
800 uint32_t value)
801{
802 int head;
803
804 head = (s->fifo[n].state >> 4) & 0xf;
805 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
806 s->ostat |= 1 << n;
807 return;
808 }
809 s->fifo[n].data[head] = value;
810 head = (head + 1) & 0xf;
811 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
812 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
813 if ((s->fifo[n].state & 0xf) == head)
814 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
815}
816
817static void stellaris_adc_update(stellaris_adc_state *s)
818{
819 int level;
820
821 level = (s->ris & s->im) != 0;
822 qemu_set_irq(s->irq, level);
823}
824
825static void stellaris_adc_trigger(void *opaque, int irq, int level)
826{
827 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
828 /* Some applications use the ADC as a random number source, so introduce
829 some variation into the signal. */
830 static uint32_t noise = 0;
831
832 if ((s->actss & 1) == 0) {
833 return;
834 }
835
836 noise = noise * 314159 + 1;
837 /* ??? actual inputs not implemented. Return an arbitrary value. */
838 stellaris_adc_fifo_write(s, 0, 0x200 + ((noise >> 16) & 7));
839 s->ris |= 1;
840 stellaris_adc_update(s);
841}
842
843static void stellaris_adc_reset(stellaris_adc_state *s)
844{
845 int n;
846
847 for (n = 0; n < 4; n++) {
848 s->ssmux[n] = 0;
849 s->ssctl[n] = 0;
850 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
851 }
852}
853
854static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset)
855{
856 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
857
858 /* TODO: Implement this. */
859 offset -= s->base;
860 if (offset >= 0x40 && offset < 0xc0) {
861 int n;
862 n = (offset - 0x40) >> 5;
863 switch (offset & 0x1f) {
864 case 0x00: /* SSMUX */
865 return s->ssmux[n];
866 case 0x04: /* SSCTL */
867 return s->ssctl[n];
868 case 0x08: /* SSFIFO */
869 return stellaris_adc_fifo_read(s, n);
870 case 0x0c: /* SSFSTAT */
871 return s->fifo[n].state;
872 default:
873 break;
874 }
875 }
876 switch (offset) {
877 case 0x00: /* ACTSS */
878 return s->actss;
879 case 0x04: /* RIS */
880 return s->ris;
881 case 0x08: /* IM */
882 return s->im;
883 case 0x0c: /* ISC */
884 return s->ris & s->im;
885 case 0x10: /* OSTAT */
886 return s->ostat;
887 case 0x14: /* EMUX */
888 return s->emux;
889 case 0x18: /* USTAT */
890 return s->ustat;
891 case 0x20: /* SSPRI */
892 return s->sspri;
893 case 0x30: /* SAC */
894 return s->sac;
895 default:
896 cpu_abort(cpu_single_env, "strllaris_adc_read: Bad offset 0x%x\n",
897 (int)offset);
898 return 0;
899 }
900}
901
902static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
903 uint32_t value)
904{
905 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
906
907 /* TODO: Implement this. */
908 offset -= s->base;
909 if (offset >= 0x40 && offset < 0xc0) {
910 int n;
911 n = (offset - 0x40) >> 5;
912 switch (offset & 0x1f) {
913 case 0x00: /* SSMUX */
914 s->ssmux[n] = value & 0x33333333;
915 return;
916 case 0x04: /* SSCTL */
917 if (value != 6) {
918 cpu_abort(cpu_single_env, "ADC: Unimplemented sequence %x\n",
919 value);
920 }
921 s->ssctl[n] = value;
922 return;
923 default:
924 break;
925 }
926 }
927 switch (offset) {
928 case 0x00: /* ACTSS */
929 s->actss = value & 0xf;
930 if (value & 0xe) {
931 cpu_abort(cpu_single_env,
932 "Not implemented: ADC sequencers 1-3\n");
933 }
934 break;
935 case 0x08: /* IM */
936 s->im = value;
937 break;
938 case 0x0c: /* ISC */
939 s->ris &= ~value;
940 break;
941 case 0x10: /* OSTAT */
942 s->ostat &= ~value;
943 break;
944 case 0x14: /* EMUX */
945 s->emux = value;
946 break;
947 case 0x18: /* USTAT */
948 s->ustat &= ~value;
949 break;
950 case 0x20: /* SSPRI */
951 s->sspri = value;
952 break;
953 case 0x28: /* PSSI */
954 cpu_abort(cpu_single_env, "Not implemented: ADC sample initiate\n");
955 break;
956 case 0x30: /* SAC */
957 s->sac = value;
958 break;
959 default:
960 cpu_abort(cpu_single_env, "stellaris_adc_write: Bad offset 0x%x\n",
961 (int)offset);
962 }
963 stellaris_adc_update(s);
964}
965
966static CPUReadMemoryFunc *stellaris_adc_readfn[] = {
967 stellaris_adc_read,
968 stellaris_adc_read,
969 stellaris_adc_read
970};
971
972static CPUWriteMemoryFunc *stellaris_adc_writefn[] = {
973 stellaris_adc_write,
974 stellaris_adc_write,
975 stellaris_adc_write
976};
977
978static qemu_irq stellaris_adc_init(uint32_t base, qemu_irq irq)
979{
980 stellaris_adc_state *s;
981 int iomemtype;
982 qemu_irq *qi;
983
984 s = (stellaris_adc_state *)qemu_mallocz(sizeof(stellaris_adc_state));
985 s->base = base;
986 s->irq = irq;
987
988 iomemtype = cpu_register_io_memory(0, stellaris_adc_readfn,
989 stellaris_adc_writefn, s);
990 cpu_register_physical_memory(base, 0x00001000, iomemtype);
991 stellaris_adc_reset(s);
992 qi = qemu_allocate_irqs(stellaris_adc_trigger, s, 1);
993 return qi[0];
994}
995
996/* Board init. */
997static stellaris_board_info stellaris_boards[] = {
998 { "LM3S811EVB",
999 0,
1000 0x0032000e,
1001 0x001f001f, /* dc0 */
1002 0x001132bf,
1003 0x01071013,
1004 0x3f0f01ff,
1005 0x0000001f,
cf0dbb21 1006 BP_OLED_I2C
9ee6e8bb
PB		 1007 },
1008 { "LM3S6965EVB",
1009 0x10010002,
1010 0x1073402e,
1011 0x00ff007f, /* dc0 */
1012 0x001133ff,
1013 0x030f5317,
1014 0x0f0f87ff,
1015 0x5000007f,
cf0dbb21 1016 BP_OLED_SSI | BP_GAMEPAD
9ee6e8bb
PB		 1017 }
1018};
1019
1020static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1021 DisplayState *ds, stellaris_board_info *board)
1022{
1023 static const int uart_irq[] = {5, 6, 33, 34};
1024 static const int timer_irq[] = {19, 21, 23, 35};
1025 static const uint32_t gpio_addr[7] =
1026 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1027 0x40024000, 0x40025000, 0x40026000};
1028 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1029
1030 qemu_irq *pic;
1031 qemu_irq *gpio_in[5];
1032 qemu_irq *gpio_out[5];
1033 qemu_irq adc;
1034 int sram_size;
1035 int flash_size;
1036 i2c_bus *i2c;
1037 int i;
1038
1039 flash_size = ((board->dc0 & 0xffff) + 1) << 1;
1040 sram_size = (board->dc0 >> 18) + 1;
1041 pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model);
1042
1043 if (board->dc1 & (1 << 16)) {
1044 adc = stellaris_adc_init(0x40038000, pic[14]);
1045 } else {
1046 adc = NULL;
1047 }
1048 for (i = 0; i < 4; i++) {
1049 if (board->dc2 & (0x10000 << i)) {
1050 stellaris_gptm_init(0x40030000 + i * 0x1000,
1051 pic[timer_irq[i]], adc);
1052 }
1053 }
1054
1055 stellaris_sys_init(0x400fe000, pic[28], board);
1056
1057 for (i = 0; i < 7; i++) {
1058 if (board->dc4 & (1 << i)) {
1059 gpio_in[i] = pl061_init(gpio_addr[i], pic[gpio_irq[i]],
1060 &gpio_out[i]);
1061 }
1062 }
1063
1064 if (board->dc2 & (1 << 12)) {
1065 i2c = i2c_init_bus();
1066 stellaris_i2c_init(0x40020000, pic[8], i2c);
cf0dbb21 1067 if (board->peripherals & BP_OLED_I2C) {
9ee6e8bb
PB		 1068 ssd0303_init(ds, i2c, 0x3d);
1069 }
1070 }
1071
1072 for (i = 0; i < 4; i++) {
1073 if (board->dc2 & (1 << i)) {
1074 pl011_init(0x4000c000 + i * 0x1000, pic[uart_irq[i]],
1075 serial_hds[i], PL011_LUMINARY);
1076 }
1077 }
1078 if (board->dc2 & (1 << 4)) {
cf0dbb21 1079 if (board->peripherals & BP_OLED_SSI) {
9ee6e8bb
PB		 1080 void * oled;
1081 /* FIXME: Implement chip select for OLED/MMC. */
cf0dbb21 1082 oled = ssd0323_init(ds, &gpio_out[GPIO_C][7]);
9ee6e8bb
PB		 1083 pl022_init(0x40008000, pic[7], ssd0323_xfer_ssi, oled);
1084 } else {
1085 pl022_init(0x40008000, pic[7], NULL, NULL);
1086 }
1087 }
cf0dbb21
PB		 1088 if (board->peripherals & BP_GAMEPAD) {
1089 qemu_irq gpad_irq[5];
1090 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1091
1092 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1093 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1094 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1095 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1096 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1097
1098 stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1099 }
9ee6e8bb
PB		 1100}
1101
1102/* FIXME: Figure out how to generate these from stellaris_boards. */
1103static void lm3s811evb_init(int ram_size, int vga_ram_size,
1104 const char *boot_device, DisplayState *ds,
9ee6e8bb
PB		 1105 const char *kernel_filename, const char *kernel_cmdline,
1106 const char *initrd_filename, const char *cpu_model)
1107{
1108 stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[0]);
1109}
1110
1111static void lm3s6965evb_init(int ram_size, int vga_ram_size,
1112 const char *boot_device, DisplayState *ds,
9ee6e8bb
PB		 1113 const char *kernel_filename, const char *kernel_cmdline,
1114 const char *initrd_filename, const char *cpu_model)
1115{
1116 stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[1]);
1117}
1118
1119QEMUMachine lm3s811evb_machine = {
1120 "lm3s811evb",
1121 "Stellaris LM3S811EVB",
1122 lm3s811evb_init,
1123};
1124
1125QEMUMachine lm3s6965evb_machine = {
1126 "lm3s6965evb",
1127 "Stellaris LM3S6965EVB",
1128 lm3s6965evb_init,
1129};
Qemu copy for testing