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Commit | Line | Data |
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420557e8 | 1 | /* |
ee76f82e | 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
5fafdf24 | 3 | * |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
9d07d757 | 24 | #include "sysbus.h" |
87ecb68b PB |
25 | #include "qemu-timer.h" |
26 | #include "sun4m.h" | |
27 | #include "nvram.h" | |
28 | #include "sparc32_dma.h" | |
29 | #include "fdc.h" | |
30 | #include "sysemu.h" | |
31 | #include "net.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
8b17de88 | 34 | #include "scsi.h" |
22548760 BS |
35 | #include "pc.h" |
36 | #include "isa.h" | |
3cce6243 | 37 | #include "fw_cfg.h" |
b4ed08e0 | 38 | #include "escc.h" |
4b48bf05 | 39 | #include "qdev-addr.h" |
d2c63fc1 | 40 | |
b3a23197 | 41 | //#define DEBUG_IRQ |
420557e8 | 42 | |
36cd9210 BS |
43 | /* |
44 | * Sun4m architecture was used in the following machines: | |
45 | * | |
46 | * SPARCserver 6xxMP/xx | |
77f193da BS |
47 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), |
48 | * SPARCclassic X (4/10) | |
36cd9210 BS |
49 | * SPARCstation LX/ZX (4/30) |
50 | * SPARCstation Voyager | |
51 | * SPARCstation 10/xx, SPARCserver 10/xx | |
52 | * SPARCstation 5, SPARCserver 5 | |
53 | * SPARCstation 20/xx, SPARCserver 20 | |
54 | * SPARCstation 4 | |
55 | * | |
7d85892b BS |
56 | * Sun4d architecture was used in the following machines: |
57 | * | |
58 | * SPARCcenter 2000 | |
59 | * SPARCserver 1000 | |
60 | * | |
ee76f82e BS |
61 | * Sun4c architecture was used in the following machines: |
62 | * SPARCstation 1/1+, SPARCserver 1/1+ | |
63 | * SPARCstation SLC | |
64 | * SPARCstation IPC | |
65 | * SPARCstation ELC | |
66 | * SPARCstation IPX | |
67 | * | |
36cd9210 BS |
68 | * See for example: http://www.sunhelp.org/faq/sunref1.html |
69 | */ | |
70 | ||
b3a23197 | 71 | #ifdef DEBUG_IRQ |
001faf32 BS |
72 | #define DPRINTF(fmt, ...) \ |
73 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
b3a23197 | 74 | #else |
001faf32 | 75 | #define DPRINTF(fmt, ...) |
b3a23197 BS |
76 | #endif |
77 | ||
420557e8 | 78 | #define KERNEL_LOAD_ADDR 0x00004000 |
b6f479d3 | 79 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 80 | #define INITRD_LOAD_ADDR 0x00800000 |
a7227727 | 81 | #define PROM_SIZE_MAX (1024 * 1024) |
40ce0a9a | 82 | #define PROM_VADDR 0xffd00000 |
f930d07e | 83 | #define PROM_FILENAME "openbios-sparc32" |
3cce6243 | 84 | #define CFG_ADDR 0xd00000510ULL |
fbfcf955 | 85 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
b8174937 | 86 | |
ba3c64fb | 87 | #define MAX_CPUS 16 |
b3a23197 | 88 | #define MAX_PILS 16 |
420557e8 | 89 | |
b4ed08e0 BS |
90 | #define ESCC_CLOCK 4915200 |
91 | ||
8137cde8 | 92 | struct sun4m_hwdef { |
5dcb6b91 BS |
93 | target_phys_addr_t iommu_base, slavio_base; |
94 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; | |
95 | target_phys_addr_t serial_base, fd_base; | |
4c2485de | 96 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
0019ad53 | 97 | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
7eb0c8e8 BS |
98 | target_phys_addr_t ecc_base; |
99 | uint32_t ecc_version; | |
36cd9210 | 100 | long vram_size, nvram_size; |
6341fdcb | 101 | // IRQ numbers are not PIL ones, but master interrupt controller |
e3a79bca | 102 | // register bit numbers |
1572a18c | 103 | int esp_irq, le_irq, clock_irq, clock1_irq; |
e42c20b4 | 104 | int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq; |
905fdcb5 BS |
105 | uint8_t nvram_machine_id; |
106 | uint16_t machine_id; | |
7fbfb139 | 107 | uint32_t iommu_version; |
e0353fe2 | 108 | uint32_t intbit_to_level[32]; |
3ebf5aaf BS |
109 | uint64_t max_mem; |
110 | const char * const default_cpu_model; | |
36cd9210 BS |
111 | }; |
112 | ||
7d85892b BS |
113 | #define MAX_IOUNITS 5 |
114 | ||
115 | struct sun4d_hwdef { | |
116 | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; | |
117 | target_phys_addr_t counter_base, nvram_base, ms_kb_base; | |
118 | target_phys_addr_t serial_base; | |
119 | target_phys_addr_t espdma_base, esp_base; | |
120 | target_phys_addr_t ledma_base, le_base; | |
121 | target_phys_addr_t tcx_base; | |
122 | target_phys_addr_t sbi_base; | |
123 | unsigned long vram_size, nvram_size; | |
124 | // IRQ numbers are not PIL ones, but SBI register bit numbers | |
125 | int esp_irq, le_irq, clock_irq, clock1_irq; | |
126 | int ser_irq, ms_kb_irq, me_irq; | |
905fdcb5 BS |
127 | uint8_t nvram_machine_id; |
128 | uint16_t machine_id; | |
7d85892b BS |
129 | uint32_t iounit_version; |
130 | uint64_t max_mem; | |
131 | const char * const default_cpu_model; | |
132 | }; | |
133 | ||
8137cde8 BS |
134 | struct sun4c_hwdef { |
135 | target_phys_addr_t iommu_base, slavio_base; | |
136 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; | |
137 | target_phys_addr_t serial_base, fd_base; | |
138 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; | |
1572a18c | 139 | target_phys_addr_t tcx_base, aux1_base; |
8137cde8 BS |
140 | long vram_size, nvram_size; |
141 | // IRQ numbers are not PIL ones, but master interrupt controller | |
142 | // register bit numbers | |
1572a18c BS |
143 | int esp_irq, le_irq, clock_irq, clock1_irq; |
144 | int ser_irq, ms_kb_irq, fd_irq, me_irq; | |
8137cde8 BS |
145 | uint8_t nvram_machine_id; |
146 | uint16_t machine_id; | |
147 | uint32_t iommu_version; | |
148 | uint32_t intbit_to_level[32]; | |
149 | uint64_t max_mem; | |
150 | const char * const default_cpu_model; | |
151 | }; | |
152 | ||
6f7e9aec FB |
153 | int DMA_get_channel_mode (int nchan) |
154 | { | |
155 | return 0; | |
156 | } | |
157 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
158 | { | |
159 | return 0; | |
160 | } | |
161 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
162 | { | |
163 | return 0; | |
164 | } | |
165 | void DMA_hold_DREQ (int nchan) {} | |
166 | void DMA_release_DREQ (int nchan) {} | |
167 | void DMA_schedule(int nchan) {} | |
6f7e9aec FB |
168 | void DMA_init (int high_page_enable) {} |
169 | void DMA_register_channel (int nchan, | |
170 | DMA_transfer_handler transfer_handler, | |
171 | void *opaque) | |
172 | { | |
173 | } | |
174 | ||
513f789f | 175 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
81864572 | 176 | { |
513f789f | 177 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
178 | return 0; |
179 | } | |
180 | ||
819385c5 | 181 | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
6ef05b95 | 182 | const char *boot_devices, ram_addr_t RAM_size, |
f930d07e BS |
183 | uint32_t kernel_size, |
184 | int width, int height, int depth, | |
905fdcb5 | 185 | int nvram_machine_id, const char *arch) |
e80cfcfc | 186 | { |
d2c63fc1 | 187 | unsigned int i; |
66508601 | 188 | uint32_t start, end; |
d2c63fc1 | 189 | uint8_t image[0x1ff0]; |
d2c63fc1 BS |
190 | struct OpenBIOS_nvpart_v1 *part_header; |
191 | ||
192 | memset(image, '\0', sizeof(image)); | |
e80cfcfc | 193 | |
513f789f | 194 | start = 0; |
b6f479d3 | 195 | |
66508601 BS |
196 | // OpenBIOS nvram variables |
197 | // Variable partition | |
d2c63fc1 BS |
198 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
199 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 200 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 201 | |
d2c63fc1 | 202 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 203 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
204 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
205 | ||
206 | // End marker | |
207 | image[end++] = '\0'; | |
66508601 | 208 | |
66508601 | 209 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 210 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
211 | |
212 | // free partition | |
213 | start = end; | |
d2c63fc1 BS |
214 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
215 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 216 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
217 | |
218 | end = 0x1fd0; | |
d2c63fc1 BS |
219 | OpenBIOS_finish_partition(part_header, end - start); |
220 | ||
905fdcb5 BS |
221 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
222 | nvram_machine_id); | |
d2c63fc1 BS |
223 | |
224 | for (i = 0; i < sizeof(image); i++) | |
225 | m48t59_write(nvram, i, image[i]); | |
e80cfcfc FB |
226 | } |
227 | ||
228 | static void *slavio_intctl; | |
229 | ||
376253ec | 230 | void pic_info(Monitor *mon) |
e80cfcfc | 231 | { |
7d85892b | 232 | if (slavio_intctl) |
376253ec | 233 | slavio_pic_info(mon, slavio_intctl); |
e80cfcfc FB |
234 | } |
235 | ||
376253ec | 236 | void irq_info(Monitor *mon) |
e80cfcfc | 237 | { |
7d85892b | 238 | if (slavio_intctl) |
376253ec | 239 | slavio_irq_info(mon, slavio_intctl); |
e80cfcfc FB |
240 | } |
241 | ||
327ac2e7 BS |
242 | void cpu_check_irqs(CPUState *env) |
243 | { | |
244 | if (env->pil_in && (env->interrupt_index == 0 || | |
245 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
246 | unsigned int i; | |
247 | ||
248 | for (i = 15; i > 0; i--) { | |
249 | if (env->pil_in & (1 << i)) { | |
250 | int old_interrupt = env->interrupt_index; | |
251 | ||
252 | env->interrupt_index = TT_EXTINT | i; | |
f32d7ec5 BS |
253 | if (old_interrupt != env->interrupt_index) { |
254 | DPRINTF("Set CPU IRQ %d\n", i); | |
327ac2e7 | 255 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
f32d7ec5 | 256 | } |
327ac2e7 BS |
257 | break; |
258 | } | |
259 | } | |
260 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { | |
f32d7ec5 | 261 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
327ac2e7 BS |
262 | env->interrupt_index = 0; |
263 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
264 | } | |
265 | } | |
266 | ||
b3a23197 BS |
267 | static void cpu_set_irq(void *opaque, int irq, int level) |
268 | { | |
269 | CPUState *env = opaque; | |
270 | ||
271 | if (level) { | |
272 | DPRINTF("Raise CPU IRQ %d\n", irq); | |
b3a23197 | 273 | env->halted = 0; |
327ac2e7 BS |
274 | env->pil_in |= 1 << irq; |
275 | cpu_check_irqs(env); | |
b3a23197 BS |
276 | } else { |
277 | DPRINTF("Lower CPU IRQ %d\n", irq); | |
327ac2e7 BS |
278 | env->pil_in &= ~(1 << irq); |
279 | cpu_check_irqs(env); | |
b3a23197 BS |
280 | } |
281 | } | |
282 | ||
283 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) | |
284 | { | |
285 | } | |
286 | ||
3475187d FB |
287 | static void *slavio_misc; |
288 | ||
289 | void qemu_system_powerdown(void) | |
290 | { | |
291 | slavio_set_power_fail(slavio_misc, 1); | |
292 | } | |
293 | ||
c68ea704 FB |
294 | static void main_cpu_reset(void *opaque) |
295 | { | |
296 | CPUState *env = opaque; | |
3d29fbef BS |
297 | |
298 | cpu_reset(env); | |
299 | env->halted = 0; | |
300 | } | |
301 | ||
302 | static void secondary_cpu_reset(void *opaque) | |
303 | { | |
304 | CPUState *env = opaque; | |
305 | ||
c68ea704 | 306 | cpu_reset(env); |
3d29fbef | 307 | env->halted = 1; |
c68ea704 FB |
308 | } |
309 | ||
6d0c293d BS |
310 | static void cpu_halt_signal(void *opaque, int irq, int level) |
311 | { | |
312 | if (level && cpu_single_env) | |
313 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); | |
314 | } | |
315 | ||
3ebf5aaf | 316 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
293f78bc BS |
317 | const char *initrd_filename, |
318 | ram_addr_t RAM_size) | |
3ebf5aaf BS |
319 | { |
320 | int linux_boot; | |
321 | unsigned int i; | |
322 | long initrd_size, kernel_size; | |
323 | ||
324 | linux_boot = (kernel_filename != NULL); | |
325 | ||
326 | kernel_size = 0; | |
327 | if (linux_boot) { | |
328 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, | |
329 | NULL); | |
330 | if (kernel_size < 0) | |
293f78bc BS |
331 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
332 | RAM_size - KERNEL_LOAD_ADDR); | |
3ebf5aaf | 333 | if (kernel_size < 0) |
293f78bc BS |
334 | kernel_size = load_image_targphys(kernel_filename, |
335 | KERNEL_LOAD_ADDR, | |
336 | RAM_size - KERNEL_LOAD_ADDR); | |
3ebf5aaf BS |
337 | if (kernel_size < 0) { |
338 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
339 | kernel_filename); | |
340 | exit(1); | |
341 | } | |
342 | ||
343 | /* load initrd */ | |
344 | initrd_size = 0; | |
345 | if (initrd_filename) { | |
293f78bc BS |
346 | initrd_size = load_image_targphys(initrd_filename, |
347 | INITRD_LOAD_ADDR, | |
348 | RAM_size - INITRD_LOAD_ADDR); | |
3ebf5aaf BS |
349 | if (initrd_size < 0) { |
350 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
351 | initrd_filename); | |
352 | exit(1); | |
353 | } | |
354 | } | |
355 | if (initrd_size > 0) { | |
356 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
293f78bc BS |
357 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
358 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
359 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
3ebf5aaf BS |
360 | break; |
361 | } | |
362 | } | |
363 | } | |
364 | } | |
365 | return kernel_size; | |
366 | } | |
367 | ||
4b48bf05 BS |
368 | static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
369 | { | |
370 | DeviceState *dev; | |
371 | SysBusDevice *s; | |
372 | ||
373 | dev = qdev_create(NULL, "iommu"); | |
374 | qdev_prop_set_uint32(dev, "version", version); | |
375 | qdev_init(dev); | |
376 | s = sysbus_from_qdev(dev); | |
377 | sysbus_connect_irq(s, 0, irq); | |
378 | sysbus_mmio_map(s, 0, addr); | |
379 | ||
380 | return s; | |
381 | } | |
382 | ||
9d07d757 PB |
383 | static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
384 | void *dma_opaque, qemu_irq irq, qemu_irq *reset) | |
385 | { | |
386 | DeviceState *dev; | |
387 | SysBusDevice *s; | |
388 | ||
389 | qemu_check_nic_model(&nd_table[0], "lance"); | |
390 | ||
391 | dev = qdev_create(NULL, "lance"); | |
ee6847d1 | 392 | dev->nd = nd; |
daa65491 | 393 | qdev_prop_set_ptr(dev, "dma", dma_opaque); |
9d07d757 PB |
394 | qdev_init(dev); |
395 | s = sysbus_from_qdev(dev); | |
396 | sysbus_mmio_map(s, 0, leaddr); | |
397 | sysbus_connect_irq(s, 0, irq); | |
067a3ddc | 398 | *reset = qdev_get_gpio_in(dev, 0); |
9d07d757 PB |
399 | } |
400 | ||
4b48bf05 BS |
401 | static DeviceState *slavio_intctl_init(target_phys_addr_t addr, |
402 | target_phys_addr_t addrg, | |
403 | const uint32_t *intbit_to_level, | |
404 | qemu_irq **parent_irq, | |
405 | unsigned int cputimer) | |
406 | { | |
407 | DeviceState *dev; | |
408 | SysBusDevice *s; | |
409 | unsigned int i, j; | |
410 | ||
411 | dev = qdev_create(NULL, "slavio_intctl"); | |
412 | qdev_prop_set_ptr(dev, "intbit_to_level", (void *)intbit_to_level); | |
413 | qdev_prop_set_uint32(dev, "cputimer_bit", cputimer); | |
414 | qdev_init(dev); | |
415 | ||
416 | s = sysbus_from_qdev(dev); | |
417 | ||
418 | for (i = 0; i < MAX_CPUS; i++) { | |
419 | for (j = 0; j < MAX_PILS; j++) { | |
420 | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); | |
421 | } | |
422 | } | |
423 | sysbus_mmio_map(s, 0, addrg); | |
424 | for (i = 0; i < MAX_CPUS; i++) { | |
425 | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); | |
426 | } | |
427 | ||
428 | return dev; | |
429 | } | |
430 | ||
431 | #define SYS_TIMER_OFFSET 0x10000ULL | |
432 | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) | |
433 | ||
434 | static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, | |
435 | qemu_irq *cpu_irqs, unsigned int num_cpus) | |
436 | { | |
437 | DeviceState *dev; | |
438 | SysBusDevice *s; | |
439 | unsigned int i; | |
440 | ||
441 | dev = qdev_create(NULL, "slavio_timer"); | |
442 | qdev_prop_set_uint32(dev, "num_cpus", num_cpus); | |
443 | qdev_init(dev); | |
444 | s = sysbus_from_qdev(dev); | |
445 | sysbus_connect_irq(s, 0, master_irq); | |
446 | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); | |
447 | ||
448 | for (i = 0; i < MAX_CPUS; i++) { | |
449 | sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i)); | |
450 | sysbus_connect_irq(s, i + 1, cpu_irqs[i]); | |
451 | } | |
452 | } | |
453 | ||
454 | #define MISC_LEDS 0x01600000 | |
455 | #define MISC_CFG 0x01800000 | |
456 | #define MISC_DIAG 0x01a00000 | |
457 | #define MISC_MDM 0x01b00000 | |
458 | #define MISC_SYS 0x01f00000 | |
459 | ||
460 | static void *slavio_misc_init(target_phys_addr_t base, | |
461 | target_phys_addr_t aux1_base, | |
462 | target_phys_addr_t aux2_base, qemu_irq irq, | |
463 | qemu_irq fdc_tc) | |
464 | { | |
465 | DeviceState *dev; | |
466 | SysBusDevice *s; | |
467 | ||
468 | dev = qdev_create(NULL, "slavio_misc"); | |
469 | qdev_init(dev); | |
470 | s = sysbus_from_qdev(dev); | |
471 | if (base) { | |
472 | /* 8 bit registers */ | |
473 | /* Slavio control */ | |
474 | sysbus_mmio_map(s, 0, base + MISC_CFG); | |
475 | /* Diagnostics */ | |
476 | sysbus_mmio_map(s, 1, base + MISC_DIAG); | |
477 | /* Modem control */ | |
478 | sysbus_mmio_map(s, 2, base + MISC_MDM); | |
479 | /* 16 bit registers */ | |
480 | /* ss600mp diag LEDs */ | |
481 | sysbus_mmio_map(s, 3, base + MISC_LEDS); | |
482 | /* 32 bit registers */ | |
483 | /* System control */ | |
484 | sysbus_mmio_map(s, 4, base + MISC_SYS); | |
485 | } | |
486 | if (aux1_base) { | |
487 | /* AUX 1 (Misc System Functions) */ | |
488 | sysbus_mmio_map(s, 5, aux1_base); | |
489 | } | |
490 | if (aux2_base) { | |
491 | /* AUX 2 (Software Powerdown Control) */ | |
492 | sysbus_mmio_map(s, 6, aux2_base); | |
493 | } | |
494 | sysbus_connect_irq(s, 0, irq); | |
495 | sysbus_connect_irq(s, 1, fdc_tc); | |
496 | ||
497 | return s; | |
498 | } | |
499 | ||
500 | static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) | |
501 | { | |
502 | DeviceState *dev; | |
503 | SysBusDevice *s; | |
504 | ||
505 | dev = qdev_create(NULL, "eccmemctl"); | |
506 | qdev_prop_set_uint32(dev, "version", version); | |
507 | qdev_init(dev); | |
508 | s = sysbus_from_qdev(dev); | |
509 | sysbus_connect_irq(s, 0, irq); | |
510 | sysbus_mmio_map(s, 0, base); | |
511 | if (version == 0) { // SS-600MP only | |
512 | sysbus_mmio_map(s, 1, base + 0x1000); | |
513 | } | |
514 | } | |
515 | ||
516 | static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) | |
517 | { | |
518 | DeviceState *dev; | |
519 | SysBusDevice *s; | |
520 | ||
521 | dev = qdev_create(NULL, "apc"); | |
522 | qdev_init(dev); | |
523 | s = sysbus_from_qdev(dev); | |
524 | /* Power management (APC) XXX: not a Slavio device */ | |
525 | sysbus_mmio_map(s, 0, power_base); | |
526 | sysbus_connect_irq(s, 0, cpu_halt); | |
527 | } | |
528 | ||
529 | static void tcx_init(target_phys_addr_t addr, int vram_size, int width, | |
530 | int height, int depth) | |
531 | { | |
532 | DeviceState *dev; | |
533 | SysBusDevice *s; | |
534 | ||
535 | dev = qdev_create(NULL, "SUNW,tcx"); | |
536 | qdev_prop_set_taddr(dev, "addr", addr); | |
537 | qdev_prop_set_uint32(dev, "vram_size", vram_size); | |
538 | qdev_prop_set_uint16(dev, "width", width); | |
539 | qdev_prop_set_uint16(dev, "height", height); | |
540 | qdev_prop_set_uint16(dev, "depth", depth); | |
541 | qdev_init(dev); | |
542 | s = sysbus_from_qdev(dev); | |
543 | /* 8-bit plane */ | |
544 | sysbus_mmio_map(s, 0, addr + 0x00800000ULL); | |
545 | /* DAC */ | |
546 | sysbus_mmio_map(s, 1, addr + 0x00200000ULL); | |
547 | /* TEC (dummy) */ | |
548 | sysbus_mmio_map(s, 2, addr + 0x00700000ULL); | |
549 | /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ | |
550 | sysbus_mmio_map(s, 3, addr + 0x00301000ULL); | |
551 | if (depth == 24) { | |
552 | /* 24-bit plane */ | |
553 | sysbus_mmio_map(s, 4, addr + 0x02000000ULL); | |
554 | /* Control plane */ | |
555 | sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); | |
556 | } else { | |
557 | /* THC 8 bit (dummy) */ | |
558 | sysbus_mmio_map(s, 4, addr + 0x00300000ULL); | |
559 | } | |
560 | } | |
561 | ||
325f2747 BS |
562 | /* NCR89C100/MACIO Internal ID register */ |
563 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; | |
564 | ||
565 | static void idreg_init(target_phys_addr_t addr) | |
566 | { | |
567 | DeviceState *dev; | |
568 | SysBusDevice *s; | |
569 | ||
570 | dev = qdev_create(NULL, "macio_idreg"); | |
571 | qdev_init(dev); | |
572 | s = sysbus_from_qdev(dev); | |
573 | ||
574 | sysbus_mmio_map(s, 0, addr); | |
575 | cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data)); | |
576 | } | |
577 | ||
578 | static void idreg_init1(SysBusDevice *dev) | |
579 | { | |
580 | ram_addr_t idreg_offset; | |
581 | ||
582 | idreg_offset = qemu_ram_alloc(sizeof(idreg_data)); | |
583 | sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM); | |
584 | } | |
585 | ||
586 | static SysBusDeviceInfo idreg_info = { | |
587 | .init = idreg_init1, | |
588 | .qdev.name = "macio_idreg", | |
589 | .qdev.size = sizeof(SysBusDevice), | |
325f2747 BS |
590 | }; |
591 | ||
592 | static void idreg_register_devices(void) | |
593 | { | |
594 | sysbus_register_withprop(&idreg_info); | |
595 | } | |
596 | ||
597 | device_init(idreg_register_devices); | |
598 | ||
f48f6569 BS |
599 | /* Boot PROM (OpenBIOS) */ |
600 | static void prom_init(target_phys_addr_t addr, const char *bios_name) | |
601 | { | |
602 | DeviceState *dev; | |
603 | SysBusDevice *s; | |
604 | char *filename; | |
605 | int ret; | |
606 | ||
607 | dev = qdev_create(NULL, "openprom"); | |
608 | qdev_init(dev); | |
609 | s = sysbus_from_qdev(dev); | |
610 | ||
611 | sysbus_mmio_map(s, 0, addr); | |
612 | ||
613 | /* load boot prom */ | |
614 | if (bios_name == NULL) { | |
615 | bios_name = PROM_FILENAME; | |
616 | } | |
617 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
618 | if (filename) { | |
619 | ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL); | |
620 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
621 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
622 | } | |
623 | qemu_free(filename); | |
624 | } else { | |
625 | ret = -1; | |
626 | } | |
627 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
628 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
629 | exit(1); | |
630 | } | |
631 | } | |
632 | ||
633 | static void prom_init1(SysBusDevice *dev) | |
634 | { | |
635 | ram_addr_t prom_offset; | |
636 | ||
637 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); | |
638 | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); | |
639 | } | |
640 | ||
641 | static SysBusDeviceInfo prom_info = { | |
642 | .init = prom_init1, | |
643 | .qdev.name = "openprom", | |
644 | .qdev.size = sizeof(SysBusDevice), | |
ee6847d1 GH |
645 | .qdev.props = (Property[]) { |
646 | {/* end of property list */} | |
f48f6569 BS |
647 | } |
648 | }; | |
649 | ||
650 | static void prom_register_devices(void) | |
651 | { | |
652 | sysbus_register_withprop(&prom_info); | |
653 | } | |
654 | ||
655 | device_init(prom_register_devices); | |
656 | ||
ee6847d1 GH |
657 | typedef struct RamDevice |
658 | { | |
659 | SysBusDevice busdev; | |
04843626 | 660 | uint64_t size; |
ee6847d1 GH |
661 | } RamDevice; |
662 | ||
a350db85 BS |
663 | /* System RAM */ |
664 | static void ram_init1(SysBusDevice *dev) | |
665 | { | |
666 | ram_addr_t RAM_size, ram_offset; | |
ee6847d1 | 667 | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
a350db85 | 668 | |
ee6847d1 | 669 | RAM_size = d->size; |
a350db85 BS |
670 | |
671 | ram_offset = qemu_ram_alloc(RAM_size); | |
672 | sysbus_init_mmio(dev, RAM_size, ram_offset); | |
673 | } | |
674 | ||
675 | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, | |
676 | uint64_t max_mem) | |
677 | { | |
678 | DeviceState *dev; | |
679 | SysBusDevice *s; | |
ee6847d1 | 680 | RamDevice *d; |
a350db85 BS |
681 | |
682 | /* allocate RAM */ | |
683 | if ((uint64_t)RAM_size > max_mem) { | |
684 | fprintf(stderr, | |
685 | "qemu: Too much memory for this machine: %d, maximum %d\n", | |
686 | (unsigned int)(RAM_size / (1024 * 1024)), | |
687 | (unsigned int)(max_mem / (1024 * 1024))); | |
688 | exit(1); | |
689 | } | |
690 | dev = qdev_create(NULL, "memory"); | |
a350db85 BS |
691 | s = sysbus_from_qdev(dev); |
692 | ||
ee6847d1 GH |
693 | d = FROM_SYSBUS(RamDevice, s); |
694 | d->size = RAM_size; | |
f6e097e7 | 695 | qdev_init(dev); |
ee6847d1 | 696 | |
a350db85 BS |
697 | sysbus_mmio_map(s, 0, addr); |
698 | } | |
699 | ||
700 | static SysBusDeviceInfo ram_info = { | |
701 | .init = ram_init1, | |
702 | .qdev.name = "memory", | |
ee6847d1 GH |
703 | .qdev.size = sizeof(RamDevice), |
704 | .qdev.props = (Property[]) { | |
705 | { | |
706 | .name = "size", | |
04843626 | 707 | .info = &qdev_prop_uint64, |
ee6847d1 GH |
708 | .offset = offsetof(RamDevice, size), |
709 | }, | |
710 | {/* end of property list */} | |
a350db85 BS |
711 | } |
712 | }; | |
713 | ||
714 | static void ram_register_devices(void) | |
715 | { | |
716 | sysbus_register_withprop(&ram_info); | |
717 | } | |
718 | ||
719 | device_init(ram_register_devices); | |
720 | ||
666713c0 BS |
721 | static CPUState *cpu_devinit(const char *cpu_model, unsigned int id, |
722 | uint64_t prom_addr, qemu_irq **cpu_irqs) | |
723 | { | |
724 | CPUState *env; | |
725 | ||
726 | env = cpu_init(cpu_model); | |
727 | if (!env) { | |
728 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); | |
729 | exit(1); | |
730 | } | |
731 | ||
732 | cpu_sparc_set_id(env, id); | |
733 | if (id == 0) { | |
734 | qemu_register_reset(main_cpu_reset, env); | |
735 | } else { | |
736 | qemu_register_reset(secondary_cpu_reset, env); | |
737 | env->halted = 1; | |
738 | } | |
739 | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | |
740 | env->prom_addr = prom_addr; | |
741 | ||
742 | return env; | |
743 | } | |
744 | ||
8137cde8 | 745 | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
3ebf5aaf | 746 | const char *boot_device, |
3023f332 | 747 | const char *kernel_filename, |
3ebf5aaf BS |
748 | const char *kernel_cmdline, |
749 | const char *initrd_filename, const char *cpu_model) | |
420557e8 | 750 | { |
666713c0 | 751 | CPUState *envs[MAX_CPUS]; |
713c45fa | 752 | unsigned int i; |
cfb9de9c | 753 | void *iommu, *espdma, *ledma, *nvram; |
a1961a4b | 754 | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], |
6f6260c7 | 755 | espdma_irq, ledma_irq; |
2d069bab | 756 | qemu_irq *esp_reset, *le_reset; |
2582cfa0 | 757 | qemu_irq fdc_tc; |
6d0c293d | 758 | qemu_irq *cpu_halt; |
5c6602c5 | 759 | unsigned long kernel_size; |
e4bcb14c | 760 | BlockDriverState *fd[MAX_FD]; |
3cce6243 | 761 | void *fw_cfg; |
a1961a4b | 762 | DeviceState *dev; |
751c6a17 | 763 | DriveInfo *dinfo; |
420557e8 | 764 | |
ba3c64fb | 765 | /* init CPUs */ |
3ebf5aaf BS |
766 | if (!cpu_model) |
767 | cpu_model = hwdef->default_cpu_model; | |
b3a23197 | 768 | |
ba3c64fb | 769 | for(i = 0; i < smp_cpus; i++) { |
666713c0 | 770 | envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
ba3c64fb | 771 | } |
b3a23197 BS |
772 | |
773 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
774 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
775 | ||
3ebf5aaf | 776 | |
3ebf5aaf | 777 | /* set up devices */ |
a350db85 BS |
778 | ram_init(0, RAM_size, hwdef->max_mem); |
779 | ||
f48f6569 BS |
780 | prom_init(hwdef->slavio_base, bios_name); |
781 | ||
a1961a4b BS |
782 | dev = slavio_intctl_init(hwdef->intctl_base, |
783 | hwdef->intctl_base + 0x10000ULL, | |
784 | &hwdef->intbit_to_level[0], | |
785 | cpu_irqs, | |
786 | hwdef->clock_irq); | |
787 | ||
788 | for (i = 0; i < 32; i++) { | |
789 | slavio_irq[i] = qdev_get_gpio_in(dev, i); | |
790 | } | |
791 | for (i = 0; i < MAX_CPUS; i++) { | |
792 | slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i); | |
793 | } | |
b3a23197 | 794 | |
fe096129 | 795 | if (hwdef->idreg_base) { |
325f2747 | 796 | idreg_init(hwdef->idreg_base); |
4c2485de BS |
797 | } |
798 | ||
ff403da6 BS |
799 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
800 | slavio_irq[hwdef->me_irq]); | |
801 | ||
5aca8c3b | 802 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
2d069bab BS |
803 | iommu, &espdma_irq, &esp_reset); |
804 | ||
5aca8c3b | 805 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, |
2d069bab BS |
806 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
807 | &le_reset); | |
ba3c64fb | 808 | |
eee0b836 BS |
809 | if (graphic_depth != 8 && graphic_depth != 24) { |
810 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
811 | exit (1); | |
812 | } | |
dc828ca1 PB |
813 | tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height, |
814 | graphic_depth); | |
dbe06e18 | 815 | |
6f6260c7 | 816 | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset); |
dbe06e18 | 817 | |
d537cf6c PB |
818 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
819 | hwdef->nvram_size, 8); | |
81732d19 BS |
820 | |
821 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], | |
19f8e5dd | 822 | slavio_cpu_irq, smp_cpus); |
81732d19 | 823 | |
577390ff | 824 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
993fbfdb | 825 | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); |
b81b3b10 FB |
826 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
827 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
aeeb69c7 AJ |
828 | escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq], |
829 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); | |
741402f9 | 830 | |
6d0c293d | 831 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
2582cfa0 | 832 | slavio_misc = slavio_misc_init(hwdef->slavio_base, |
2be17ebd | 833 | hwdef->aux1_base, hwdef->aux2_base, |
2582cfa0 BS |
834 | slavio_irq[hwdef->me_irq], fdc_tc); |
835 | if (hwdef->apc_base) { | |
836 | apc_init(hwdef->apc_base, cpu_halt[0]); | |
837 | } | |
2be17ebd | 838 | |
fe096129 | 839 | if (hwdef->fd_base) { |
e4bcb14c | 840 | /* there is zero or one floppy drive */ |
309e60bd | 841 | memset(fd, 0, sizeof(fd)); |
751c6a17 GH |
842 | dinfo = drive_get(IF_FLOPPY, 0, 0); |
843 | if (dinfo) | |
844 | fd[0] = dinfo->bdrv; | |
2d069bab | 845 | |
2be17ebd | 846 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
2582cfa0 | 847 | &fdc_tc); |
e4bcb14c TS |
848 | } |
849 | ||
850 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
851 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
852 | exit(1); | |
853 | } | |
854 | ||
cfb9de9c PB |
855 | esp_init(hwdef->esp_base, 2, |
856 | espdma_memory_read, espdma_memory_write, | |
6f6260c7 | 857 | espdma, espdma_irq, esp_reset); |
f1587550 | 858 | |
fa28ec52 BS |
859 | if (hwdef->cs_base) { |
860 | sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, | |
861 | slavio_irq[hwdef->cs_irq]); | |
862 | } | |
b3ceef24 | 863 | |
293f78bc BS |
864 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
865 | RAM_size); | |
36cd9210 | 866 | |
36cd9210 | 867 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, |
b3ceef24 | 868 | boot_device, RAM_size, kernel_size, graphic_width, |
905fdcb5 BS |
869 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
870 | "Sun4m"); | |
7eb0c8e8 | 871 | |
fe096129 | 872 | if (hwdef->ecc_base) |
e42c20b4 BS |
873 | ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq], |
874 | hwdef->ecc_version); | |
3cce6243 BS |
875 | |
876 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); | |
877 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 BS |
878 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
879 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
fbfcf955 | 880 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
513f789f BS |
881 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
882 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
883 | if (kernel_cmdline) { | |
884 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
885 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
886 | } else { | |
887 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
888 | } | |
889 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
890 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used | |
891 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
892 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
36cd9210 BS |
893 | } |
894 | ||
905fdcb5 BS |
895 | enum { |
896 | ss2_id = 0, | |
897 | ss5_id = 32, | |
898 | vger_id, | |
899 | lx_id, | |
900 | ss4_id, | |
901 | scls_id, | |
902 | sbook_id, | |
903 | ss10_id = 64, | |
904 | ss20_id, | |
905 | ss600mp_id, | |
906 | ss1000_id = 96, | |
907 | ss2000_id, | |
908 | }; | |
909 | ||
8137cde8 | 910 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
36cd9210 BS |
911 | /* SS-5 */ |
912 | { | |
913 | .iommu_base = 0x10000000, | |
914 | .tcx_base = 0x50000000, | |
915 | .cs_base = 0x6c000000, | |
384ccb5d | 916 | .slavio_base = 0x70000000, |
36cd9210 BS |
917 | .ms_kb_base = 0x71000000, |
918 | .serial_base = 0x71100000, | |
919 | .nvram_base = 0x71200000, | |
920 | .fd_base = 0x71400000, | |
921 | .counter_base = 0x71d00000, | |
922 | .intctl_base = 0x71e00000, | |
4c2485de | 923 | .idreg_base = 0x78000000, |
36cd9210 BS |
924 | .dma_base = 0x78400000, |
925 | .esp_base = 0x78800000, | |
926 | .le_base = 0x78c00000, | |
127fc407 | 927 | .apc_base = 0x6a000000, |
0019ad53 BS |
928 | .aux1_base = 0x71900000, |
929 | .aux2_base = 0x71910000, | |
36cd9210 BS |
930 | .vram_size = 0x00100000, |
931 | .nvram_size = 0x2000, | |
932 | .esp_irq = 18, | |
933 | .le_irq = 16, | |
e3a79bca | 934 | .clock_irq = 7, |
36cd9210 BS |
935 | .clock1_irq = 19, |
936 | .ms_kb_irq = 14, | |
937 | .ser_irq = 15, | |
938 | .fd_irq = 22, | |
939 | .me_irq = 30, | |
940 | .cs_irq = 5, | |
905fdcb5 BS |
941 | .nvram_machine_id = 0x80, |
942 | .machine_id = ss5_id, | |
cf3102ac | 943 | .iommu_version = 0x05000000, |
e0353fe2 | 944 | .intbit_to_level = { |
f930d07e BS |
945 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
946 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
e0353fe2 | 947 | }, |
3ebf5aaf BS |
948 | .max_mem = 0x10000000, |
949 | .default_cpu_model = "Fujitsu MB86904", | |
e0353fe2 BS |
950 | }, |
951 | /* SS-10 */ | |
e0353fe2 | 952 | { |
5dcb6b91 BS |
953 | .iommu_base = 0xfe0000000ULL, |
954 | .tcx_base = 0xe20000000ULL, | |
5dcb6b91 BS |
955 | .slavio_base = 0xff0000000ULL, |
956 | .ms_kb_base = 0xff1000000ULL, | |
957 | .serial_base = 0xff1100000ULL, | |
958 | .nvram_base = 0xff1200000ULL, | |
959 | .fd_base = 0xff1700000ULL, | |
960 | .counter_base = 0xff1300000ULL, | |
961 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 962 | .idreg_base = 0xef0000000ULL, |
5dcb6b91 BS |
963 | .dma_base = 0xef0400000ULL, |
964 | .esp_base = 0xef0800000ULL, | |
965 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 966 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
967 | .aux1_base = 0xff1800000ULL, |
968 | .aux2_base = 0xff1a01000ULL, | |
7eb0c8e8 BS |
969 | .ecc_base = 0xf00000000ULL, |
970 | .ecc_version = 0x10000000, // version 0, implementation 1 | |
e0353fe2 BS |
971 | .vram_size = 0x00100000, |
972 | .nvram_size = 0x2000, | |
973 | .esp_irq = 18, | |
974 | .le_irq = 16, | |
e3a79bca | 975 | .clock_irq = 7, |
e0353fe2 BS |
976 | .clock1_irq = 19, |
977 | .ms_kb_irq = 14, | |
978 | .ser_irq = 15, | |
979 | .fd_irq = 22, | |
980 | .me_irq = 30, | |
e42c20b4 | 981 | .ecc_irq = 28, |
905fdcb5 BS |
982 | .nvram_machine_id = 0x72, |
983 | .machine_id = ss10_id, | |
7fbfb139 | 984 | .iommu_version = 0x03000000, |
e0353fe2 | 985 | .intbit_to_level = { |
f930d07e BS |
986 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
987 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
e0353fe2 | 988 | }, |
6ef05b95 | 989 | .max_mem = 0xf00000000ULL, |
3ebf5aaf | 990 | .default_cpu_model = "TI SuperSparc II", |
36cd9210 | 991 | }, |
6a3b9cc9 BS |
992 | /* SS-600MP */ |
993 | { | |
994 | .iommu_base = 0xfe0000000ULL, | |
995 | .tcx_base = 0xe20000000ULL, | |
6a3b9cc9 BS |
996 | .slavio_base = 0xff0000000ULL, |
997 | .ms_kb_base = 0xff1000000ULL, | |
998 | .serial_base = 0xff1100000ULL, | |
999 | .nvram_base = 0xff1200000ULL, | |
6a3b9cc9 BS |
1000 | .counter_base = 0xff1300000ULL, |
1001 | .intctl_base = 0xff1400000ULL, | |
1002 | .dma_base = 0xef0081000ULL, | |
1003 | .esp_base = 0xef0080000ULL, | |
1004 | .le_base = 0xef0060000ULL, | |
0019ad53 | 1005 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
1006 | .aux1_base = 0xff1800000ULL, |
1007 | .aux2_base = 0xff1a01000ULL, // XXX should not exist | |
7eb0c8e8 BS |
1008 | .ecc_base = 0xf00000000ULL, |
1009 | .ecc_version = 0x00000000, // version 0, implementation 0 | |
6a3b9cc9 BS |
1010 | .vram_size = 0x00100000, |
1011 | .nvram_size = 0x2000, | |
1012 | .esp_irq = 18, | |
1013 | .le_irq = 16, | |
e3a79bca | 1014 | .clock_irq = 7, |
6a3b9cc9 BS |
1015 | .clock1_irq = 19, |
1016 | .ms_kb_irq = 14, | |
1017 | .ser_irq = 15, | |
1018 | .fd_irq = 22, | |
1019 | .me_irq = 30, | |
e42c20b4 | 1020 | .ecc_irq = 28, |
905fdcb5 BS |
1021 | .nvram_machine_id = 0x71, |
1022 | .machine_id = ss600mp_id, | |
7fbfb139 | 1023 | .iommu_version = 0x01000000, |
6a3b9cc9 BS |
1024 | .intbit_to_level = { |
1025 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1026 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1027 | }, | |
6ef05b95 | 1028 | .max_mem = 0xf00000000ULL, |
3ebf5aaf | 1029 | .default_cpu_model = "TI SuperSparc II", |
6a3b9cc9 | 1030 | }, |
ae40972f BS |
1031 | /* SS-20 */ |
1032 | { | |
1033 | .iommu_base = 0xfe0000000ULL, | |
1034 | .tcx_base = 0xe20000000ULL, | |
ae40972f BS |
1035 | .slavio_base = 0xff0000000ULL, |
1036 | .ms_kb_base = 0xff1000000ULL, | |
1037 | .serial_base = 0xff1100000ULL, | |
1038 | .nvram_base = 0xff1200000ULL, | |
1039 | .fd_base = 0xff1700000ULL, | |
1040 | .counter_base = 0xff1300000ULL, | |
1041 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1042 | .idreg_base = 0xef0000000ULL, |
ae40972f BS |
1043 | .dma_base = 0xef0400000ULL, |
1044 | .esp_base = 0xef0800000ULL, | |
1045 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 1046 | .apc_base = 0xefa000000ULL, // XXX should not exist |
577d8dd4 BS |
1047 | .aux1_base = 0xff1800000ULL, |
1048 | .aux2_base = 0xff1a01000ULL, | |
ae40972f BS |
1049 | .ecc_base = 0xf00000000ULL, |
1050 | .ecc_version = 0x20000000, // version 0, implementation 2 | |
1051 | .vram_size = 0x00100000, | |
1052 | .nvram_size = 0x2000, | |
1053 | .esp_irq = 18, | |
1054 | .le_irq = 16, | |
e3a79bca | 1055 | .clock_irq = 7, |
ae40972f BS |
1056 | .clock1_irq = 19, |
1057 | .ms_kb_irq = 14, | |
1058 | .ser_irq = 15, | |
1059 | .fd_irq = 22, | |
1060 | .me_irq = 30, | |
e42c20b4 | 1061 | .ecc_irq = 28, |
905fdcb5 BS |
1062 | .nvram_machine_id = 0x72, |
1063 | .machine_id = ss20_id, | |
ae40972f BS |
1064 | .iommu_version = 0x13000000, |
1065 | .intbit_to_level = { | |
1066 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1067 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1068 | }, | |
6ef05b95 | 1069 | .max_mem = 0xf00000000ULL, |
ae40972f BS |
1070 | .default_cpu_model = "TI SuperSparc II", |
1071 | }, | |
a526a31c BS |
1072 | /* Voyager */ |
1073 | { | |
1074 | .iommu_base = 0x10000000, | |
1075 | .tcx_base = 0x50000000, | |
a526a31c BS |
1076 | .slavio_base = 0x70000000, |
1077 | .ms_kb_base = 0x71000000, | |
1078 | .serial_base = 0x71100000, | |
1079 | .nvram_base = 0x71200000, | |
1080 | .fd_base = 0x71400000, | |
1081 | .counter_base = 0x71d00000, | |
1082 | .intctl_base = 0x71e00000, | |
1083 | .idreg_base = 0x78000000, | |
1084 | .dma_base = 0x78400000, | |
1085 | .esp_base = 0x78800000, | |
1086 | .le_base = 0x78c00000, | |
1087 | .apc_base = 0x71300000, // pmc | |
1088 | .aux1_base = 0x71900000, | |
1089 | .aux2_base = 0x71910000, | |
a526a31c BS |
1090 | .vram_size = 0x00100000, |
1091 | .nvram_size = 0x2000, | |
1092 | .esp_irq = 18, | |
1093 | .le_irq = 16, | |
1094 | .clock_irq = 7, | |
1095 | .clock1_irq = 19, | |
1096 | .ms_kb_irq = 14, | |
1097 | .ser_irq = 15, | |
1098 | .fd_irq = 22, | |
1099 | .me_irq = 30, | |
905fdcb5 BS |
1100 | .nvram_machine_id = 0x80, |
1101 | .machine_id = vger_id, | |
a526a31c BS |
1102 | .iommu_version = 0x05000000, |
1103 | .intbit_to_level = { | |
1104 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1105 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1106 | }, | |
1107 | .max_mem = 0x10000000, | |
1108 | .default_cpu_model = "Fujitsu MB86904", | |
1109 | }, | |
1110 | /* LX */ | |
1111 | { | |
1112 | .iommu_base = 0x10000000, | |
1113 | .tcx_base = 0x50000000, | |
a526a31c BS |
1114 | .slavio_base = 0x70000000, |
1115 | .ms_kb_base = 0x71000000, | |
1116 | .serial_base = 0x71100000, | |
1117 | .nvram_base = 0x71200000, | |
1118 | .fd_base = 0x71400000, | |
1119 | .counter_base = 0x71d00000, | |
1120 | .intctl_base = 0x71e00000, | |
1121 | .idreg_base = 0x78000000, | |
1122 | .dma_base = 0x78400000, | |
1123 | .esp_base = 0x78800000, | |
1124 | .le_base = 0x78c00000, | |
a526a31c BS |
1125 | .aux1_base = 0x71900000, |
1126 | .aux2_base = 0x71910000, | |
a526a31c BS |
1127 | .vram_size = 0x00100000, |
1128 | .nvram_size = 0x2000, | |
1129 | .esp_irq = 18, | |
1130 | .le_irq = 16, | |
1131 | .clock_irq = 7, | |
1132 | .clock1_irq = 19, | |
1133 | .ms_kb_irq = 14, | |
1134 | .ser_irq = 15, | |
1135 | .fd_irq = 22, | |
1136 | .me_irq = 30, | |
905fdcb5 BS |
1137 | .nvram_machine_id = 0x80, |
1138 | .machine_id = lx_id, | |
a526a31c BS |
1139 | .iommu_version = 0x04000000, |
1140 | .intbit_to_level = { | |
1141 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1142 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1143 | }, | |
1144 | .max_mem = 0x10000000, | |
1145 | .default_cpu_model = "TI MicroSparc I", | |
1146 | }, | |
1147 | /* SS-4 */ | |
1148 | { | |
1149 | .iommu_base = 0x10000000, | |
1150 | .tcx_base = 0x50000000, | |
1151 | .cs_base = 0x6c000000, | |
1152 | .slavio_base = 0x70000000, | |
1153 | .ms_kb_base = 0x71000000, | |
1154 | .serial_base = 0x71100000, | |
1155 | .nvram_base = 0x71200000, | |
1156 | .fd_base = 0x71400000, | |
1157 | .counter_base = 0x71d00000, | |
1158 | .intctl_base = 0x71e00000, | |
1159 | .idreg_base = 0x78000000, | |
1160 | .dma_base = 0x78400000, | |
1161 | .esp_base = 0x78800000, | |
1162 | .le_base = 0x78c00000, | |
1163 | .apc_base = 0x6a000000, | |
1164 | .aux1_base = 0x71900000, | |
1165 | .aux2_base = 0x71910000, | |
a526a31c BS |
1166 | .vram_size = 0x00100000, |
1167 | .nvram_size = 0x2000, | |
1168 | .esp_irq = 18, | |
1169 | .le_irq = 16, | |
1170 | .clock_irq = 7, | |
1171 | .clock1_irq = 19, | |
1172 | .ms_kb_irq = 14, | |
1173 | .ser_irq = 15, | |
1174 | .fd_irq = 22, | |
1175 | .me_irq = 30, | |
1176 | .cs_irq = 5, | |
905fdcb5 BS |
1177 | .nvram_machine_id = 0x80, |
1178 | .machine_id = ss4_id, | |
a526a31c BS |
1179 | .iommu_version = 0x05000000, |
1180 | .intbit_to_level = { | |
1181 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1182 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1183 | }, | |
1184 | .max_mem = 0x10000000, | |
1185 | .default_cpu_model = "Fujitsu MB86904", | |
1186 | }, | |
1187 | /* SPARCClassic */ | |
1188 | { | |
1189 | .iommu_base = 0x10000000, | |
1190 | .tcx_base = 0x50000000, | |
a526a31c BS |
1191 | .slavio_base = 0x70000000, |
1192 | .ms_kb_base = 0x71000000, | |
1193 | .serial_base = 0x71100000, | |
1194 | .nvram_base = 0x71200000, | |
1195 | .fd_base = 0x71400000, | |
1196 | .counter_base = 0x71d00000, | |
1197 | .intctl_base = 0x71e00000, | |
1198 | .idreg_base = 0x78000000, | |
1199 | .dma_base = 0x78400000, | |
1200 | .esp_base = 0x78800000, | |
1201 | .le_base = 0x78c00000, | |
1202 | .apc_base = 0x6a000000, | |
1203 | .aux1_base = 0x71900000, | |
1204 | .aux2_base = 0x71910000, | |
a526a31c BS |
1205 | .vram_size = 0x00100000, |
1206 | .nvram_size = 0x2000, | |
1207 | .esp_irq = 18, | |
1208 | .le_irq = 16, | |
1209 | .clock_irq = 7, | |
1210 | .clock1_irq = 19, | |
1211 | .ms_kb_irq = 14, | |
1212 | .ser_irq = 15, | |
1213 | .fd_irq = 22, | |
1214 | .me_irq = 30, | |
905fdcb5 BS |
1215 | .nvram_machine_id = 0x80, |
1216 | .machine_id = scls_id, | |
a526a31c BS |
1217 | .iommu_version = 0x05000000, |
1218 | .intbit_to_level = { | |
1219 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1220 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1221 | }, | |
1222 | .max_mem = 0x10000000, | |
1223 | .default_cpu_model = "TI MicroSparc I", | |
1224 | }, | |
1225 | /* SPARCbook */ | |
1226 | { | |
1227 | .iommu_base = 0x10000000, | |
1228 | .tcx_base = 0x50000000, // XXX | |
a526a31c BS |
1229 | .slavio_base = 0x70000000, |
1230 | .ms_kb_base = 0x71000000, | |
1231 | .serial_base = 0x71100000, | |
1232 | .nvram_base = 0x71200000, | |
1233 | .fd_base = 0x71400000, | |
1234 | .counter_base = 0x71d00000, | |
1235 | .intctl_base = 0x71e00000, | |
1236 | .idreg_base = 0x78000000, | |
1237 | .dma_base = 0x78400000, | |
1238 | .esp_base = 0x78800000, | |
1239 | .le_base = 0x78c00000, | |
1240 | .apc_base = 0x6a000000, | |
1241 | .aux1_base = 0x71900000, | |
1242 | .aux2_base = 0x71910000, | |
a526a31c BS |
1243 | .vram_size = 0x00100000, |
1244 | .nvram_size = 0x2000, | |
1245 | .esp_irq = 18, | |
1246 | .le_irq = 16, | |
1247 | .clock_irq = 7, | |
1248 | .clock1_irq = 19, | |
1249 | .ms_kb_irq = 14, | |
1250 | .ser_irq = 15, | |
1251 | .fd_irq = 22, | |
1252 | .me_irq = 30, | |
905fdcb5 BS |
1253 | .nvram_machine_id = 0x80, |
1254 | .machine_id = sbook_id, | |
a526a31c BS |
1255 | .iommu_version = 0x05000000, |
1256 | .intbit_to_level = { | |
1257 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1258 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1259 | }, | |
1260 | .max_mem = 0x10000000, | |
1261 | .default_cpu_model = "TI MicroSparc I", | |
1262 | }, | |
36cd9210 BS |
1263 | }; |
1264 | ||
36cd9210 | 1265 | /* SPARCstation 5 hardware initialisation */ |
fbe1b595 | 1266 | static void ss5_init(ram_addr_t RAM_size, |
3023f332 | 1267 | const char *boot_device, |
b881c2c6 BS |
1268 | const char *kernel_filename, const char *kernel_cmdline, |
1269 | const char *initrd_filename, const char *cpu_model) | |
36cd9210 | 1270 | { |
3023f332 | 1271 | sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, |
3ebf5aaf | 1272 | kernel_cmdline, initrd_filename, cpu_model); |
420557e8 | 1273 | } |
c0e564d5 | 1274 | |
e0353fe2 | 1275 | /* SPARCstation 10 hardware initialisation */ |
fbe1b595 | 1276 | static void ss10_init(ram_addr_t RAM_size, |
3023f332 | 1277 | const char *boot_device, |
b881c2c6 BS |
1278 | const char *kernel_filename, const char *kernel_cmdline, |
1279 | const char *initrd_filename, const char *cpu_model) | |
e0353fe2 | 1280 | { |
3023f332 | 1281 | sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, |
3ebf5aaf | 1282 | kernel_cmdline, initrd_filename, cpu_model); |
e0353fe2 BS |
1283 | } |
1284 | ||
6a3b9cc9 | 1285 | /* SPARCserver 600MP hardware initialisation */ |
fbe1b595 | 1286 | static void ss600mp_init(ram_addr_t RAM_size, |
3023f332 | 1287 | const char *boot_device, |
77f193da BS |
1288 | const char *kernel_filename, |
1289 | const char *kernel_cmdline, | |
6a3b9cc9 BS |
1290 | const char *initrd_filename, const char *cpu_model) |
1291 | { | |
3023f332 | 1292 | sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, |
3ebf5aaf | 1293 | kernel_cmdline, initrd_filename, cpu_model); |
6a3b9cc9 BS |
1294 | } |
1295 | ||
ae40972f | 1296 | /* SPARCstation 20 hardware initialisation */ |
fbe1b595 | 1297 | static void ss20_init(ram_addr_t RAM_size, |
3023f332 | 1298 | const char *boot_device, |
ae40972f BS |
1299 | const char *kernel_filename, const char *kernel_cmdline, |
1300 | const char *initrd_filename, const char *cpu_model) | |
1301 | { | |
3023f332 | 1302 | sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, |
ee76f82e BS |
1303 | kernel_cmdline, initrd_filename, cpu_model); |
1304 | } | |
1305 | ||
a526a31c | 1306 | /* SPARCstation Voyager hardware initialisation */ |
fbe1b595 | 1307 | static void vger_init(ram_addr_t RAM_size, |
3023f332 | 1308 | const char *boot_device, |
a526a31c BS |
1309 | const char *kernel_filename, const char *kernel_cmdline, |
1310 | const char *initrd_filename, const char *cpu_model) | |
1311 | { | |
3023f332 | 1312 | sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1313 | kernel_cmdline, initrd_filename, cpu_model); |
1314 | } | |
1315 | ||
1316 | /* SPARCstation LX hardware initialisation */ | |
fbe1b595 | 1317 | static void ss_lx_init(ram_addr_t RAM_size, |
3023f332 | 1318 | const char *boot_device, |
a526a31c BS |
1319 | const char *kernel_filename, const char *kernel_cmdline, |
1320 | const char *initrd_filename, const char *cpu_model) | |
1321 | { | |
3023f332 | 1322 | sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1323 | kernel_cmdline, initrd_filename, cpu_model); |
1324 | } | |
1325 | ||
1326 | /* SPARCstation 4 hardware initialisation */ | |
fbe1b595 | 1327 | static void ss4_init(ram_addr_t RAM_size, |
3023f332 | 1328 | const char *boot_device, |
a526a31c BS |
1329 | const char *kernel_filename, const char *kernel_cmdline, |
1330 | const char *initrd_filename, const char *cpu_model) | |
1331 | { | |
3023f332 | 1332 | sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1333 | kernel_cmdline, initrd_filename, cpu_model); |
1334 | } | |
1335 | ||
1336 | /* SPARCClassic hardware initialisation */ | |
fbe1b595 | 1337 | static void scls_init(ram_addr_t RAM_size, |
3023f332 | 1338 | const char *boot_device, |
a526a31c BS |
1339 | const char *kernel_filename, const char *kernel_cmdline, |
1340 | const char *initrd_filename, const char *cpu_model) | |
1341 | { | |
3023f332 | 1342 | sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1343 | kernel_cmdline, initrd_filename, cpu_model); |
1344 | } | |
1345 | ||
1346 | /* SPARCbook hardware initialisation */ | |
fbe1b595 | 1347 | static void sbook_init(ram_addr_t RAM_size, |
3023f332 | 1348 | const char *boot_device, |
a526a31c BS |
1349 | const char *kernel_filename, const char *kernel_cmdline, |
1350 | const char *initrd_filename, const char *cpu_model) | |
1351 | { | |
3023f332 | 1352 | sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1353 | kernel_cmdline, initrd_filename, cpu_model); |
1354 | } | |
1355 | ||
f80f9ec9 | 1356 | static QEMUMachine ss5_machine = { |
66de733b BS |
1357 | .name = "SS-5", |
1358 | .desc = "Sun4m platform, SPARCstation 5", | |
1359 | .init = ss5_init, | |
c9b1ae2c | 1360 | .use_scsi = 1, |
0c257437 | 1361 | .is_default = 1, |
c0e564d5 | 1362 | }; |
e0353fe2 | 1363 | |
f80f9ec9 | 1364 | static QEMUMachine ss10_machine = { |
66de733b BS |
1365 | .name = "SS-10", |
1366 | .desc = "Sun4m platform, SPARCstation 10", | |
1367 | .init = ss10_init, | |
c9b1ae2c | 1368 | .use_scsi = 1, |
1bcee014 | 1369 | .max_cpus = 4, |
e0353fe2 | 1370 | }; |
6a3b9cc9 | 1371 | |
f80f9ec9 | 1372 | static QEMUMachine ss600mp_machine = { |
66de733b BS |
1373 | .name = "SS-600MP", |
1374 | .desc = "Sun4m platform, SPARCserver 600MP", | |
1375 | .init = ss600mp_init, | |
c9b1ae2c | 1376 | .use_scsi = 1, |
1bcee014 | 1377 | .max_cpus = 4, |
6a3b9cc9 | 1378 | }; |
ae40972f | 1379 | |
f80f9ec9 | 1380 | static QEMUMachine ss20_machine = { |
66de733b BS |
1381 | .name = "SS-20", |
1382 | .desc = "Sun4m platform, SPARCstation 20", | |
1383 | .init = ss20_init, | |
c9b1ae2c | 1384 | .use_scsi = 1, |
1bcee014 | 1385 | .max_cpus = 4, |
ae40972f BS |
1386 | }; |
1387 | ||
f80f9ec9 | 1388 | static QEMUMachine voyager_machine = { |
66de733b BS |
1389 | .name = "Voyager", |
1390 | .desc = "Sun4m platform, SPARCstation Voyager", | |
1391 | .init = vger_init, | |
c9b1ae2c | 1392 | .use_scsi = 1, |
a526a31c BS |
1393 | }; |
1394 | ||
f80f9ec9 | 1395 | static QEMUMachine ss_lx_machine = { |
66de733b BS |
1396 | .name = "LX", |
1397 | .desc = "Sun4m platform, SPARCstation LX", | |
1398 | .init = ss_lx_init, | |
c9b1ae2c | 1399 | .use_scsi = 1, |
a526a31c BS |
1400 | }; |
1401 | ||
f80f9ec9 | 1402 | static QEMUMachine ss4_machine = { |
66de733b BS |
1403 | .name = "SS-4", |
1404 | .desc = "Sun4m platform, SPARCstation 4", | |
1405 | .init = ss4_init, | |
c9b1ae2c | 1406 | .use_scsi = 1, |
a526a31c BS |
1407 | }; |
1408 | ||
f80f9ec9 | 1409 | static QEMUMachine scls_machine = { |
66de733b BS |
1410 | .name = "SPARCClassic", |
1411 | .desc = "Sun4m platform, SPARCClassic", | |
1412 | .init = scls_init, | |
c9b1ae2c | 1413 | .use_scsi = 1, |
a526a31c BS |
1414 | }; |
1415 | ||
f80f9ec9 | 1416 | static QEMUMachine sbook_machine = { |
66de733b BS |
1417 | .name = "SPARCbook", |
1418 | .desc = "Sun4m platform, SPARCbook", | |
1419 | .init = sbook_init, | |
c9b1ae2c | 1420 | .use_scsi = 1, |
a526a31c BS |
1421 | }; |
1422 | ||
7d85892b BS |
1423 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1424 | /* SS-1000 */ | |
1425 | { | |
1426 | .iounit_bases = { | |
1427 | 0xfe0200000ULL, | |
1428 | 0xfe1200000ULL, | |
1429 | 0xfe2200000ULL, | |
1430 | 0xfe3200000ULL, | |
1431 | -1, | |
1432 | }, | |
1433 | .tcx_base = 0x820000000ULL, | |
1434 | .slavio_base = 0xf00000000ULL, | |
1435 | .ms_kb_base = 0xf00240000ULL, | |
1436 | .serial_base = 0xf00200000ULL, | |
1437 | .nvram_base = 0xf00280000ULL, | |
1438 | .counter_base = 0xf00300000ULL, | |
1439 | .espdma_base = 0x800081000ULL, | |
1440 | .esp_base = 0x800080000ULL, | |
1441 | .ledma_base = 0x800040000ULL, | |
1442 | .le_base = 0x800060000ULL, | |
1443 | .sbi_base = 0xf02800000ULL, | |
c1d00dc0 | 1444 | .vram_size = 0x00100000, |
7d85892b BS |
1445 | .nvram_size = 0x2000, |
1446 | .esp_irq = 3, | |
1447 | .le_irq = 4, | |
1448 | .clock_irq = 14, | |
1449 | .clock1_irq = 10, | |
1450 | .ms_kb_irq = 12, | |
1451 | .ser_irq = 12, | |
905fdcb5 BS |
1452 | .nvram_machine_id = 0x80, |
1453 | .machine_id = ss1000_id, | |
7d85892b | 1454 | .iounit_version = 0x03000000, |
6ef05b95 | 1455 | .max_mem = 0xf00000000ULL, |
7d85892b BS |
1456 | .default_cpu_model = "TI SuperSparc II", |
1457 | }, | |
1458 | /* SS-2000 */ | |
1459 | { | |
1460 | .iounit_bases = { | |
1461 | 0xfe0200000ULL, | |
1462 | 0xfe1200000ULL, | |
1463 | 0xfe2200000ULL, | |
1464 | 0xfe3200000ULL, | |
1465 | 0xfe4200000ULL, | |
1466 | }, | |
1467 | .tcx_base = 0x820000000ULL, | |
1468 | .slavio_base = 0xf00000000ULL, | |
1469 | .ms_kb_base = 0xf00240000ULL, | |
1470 | .serial_base = 0xf00200000ULL, | |
1471 | .nvram_base = 0xf00280000ULL, | |
1472 | .counter_base = 0xf00300000ULL, | |
1473 | .espdma_base = 0x800081000ULL, | |
1474 | .esp_base = 0x800080000ULL, | |
1475 | .ledma_base = 0x800040000ULL, | |
1476 | .le_base = 0x800060000ULL, | |
1477 | .sbi_base = 0xf02800000ULL, | |
c1d00dc0 | 1478 | .vram_size = 0x00100000, |
7d85892b BS |
1479 | .nvram_size = 0x2000, |
1480 | .esp_irq = 3, | |
1481 | .le_irq = 4, | |
1482 | .clock_irq = 14, | |
1483 | .clock1_irq = 10, | |
1484 | .ms_kb_irq = 12, | |
1485 | .ser_irq = 12, | |
905fdcb5 BS |
1486 | .nvram_machine_id = 0x80, |
1487 | .machine_id = ss2000_id, | |
7d85892b | 1488 | .iounit_version = 0x03000000, |
6ef05b95 | 1489 | .max_mem = 0xf00000000ULL, |
7d85892b BS |
1490 | .default_cpu_model = "TI SuperSparc II", |
1491 | }, | |
1492 | }; | |
1493 | ||
4b48bf05 BS |
1494 | static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq) |
1495 | { | |
1496 | DeviceState *dev; | |
1497 | SysBusDevice *s; | |
1498 | unsigned int i; | |
1499 | ||
1500 | dev = qdev_create(NULL, "sbi"); | |
1501 | qdev_init(dev); | |
1502 | ||
1503 | s = sysbus_from_qdev(dev); | |
1504 | ||
1505 | for (i = 0; i < MAX_CPUS; i++) { | |
1506 | sysbus_connect_irq(s, i, *parent_irq[i]); | |
1507 | } | |
1508 | ||
1509 | sysbus_mmio_map(s, 0, addr); | |
1510 | ||
1511 | return dev; | |
1512 | } | |
1513 | ||
6ef05b95 | 1514 | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
7d85892b | 1515 | const char *boot_device, |
3023f332 | 1516 | const char *kernel_filename, |
7d85892b BS |
1517 | const char *kernel_cmdline, |
1518 | const char *initrd_filename, const char *cpu_model) | |
1519 | { | |
666713c0 | 1520 | CPUState *envs[MAX_CPUS]; |
7d85892b | 1521 | unsigned int i; |
7fc06735 BS |
1522 | void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram; |
1523 | qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS], | |
6f6260c7 | 1524 | espdma_irq, ledma_irq; |
7d85892b | 1525 | qemu_irq *esp_reset, *le_reset; |
5c6602c5 | 1526 | unsigned long kernel_size; |
3cce6243 | 1527 | void *fw_cfg; |
7fc06735 | 1528 | DeviceState *dev; |
7d85892b BS |
1529 | |
1530 | /* init CPUs */ | |
1531 | if (!cpu_model) | |
1532 | cpu_model = hwdef->default_cpu_model; | |
1533 | ||
666713c0 BS |
1534 | for(i = 0; i < smp_cpus; i++) { |
1535 | envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); | |
7d85892b BS |
1536 | } |
1537 | ||
1538 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
1539 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
1540 | ||
7d85892b | 1541 | /* set up devices */ |
a350db85 BS |
1542 | ram_init(0, RAM_size, hwdef->max_mem); |
1543 | ||
f48f6569 BS |
1544 | prom_init(hwdef->slavio_base, bios_name); |
1545 | ||
7fc06735 BS |
1546 | dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
1547 | ||
1548 | for (i = 0; i < 32; i++) { | |
1549 | sbi_irq[i] = qdev_get_gpio_in(dev, i); | |
1550 | } | |
1551 | for (i = 0; i < MAX_CPUS; i++) { | |
1552 | sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i); | |
1553 | } | |
7d85892b BS |
1554 | |
1555 | for (i = 0; i < MAX_IOUNITS; i++) | |
1556 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) | |
ff403da6 BS |
1557 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1558 | hwdef->iounit_version, | |
1559 | sbi_irq[hwdef->me_irq]); | |
7d85892b BS |
1560 | |
1561 | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], | |
1562 | iounits[0], &espdma_irq, &esp_reset); | |
1563 | ||
1564 | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], | |
1565 | iounits[0], &ledma_irq, &le_reset); | |
1566 | ||
1567 | if (graphic_depth != 8 && graphic_depth != 24) { | |
1568 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
1569 | exit (1); | |
1570 | } | |
dc828ca1 PB |
1571 | tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height, |
1572 | graphic_depth); | |
7d85892b | 1573 | |
6f6260c7 | 1574 | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset); |
7d85892b BS |
1575 | |
1576 | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, | |
1577 | hwdef->nvram_size, 8); | |
1578 | ||
1579 | slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], | |
1580 | sbi_cpu_irq, smp_cpus); | |
1581 | ||
1582 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], | |
993fbfdb | 1583 | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); |
7d85892b BS |
1584 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
1585 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
aeeb69c7 AJ |
1586 | escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq], |
1587 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); | |
7d85892b BS |
1588 | |
1589 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
1590 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
1591 | exit(1); | |
1592 | } | |
1593 | ||
cfb9de9c PB |
1594 | esp_init(hwdef->esp_base, 2, |
1595 | espdma_memory_read, espdma_memory_write, | |
6f6260c7 | 1596 | espdma, espdma_irq, esp_reset); |
7d85892b | 1597 | |
293f78bc BS |
1598 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1599 | RAM_size); | |
7d85892b BS |
1600 | |
1601 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, | |
1602 | boot_device, RAM_size, kernel_size, graphic_width, | |
905fdcb5 BS |
1603 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1604 | "Sun4d"); | |
3cce6243 BS |
1605 | |
1606 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); | |
1607 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 BS |
1608 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1609 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
513f789f BS |
1610 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1611 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); | |
1612 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1613 | if (kernel_cmdline) { | |
1614 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
1615 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
1616 | } else { | |
1617 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
1618 | } | |
1619 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
1620 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used | |
1621 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
1622 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
7d85892b BS |
1623 | } |
1624 | ||
1625 | /* SPARCserver 1000 hardware initialisation */ | |
fbe1b595 | 1626 | static void ss1000_init(ram_addr_t RAM_size, |
3023f332 | 1627 | const char *boot_device, |
7d85892b BS |
1628 | const char *kernel_filename, const char *kernel_cmdline, |
1629 | const char *initrd_filename, const char *cpu_model) | |
1630 | { | |
3023f332 | 1631 | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename, |
7d85892b BS |
1632 | kernel_cmdline, initrd_filename, cpu_model); |
1633 | } | |
1634 | ||
1635 | /* SPARCcenter 2000 hardware initialisation */ | |
fbe1b595 | 1636 | static void ss2000_init(ram_addr_t RAM_size, |
3023f332 | 1637 | const char *boot_device, |
7d85892b BS |
1638 | const char *kernel_filename, const char *kernel_cmdline, |
1639 | const char *initrd_filename, const char *cpu_model) | |
1640 | { | |
3023f332 | 1641 | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename, |
7d85892b BS |
1642 | kernel_cmdline, initrd_filename, cpu_model); |
1643 | } | |
1644 | ||
f80f9ec9 | 1645 | static QEMUMachine ss1000_machine = { |
66de733b BS |
1646 | .name = "SS-1000", |
1647 | .desc = "Sun4d platform, SPARCserver 1000", | |
1648 | .init = ss1000_init, | |
c9b1ae2c | 1649 | .use_scsi = 1, |
1bcee014 | 1650 | .max_cpus = 8, |
7d85892b BS |
1651 | }; |
1652 | ||
f80f9ec9 | 1653 | static QEMUMachine ss2000_machine = { |
66de733b BS |
1654 | .name = "SS-2000", |
1655 | .desc = "Sun4d platform, SPARCcenter 2000", | |
1656 | .init = ss2000_init, | |
c9b1ae2c | 1657 | .use_scsi = 1, |
1bcee014 | 1658 | .max_cpus = 20, |
7d85892b | 1659 | }; |
8137cde8 BS |
1660 | |
1661 | static const struct sun4c_hwdef sun4c_hwdefs[] = { | |
1662 | /* SS-2 */ | |
1663 | { | |
1664 | .iommu_base = 0xf8000000, | |
1665 | .tcx_base = 0xfe000000, | |
8137cde8 BS |
1666 | .slavio_base = 0xf6000000, |
1667 | .intctl_base = 0xf5000000, | |
1668 | .counter_base = 0xf3000000, | |
1669 | .ms_kb_base = 0xf0000000, | |
1670 | .serial_base = 0xf1000000, | |
1671 | .nvram_base = 0xf2000000, | |
1672 | .fd_base = 0xf7200000, | |
1673 | .dma_base = 0xf8400000, | |
1674 | .esp_base = 0xf8800000, | |
1675 | .le_base = 0xf8c00000, | |
8137cde8 | 1676 | .aux1_base = 0xf7400003, |
8137cde8 BS |
1677 | .vram_size = 0x00100000, |
1678 | .nvram_size = 0x800, | |
1679 | .esp_irq = 2, | |
1680 | .le_irq = 3, | |
1681 | .clock_irq = 5, | |
1682 | .clock1_irq = 7, | |
1683 | .ms_kb_irq = 1, | |
1684 | .ser_irq = 1, | |
1685 | .fd_irq = 1, | |
1686 | .me_irq = 1, | |
8137cde8 BS |
1687 | .nvram_machine_id = 0x55, |
1688 | .machine_id = ss2_id, | |
1689 | .max_mem = 0x10000000, | |
1690 | .default_cpu_model = "Cypress CY7C601", | |
1691 | }, | |
1692 | }; | |
1693 | ||
4b48bf05 BS |
1694 | static DeviceState *sun4c_intctl_init(target_phys_addr_t addr, |
1695 | qemu_irq *parent_irq) | |
1696 | { | |
1697 | DeviceState *dev; | |
1698 | SysBusDevice *s; | |
1699 | unsigned int i; | |
1700 | ||
1701 | dev = qdev_create(NULL, "sun4c_intctl"); | |
1702 | qdev_init(dev); | |
1703 | ||
1704 | s = sysbus_from_qdev(dev); | |
1705 | ||
1706 | for (i = 0; i < MAX_PILS; i++) { | |
1707 | sysbus_connect_irq(s, i, parent_irq[i]); | |
1708 | } | |
1709 | sysbus_mmio_map(s, 0, addr); | |
1710 | ||
1711 | return dev; | |
1712 | } | |
1713 | ||
8137cde8 BS |
1714 | static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1715 | const char *boot_device, | |
3023f332 | 1716 | const char *kernel_filename, |
8137cde8 BS |
1717 | const char *kernel_cmdline, |
1718 | const char *initrd_filename, const char *cpu_model) | |
1719 | { | |
1720 | CPUState *env; | |
cfb9de9c | 1721 | void *iommu, *espdma, *ledma, *nvram; |
e32cba29 | 1722 | qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq; |
8137cde8 | 1723 | qemu_irq *esp_reset, *le_reset; |
2582cfa0 | 1724 | qemu_irq fdc_tc; |
5c6602c5 | 1725 | unsigned long kernel_size; |
8137cde8 | 1726 | BlockDriverState *fd[MAX_FD]; |
8137cde8 | 1727 | void *fw_cfg; |
e32cba29 BS |
1728 | DeviceState *dev; |
1729 | unsigned int i; | |
751c6a17 | 1730 | DriveInfo *dinfo; |
8137cde8 BS |
1731 | |
1732 | /* init CPU */ | |
1733 | if (!cpu_model) | |
1734 | cpu_model = hwdef->default_cpu_model; | |
1735 | ||
666713c0 | 1736 | env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs); |
8137cde8 | 1737 | |
8137cde8 | 1738 | /* set up devices */ |
a350db85 BS |
1739 | ram_init(0, RAM_size, hwdef->max_mem); |
1740 | ||
f48f6569 BS |
1741 | prom_init(hwdef->slavio_base, bios_name); |
1742 | ||
e32cba29 BS |
1743 | dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); |
1744 | ||
1745 | for (i = 0; i < 8; i++) { | |
1746 | slavio_irq[i] = qdev_get_gpio_in(dev, i); | |
1747 | } | |
8137cde8 BS |
1748 | |
1749 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, | |
1750 | slavio_irq[hwdef->me_irq]); | |
1751 | ||
1752 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], | |
1753 | iommu, &espdma_irq, &esp_reset); | |
1754 | ||
1755 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, | |
1756 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, | |
1757 | &le_reset); | |
1758 | ||
1759 | if (graphic_depth != 8 && graphic_depth != 24) { | |
1760 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
1761 | exit (1); | |
1762 | } | |
dc828ca1 PB |
1763 | tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height, |
1764 | graphic_depth); | |
8137cde8 | 1765 | |
6f6260c7 | 1766 | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset); |
8137cde8 BS |
1767 | |
1768 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, | |
1769 | hwdef->nvram_size, 2); | |
1770 | ||
1771 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], | |
993fbfdb | 1772 | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); |
8137cde8 BS |
1773 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
1774 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
aeeb69c7 AJ |
1775 | escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
1776 | slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1], | |
1777 | ESCC_CLOCK, 1); | |
8137cde8 | 1778 | |
2582cfa0 BS |
1779 | slavio_misc = slavio_misc_init(0, hwdef->aux1_base, 0, |
1780 | slavio_irq[hwdef->me_irq], fdc_tc); | |
8137cde8 BS |
1781 | |
1782 | if (hwdef->fd_base != (target_phys_addr_t)-1) { | |
1783 | /* there is zero or one floppy drive */ | |
ce802585 | 1784 | memset(fd, 0, sizeof(fd)); |
751c6a17 GH |
1785 | dinfo = drive_get(IF_FLOPPY, 0, 0); |
1786 | if (dinfo) | |
1787 | fd[0] = dinfo->bdrv; | |
8137cde8 BS |
1788 | |
1789 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, | |
2582cfa0 | 1790 | &fdc_tc); |
8137cde8 BS |
1791 | } |
1792 | ||
1793 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
1794 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
1795 | exit(1); | |
1796 | } | |
1797 | ||
cfb9de9c PB |
1798 | esp_init(hwdef->esp_base, 2, |
1799 | espdma_memory_read, espdma_memory_write, | |
6f6260c7 | 1800 | espdma, espdma_irq, esp_reset); |
8137cde8 BS |
1801 | |
1802 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, | |
1803 | RAM_size); | |
1804 | ||
1805 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, | |
1806 | boot_device, RAM_size, kernel_size, graphic_width, | |
1807 | graphic_height, graphic_depth, hwdef->nvram_machine_id, | |
1808 | "Sun4c"); | |
1809 | ||
1810 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); | |
1811 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
1812 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
1813 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
513f789f BS |
1814 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1815 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); | |
1816 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1817 | if (kernel_cmdline) { | |
1818 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
1819 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
1820 | } else { | |
1821 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
1822 | } | |
1823 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
1824 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used | |
1825 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
1826 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
8137cde8 BS |
1827 | } |
1828 | ||
1829 | /* SPARCstation 2 hardware initialisation */ | |
fbe1b595 | 1830 | static void ss2_init(ram_addr_t RAM_size, |
3023f332 | 1831 | const char *boot_device, |
8137cde8 BS |
1832 | const char *kernel_filename, const char *kernel_cmdline, |
1833 | const char *initrd_filename, const char *cpu_model) | |
1834 | { | |
3023f332 | 1835 | sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename, |
8137cde8 BS |
1836 | kernel_cmdline, initrd_filename, cpu_model); |
1837 | } | |
1838 | ||
f80f9ec9 | 1839 | static QEMUMachine ss2_machine = { |
8137cde8 BS |
1840 | .name = "SS-2", |
1841 | .desc = "Sun4c platform, SPARCstation 2", | |
1842 | .init = ss2_init, | |
8137cde8 | 1843 | .use_scsi = 1, |
8137cde8 | 1844 | }; |
f80f9ec9 AL |
1845 | |
1846 | static void ss2_machine_init(void) | |
1847 | { | |
1848 | qemu_register_machine(&ss5_machine); | |
1849 | qemu_register_machine(&ss10_machine); | |
1850 | qemu_register_machine(&ss600mp_machine); | |
1851 | qemu_register_machine(&ss20_machine); | |
1852 | qemu_register_machine(&voyager_machine); | |
1853 | qemu_register_machine(&ss_lx_machine); | |
1854 | qemu_register_machine(&ss4_machine); | |
1855 | qemu_register_machine(&scls_machine); | |
1856 | qemu_register_machine(&sbook_machine); | |
1857 | qemu_register_machine(&ss1000_machine); | |
1858 | qemu_register_machine(&ss2000_machine); | |
1859 | qemu_register_machine(&ss2_machine); | |
1860 | } | |
1861 | ||
1862 | machine_init(ss2_machine_init); |