]>
Commit | Line | Data |
---|---|---|
420557e8 | 1 | /* |
ee76f82e | 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
5fafdf24 | 3 | * |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "qemu-timer.h" | |
26 | #include "sun4m.h" | |
27 | #include "nvram.h" | |
28 | #include "sparc32_dma.h" | |
29 | #include "fdc.h" | |
30 | #include "sysemu.h" | |
31 | #include "net.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
8b17de88 | 34 | #include "scsi.h" |
22548760 BS |
35 | #include "pc.h" |
36 | #include "isa.h" | |
3cce6243 | 37 | #include "fw_cfg.h" |
b4ed08e0 | 38 | #include "escc.h" |
d2c63fc1 | 39 | |
b3a23197 | 40 | //#define DEBUG_IRQ |
420557e8 | 41 | |
36cd9210 BS |
42 | /* |
43 | * Sun4m architecture was used in the following machines: | |
44 | * | |
45 | * SPARCserver 6xxMP/xx | |
77f193da BS |
46 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), |
47 | * SPARCclassic X (4/10) | |
36cd9210 BS |
48 | * SPARCstation LX/ZX (4/30) |
49 | * SPARCstation Voyager | |
50 | * SPARCstation 10/xx, SPARCserver 10/xx | |
51 | * SPARCstation 5, SPARCserver 5 | |
52 | * SPARCstation 20/xx, SPARCserver 20 | |
53 | * SPARCstation 4 | |
54 | * | |
7d85892b BS |
55 | * Sun4d architecture was used in the following machines: |
56 | * | |
57 | * SPARCcenter 2000 | |
58 | * SPARCserver 1000 | |
59 | * | |
ee76f82e BS |
60 | * Sun4c architecture was used in the following machines: |
61 | * SPARCstation 1/1+, SPARCserver 1/1+ | |
62 | * SPARCstation SLC | |
63 | * SPARCstation IPC | |
64 | * SPARCstation ELC | |
65 | * SPARCstation IPX | |
66 | * | |
36cd9210 BS |
67 | * See for example: http://www.sunhelp.org/faq/sunref1.html |
68 | */ | |
69 | ||
b3a23197 BS |
70 | #ifdef DEBUG_IRQ |
71 | #define DPRINTF(fmt, args...) \ | |
72 | do { printf("CPUIRQ: " fmt , ##args); } while (0) | |
73 | #else | |
74 | #define DPRINTF(fmt, args...) | |
75 | #endif | |
76 | ||
420557e8 | 77 | #define KERNEL_LOAD_ADDR 0x00004000 |
b6f479d3 | 78 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 79 | #define INITRD_LOAD_ADDR 0x00800000 |
a7227727 | 80 | #define PROM_SIZE_MAX (1024 * 1024) |
40ce0a9a | 81 | #define PROM_VADDR 0xffd00000 |
f930d07e | 82 | #define PROM_FILENAME "openbios-sparc32" |
3cce6243 | 83 | #define CFG_ADDR 0xd00000510ULL |
fbfcf955 | 84 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
b8174937 | 85 | |
ac2e9d66 BS |
86 | // Control plane, 8-bit and 24-bit planes |
87 | #define TCX_SIZE (9 * 1024 * 1024) | |
88 | ||
ba3c64fb | 89 | #define MAX_CPUS 16 |
b3a23197 | 90 | #define MAX_PILS 16 |
420557e8 | 91 | |
b4ed08e0 BS |
92 | #define ESCC_CLOCK 4915200 |
93 | ||
8137cde8 | 94 | struct sun4m_hwdef { |
5dcb6b91 BS |
95 | target_phys_addr_t iommu_base, slavio_base; |
96 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; | |
97 | target_phys_addr_t serial_base, fd_base; | |
4c2485de | 98 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
0019ad53 | 99 | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
7eb0c8e8 BS |
100 | target_phys_addr_t ecc_base; |
101 | uint32_t ecc_version; | |
36cd9210 | 102 | long vram_size, nvram_size; |
6341fdcb | 103 | // IRQ numbers are not PIL ones, but master interrupt controller |
e3a79bca | 104 | // register bit numbers |
1572a18c | 105 | int esp_irq, le_irq, clock_irq, clock1_irq; |
e42c20b4 | 106 | int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq; |
905fdcb5 BS |
107 | uint8_t nvram_machine_id; |
108 | uint16_t machine_id; | |
7fbfb139 | 109 | uint32_t iommu_version; |
e0353fe2 | 110 | uint32_t intbit_to_level[32]; |
3ebf5aaf BS |
111 | uint64_t max_mem; |
112 | const char * const default_cpu_model; | |
36cd9210 BS |
113 | }; |
114 | ||
7d85892b BS |
115 | #define MAX_IOUNITS 5 |
116 | ||
117 | struct sun4d_hwdef { | |
118 | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; | |
119 | target_phys_addr_t counter_base, nvram_base, ms_kb_base; | |
120 | target_phys_addr_t serial_base; | |
121 | target_phys_addr_t espdma_base, esp_base; | |
122 | target_phys_addr_t ledma_base, le_base; | |
123 | target_phys_addr_t tcx_base; | |
124 | target_phys_addr_t sbi_base; | |
125 | unsigned long vram_size, nvram_size; | |
126 | // IRQ numbers are not PIL ones, but SBI register bit numbers | |
127 | int esp_irq, le_irq, clock_irq, clock1_irq; | |
128 | int ser_irq, ms_kb_irq, me_irq; | |
905fdcb5 BS |
129 | uint8_t nvram_machine_id; |
130 | uint16_t machine_id; | |
7d85892b BS |
131 | uint32_t iounit_version; |
132 | uint64_t max_mem; | |
133 | const char * const default_cpu_model; | |
134 | }; | |
135 | ||
8137cde8 BS |
136 | struct sun4c_hwdef { |
137 | target_phys_addr_t iommu_base, slavio_base; | |
138 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; | |
139 | target_phys_addr_t serial_base, fd_base; | |
140 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; | |
1572a18c | 141 | target_phys_addr_t tcx_base, aux1_base; |
8137cde8 BS |
142 | long vram_size, nvram_size; |
143 | // IRQ numbers are not PIL ones, but master interrupt controller | |
144 | // register bit numbers | |
1572a18c BS |
145 | int esp_irq, le_irq, clock_irq, clock1_irq; |
146 | int ser_irq, ms_kb_irq, fd_irq, me_irq; | |
8137cde8 BS |
147 | uint8_t nvram_machine_id; |
148 | uint16_t machine_id; | |
149 | uint32_t iommu_version; | |
150 | uint32_t intbit_to_level[32]; | |
151 | uint64_t max_mem; | |
152 | const char * const default_cpu_model; | |
153 | }; | |
154 | ||
6f7e9aec FB |
155 | int DMA_get_channel_mode (int nchan) |
156 | { | |
157 | return 0; | |
158 | } | |
159 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
160 | { | |
161 | return 0; | |
162 | } | |
163 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
164 | { | |
165 | return 0; | |
166 | } | |
167 | void DMA_hold_DREQ (int nchan) {} | |
168 | void DMA_release_DREQ (int nchan) {} | |
169 | void DMA_schedule(int nchan) {} | |
6f7e9aec FB |
170 | void DMA_init (int high_page_enable) {} |
171 | void DMA_register_channel (int nchan, | |
172 | DMA_transfer_handler transfer_handler, | |
173 | void *opaque) | |
174 | { | |
175 | } | |
176 | ||
513f789f | 177 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
81864572 | 178 | { |
513f789f | 179 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
180 | return 0; |
181 | } | |
182 | ||
819385c5 | 183 | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
6ef05b95 | 184 | const char *boot_devices, ram_addr_t RAM_size, |
f930d07e BS |
185 | uint32_t kernel_size, |
186 | int width, int height, int depth, | |
905fdcb5 | 187 | int nvram_machine_id, const char *arch) |
e80cfcfc | 188 | { |
d2c63fc1 | 189 | unsigned int i; |
66508601 | 190 | uint32_t start, end; |
d2c63fc1 | 191 | uint8_t image[0x1ff0]; |
d2c63fc1 BS |
192 | struct OpenBIOS_nvpart_v1 *part_header; |
193 | ||
194 | memset(image, '\0', sizeof(image)); | |
e80cfcfc | 195 | |
513f789f | 196 | start = 0; |
b6f479d3 | 197 | |
66508601 BS |
198 | // OpenBIOS nvram variables |
199 | // Variable partition | |
d2c63fc1 BS |
200 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
201 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 202 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 203 | |
d2c63fc1 | 204 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 205 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
206 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
207 | ||
208 | // End marker | |
209 | image[end++] = '\0'; | |
66508601 | 210 | |
66508601 | 211 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 212 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
213 | |
214 | // free partition | |
215 | start = end; | |
d2c63fc1 BS |
216 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
217 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 218 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
219 | |
220 | end = 0x1fd0; | |
d2c63fc1 BS |
221 | OpenBIOS_finish_partition(part_header, end - start); |
222 | ||
905fdcb5 BS |
223 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
224 | nvram_machine_id); | |
d2c63fc1 BS |
225 | |
226 | for (i = 0; i < sizeof(image); i++) | |
227 | m48t59_write(nvram, i, image[i]); | |
e80cfcfc FB |
228 | } |
229 | ||
230 | static void *slavio_intctl; | |
231 | ||
376253ec | 232 | void pic_info(Monitor *mon) |
e80cfcfc | 233 | { |
7d85892b | 234 | if (slavio_intctl) |
376253ec | 235 | slavio_pic_info(mon, slavio_intctl); |
e80cfcfc FB |
236 | } |
237 | ||
376253ec | 238 | void irq_info(Monitor *mon) |
e80cfcfc | 239 | { |
7d85892b | 240 | if (slavio_intctl) |
376253ec | 241 | slavio_irq_info(mon, slavio_intctl); |
e80cfcfc FB |
242 | } |
243 | ||
327ac2e7 BS |
244 | void cpu_check_irqs(CPUState *env) |
245 | { | |
246 | if (env->pil_in && (env->interrupt_index == 0 || | |
247 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
248 | unsigned int i; | |
249 | ||
250 | for (i = 15; i > 0; i--) { | |
251 | if (env->pil_in & (1 << i)) { | |
252 | int old_interrupt = env->interrupt_index; | |
253 | ||
254 | env->interrupt_index = TT_EXTINT | i; | |
f32d7ec5 BS |
255 | if (old_interrupt != env->interrupt_index) { |
256 | DPRINTF("Set CPU IRQ %d\n", i); | |
327ac2e7 | 257 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
f32d7ec5 | 258 | } |
327ac2e7 BS |
259 | break; |
260 | } | |
261 | } | |
262 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { | |
f32d7ec5 | 263 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
327ac2e7 BS |
264 | env->interrupt_index = 0; |
265 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
266 | } | |
267 | } | |
268 | ||
b3a23197 BS |
269 | static void cpu_set_irq(void *opaque, int irq, int level) |
270 | { | |
271 | CPUState *env = opaque; | |
272 | ||
273 | if (level) { | |
274 | DPRINTF("Raise CPU IRQ %d\n", irq); | |
b3a23197 | 275 | env->halted = 0; |
327ac2e7 BS |
276 | env->pil_in |= 1 << irq; |
277 | cpu_check_irqs(env); | |
b3a23197 BS |
278 | } else { |
279 | DPRINTF("Lower CPU IRQ %d\n", irq); | |
327ac2e7 BS |
280 | env->pil_in &= ~(1 << irq); |
281 | cpu_check_irqs(env); | |
b3a23197 BS |
282 | } |
283 | } | |
284 | ||
285 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) | |
286 | { | |
287 | } | |
288 | ||
3475187d FB |
289 | static void *slavio_misc; |
290 | ||
291 | void qemu_system_powerdown(void) | |
292 | { | |
293 | slavio_set_power_fail(slavio_misc, 1); | |
294 | } | |
295 | ||
c68ea704 FB |
296 | static void main_cpu_reset(void *opaque) |
297 | { | |
298 | CPUState *env = opaque; | |
3d29fbef BS |
299 | |
300 | cpu_reset(env); | |
301 | env->halted = 0; | |
302 | } | |
303 | ||
304 | static void secondary_cpu_reset(void *opaque) | |
305 | { | |
306 | CPUState *env = opaque; | |
307 | ||
c68ea704 | 308 | cpu_reset(env); |
3d29fbef | 309 | env->halted = 1; |
c68ea704 FB |
310 | } |
311 | ||
6d0c293d BS |
312 | static void cpu_halt_signal(void *opaque, int irq, int level) |
313 | { | |
314 | if (level && cpu_single_env) | |
315 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); | |
316 | } | |
317 | ||
3ebf5aaf | 318 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
293f78bc BS |
319 | const char *initrd_filename, |
320 | ram_addr_t RAM_size) | |
3ebf5aaf BS |
321 | { |
322 | int linux_boot; | |
323 | unsigned int i; | |
324 | long initrd_size, kernel_size; | |
325 | ||
326 | linux_boot = (kernel_filename != NULL); | |
327 | ||
328 | kernel_size = 0; | |
329 | if (linux_boot) { | |
330 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, | |
331 | NULL); | |
332 | if (kernel_size < 0) | |
293f78bc BS |
333 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
334 | RAM_size - KERNEL_LOAD_ADDR); | |
3ebf5aaf | 335 | if (kernel_size < 0) |
293f78bc BS |
336 | kernel_size = load_image_targphys(kernel_filename, |
337 | KERNEL_LOAD_ADDR, | |
338 | RAM_size - KERNEL_LOAD_ADDR); | |
3ebf5aaf BS |
339 | if (kernel_size < 0) { |
340 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
341 | kernel_filename); | |
342 | exit(1); | |
343 | } | |
344 | ||
345 | /* load initrd */ | |
346 | initrd_size = 0; | |
347 | if (initrd_filename) { | |
293f78bc BS |
348 | initrd_size = load_image_targphys(initrd_filename, |
349 | INITRD_LOAD_ADDR, | |
350 | RAM_size - INITRD_LOAD_ADDR); | |
3ebf5aaf BS |
351 | if (initrd_size < 0) { |
352 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
353 | initrd_filename); | |
354 | exit(1); | |
355 | } | |
356 | } | |
357 | if (initrd_size > 0) { | |
358 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
293f78bc BS |
359 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
360 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
361 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
3ebf5aaf BS |
362 | break; |
363 | } | |
364 | } | |
365 | } | |
366 | } | |
367 | return kernel_size; | |
368 | } | |
369 | ||
8137cde8 | 370 | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
3ebf5aaf | 371 | const char *boot_device, |
3023f332 | 372 | const char *kernel_filename, |
3ebf5aaf BS |
373 | const char *kernel_cmdline, |
374 | const char *initrd_filename, const char *cpu_model) | |
36cd9210 | 375 | |
420557e8 | 376 | { |
ba3c64fb | 377 | CPUState *env, *envs[MAX_CPUS]; |
713c45fa | 378 | unsigned int i; |
b3ceef24 | 379 | void *iommu, *espdma, *ledma, *main_esp, *nvram; |
b3a23197 | 380 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
d7edfd27 | 381 | *espdma_irq, *ledma_irq; |
2d069bab | 382 | qemu_irq *esp_reset, *le_reset; |
2be17ebd | 383 | qemu_irq *fdc_tc; |
6d0c293d | 384 | qemu_irq *cpu_halt; |
5c6602c5 BS |
385 | ram_addr_t ram_offset, prom_offset, tcx_offset, idreg_offset; |
386 | unsigned long kernel_size; | |
3ebf5aaf BS |
387 | int ret; |
388 | char buf[1024]; | |
e4bcb14c | 389 | BlockDriverState *fd[MAX_FD]; |
22548760 | 390 | int drive_index; |
3cce6243 | 391 | void *fw_cfg; |
420557e8 | 392 | |
ba3c64fb | 393 | /* init CPUs */ |
3ebf5aaf BS |
394 | if (!cpu_model) |
395 | cpu_model = hwdef->default_cpu_model; | |
b3a23197 | 396 | |
ba3c64fb | 397 | for(i = 0; i < smp_cpus; i++) { |
aaed909a FB |
398 | env = cpu_init(cpu_model); |
399 | if (!env) { | |
8e82c6a8 | 400 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); |
aaed909a FB |
401 | exit(1); |
402 | } | |
403 | cpu_sparc_set_id(env, i); | |
ba3c64fb | 404 | envs[i] = env; |
3d29fbef BS |
405 | if (i == 0) { |
406 | qemu_register_reset(main_cpu_reset, env); | |
407 | } else { | |
408 | qemu_register_reset(secondary_cpu_reset, env); | |
ba3c64fb | 409 | env->halted = 1; |
3d29fbef | 410 | } |
b3a23197 | 411 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
3ebf5aaf | 412 | env->prom_addr = hwdef->slavio_base; |
ba3c64fb | 413 | } |
b3a23197 BS |
414 | |
415 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
416 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
417 | ||
3ebf5aaf | 418 | |
420557e8 | 419 | /* allocate RAM */ |
3ebf5aaf | 420 | if ((uint64_t)RAM_size > hwdef->max_mem) { |
77f193da BS |
421 | fprintf(stderr, |
422 | "qemu: Too much memory for this machine: %d, maximum %d\n", | |
6ef05b95 | 423 | (unsigned int)(RAM_size / (1024 * 1024)), |
3ebf5aaf BS |
424 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
425 | exit(1); | |
426 | } | |
5c6602c5 BS |
427 | ram_offset = qemu_ram_alloc(RAM_size); |
428 | cpu_register_physical_memory(0, RAM_size, ram_offset); | |
420557e8 | 429 | |
3ebf5aaf | 430 | /* load boot prom */ |
5c6602c5 | 431 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
3ebf5aaf BS |
432 | cpu_register_physical_memory(hwdef->slavio_base, |
433 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & | |
434 | TARGET_PAGE_MASK, | |
435 | prom_offset | IO_MEM_ROM); | |
436 | ||
437 | if (bios_name == NULL) | |
438 | bios_name = PROM_FILENAME; | |
439 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
440 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); | |
441 | if (ret < 0 || ret > PROM_SIZE_MAX) | |
e01f4a1c | 442 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
3ebf5aaf BS |
443 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
444 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
445 | buf); | |
446 | exit(1); | |
447 | } | |
448 | ||
449 | /* set up devices */ | |
36cd9210 | 450 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
5dcb6b91 | 451 | hwdef->intctl_base + 0x10000ULL, |
d537cf6c | 452 | &hwdef->intbit_to_level[0], |
d7edfd27 | 453 | &slavio_irq, &slavio_cpu_irq, |
b3a23197 | 454 | cpu_irqs, |
d7edfd27 | 455 | hwdef->clock_irq); |
b3a23197 | 456 | |
fe096129 | 457 | if (hwdef->idreg_base) { |
293f78bc | 458 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
4c2485de | 459 | |
5c6602c5 | 460 | idreg_offset = qemu_ram_alloc(sizeof(idreg_data)); |
293f78bc | 461 | cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data), |
5c6602c5 | 462 | idreg_offset | IO_MEM_ROM); |
293f78bc BS |
463 | cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data, |
464 | sizeof(idreg_data)); | |
4c2485de BS |
465 | } |
466 | ||
ff403da6 BS |
467 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
468 | slavio_irq[hwdef->me_irq]); | |
469 | ||
5aca8c3b | 470 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
2d069bab BS |
471 | iommu, &espdma_irq, &esp_reset); |
472 | ||
5aca8c3b | 473 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, |
2d069bab BS |
474 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
475 | &le_reset); | |
ba3c64fb | 476 | |
eee0b836 BS |
477 | if (graphic_depth != 8 && graphic_depth != 24) { |
478 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
479 | exit (1); | |
480 | } | |
5c6602c5 | 481 | tcx_offset = qemu_ram_alloc(hwdef->vram_size); |
3023f332 | 482 | tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset, |
eee0b836 | 483 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
dbe06e18 | 484 | |
0ae18cee | 485 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); |
dbe06e18 | 486 | |
d537cf6c PB |
487 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
488 | hwdef->nvram_size, 8); | |
81732d19 BS |
489 | |
490 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], | |
19f8e5dd | 491 | slavio_cpu_irq, smp_cpus); |
81732d19 | 492 | |
577390ff | 493 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
b4ed08e0 | 494 | nographic, ESCC_CLOCK, 1); |
b81b3b10 FB |
495 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
496 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
aeeb69c7 AJ |
497 | escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq], |
498 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); | |
741402f9 | 499 | |
6d0c293d | 500 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
2be17ebd BS |
501 | slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base, |
502 | hwdef->aux1_base, hwdef->aux2_base, | |
6d0c293d | 503 | slavio_irq[hwdef->me_irq], cpu_halt[0], |
2be17ebd BS |
504 | &fdc_tc); |
505 | ||
fe096129 | 506 | if (hwdef->fd_base) { |
e4bcb14c | 507 | /* there is zero or one floppy drive */ |
309e60bd | 508 | memset(fd, 0, sizeof(fd)); |
22548760 BS |
509 | drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
510 | if (drive_index != -1) | |
511 | fd[0] = drives_table[drive_index].bdrv; | |
2d069bab | 512 | |
2be17ebd BS |
513 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
514 | fdc_tc); | |
e4bcb14c TS |
515 | } |
516 | ||
517 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
518 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
519 | exit(1); | |
520 | } | |
521 | ||
5d20fa6b | 522 | main_esp = esp_init(hwdef->esp_base, 2, |
8b17de88 BS |
523 | espdma_memory_read, espdma_memory_write, |
524 | espdma, *espdma_irq, esp_reset); | |
f1587550 | 525 | |
e4bcb14c | 526 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
22548760 BS |
527 | drive_index = drive_get_index(IF_SCSI, 0, i); |
528 | if (drive_index == -1) | |
e4bcb14c | 529 | continue; |
22548760 | 530 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
f1587550 TS |
531 | } |
532 | ||
fe096129 | 533 | if (hwdef->cs_base) |
803b3c7b | 534 | cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
b3ceef24 | 535 | |
293f78bc BS |
536 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
537 | RAM_size); | |
36cd9210 | 538 | |
36cd9210 | 539 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, |
b3ceef24 | 540 | boot_device, RAM_size, kernel_size, graphic_width, |
905fdcb5 BS |
541 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
542 | "Sun4m"); | |
7eb0c8e8 | 543 | |
fe096129 | 544 | if (hwdef->ecc_base) |
e42c20b4 BS |
545 | ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq], |
546 | hwdef->ecc_version); | |
3cce6243 BS |
547 | |
548 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); | |
549 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 BS |
550 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
551 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
fbfcf955 | 552 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
513f789f BS |
553 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
554 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
555 | if (kernel_cmdline) { | |
556 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
557 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
558 | } else { | |
559 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
560 | } | |
561 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
562 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used | |
563 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
564 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
36cd9210 BS |
565 | } |
566 | ||
905fdcb5 BS |
567 | enum { |
568 | ss2_id = 0, | |
569 | ss5_id = 32, | |
570 | vger_id, | |
571 | lx_id, | |
572 | ss4_id, | |
573 | scls_id, | |
574 | sbook_id, | |
575 | ss10_id = 64, | |
576 | ss20_id, | |
577 | ss600mp_id, | |
578 | ss1000_id = 96, | |
579 | ss2000_id, | |
580 | }; | |
581 | ||
8137cde8 | 582 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
36cd9210 BS |
583 | /* SS-5 */ |
584 | { | |
585 | .iommu_base = 0x10000000, | |
586 | .tcx_base = 0x50000000, | |
587 | .cs_base = 0x6c000000, | |
384ccb5d | 588 | .slavio_base = 0x70000000, |
36cd9210 BS |
589 | .ms_kb_base = 0x71000000, |
590 | .serial_base = 0x71100000, | |
591 | .nvram_base = 0x71200000, | |
592 | .fd_base = 0x71400000, | |
593 | .counter_base = 0x71d00000, | |
594 | .intctl_base = 0x71e00000, | |
4c2485de | 595 | .idreg_base = 0x78000000, |
36cd9210 BS |
596 | .dma_base = 0x78400000, |
597 | .esp_base = 0x78800000, | |
598 | .le_base = 0x78c00000, | |
127fc407 | 599 | .apc_base = 0x6a000000, |
0019ad53 BS |
600 | .aux1_base = 0x71900000, |
601 | .aux2_base = 0x71910000, | |
36cd9210 BS |
602 | .vram_size = 0x00100000, |
603 | .nvram_size = 0x2000, | |
604 | .esp_irq = 18, | |
605 | .le_irq = 16, | |
e3a79bca | 606 | .clock_irq = 7, |
36cd9210 BS |
607 | .clock1_irq = 19, |
608 | .ms_kb_irq = 14, | |
609 | .ser_irq = 15, | |
610 | .fd_irq = 22, | |
611 | .me_irq = 30, | |
612 | .cs_irq = 5, | |
905fdcb5 BS |
613 | .nvram_machine_id = 0x80, |
614 | .machine_id = ss5_id, | |
cf3102ac | 615 | .iommu_version = 0x05000000, |
e0353fe2 | 616 | .intbit_to_level = { |
f930d07e BS |
617 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
618 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
e0353fe2 | 619 | }, |
3ebf5aaf BS |
620 | .max_mem = 0x10000000, |
621 | .default_cpu_model = "Fujitsu MB86904", | |
e0353fe2 BS |
622 | }, |
623 | /* SS-10 */ | |
e0353fe2 | 624 | { |
5dcb6b91 BS |
625 | .iommu_base = 0xfe0000000ULL, |
626 | .tcx_base = 0xe20000000ULL, | |
5dcb6b91 BS |
627 | .slavio_base = 0xff0000000ULL, |
628 | .ms_kb_base = 0xff1000000ULL, | |
629 | .serial_base = 0xff1100000ULL, | |
630 | .nvram_base = 0xff1200000ULL, | |
631 | .fd_base = 0xff1700000ULL, | |
632 | .counter_base = 0xff1300000ULL, | |
633 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 634 | .idreg_base = 0xef0000000ULL, |
5dcb6b91 BS |
635 | .dma_base = 0xef0400000ULL, |
636 | .esp_base = 0xef0800000ULL, | |
637 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 638 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
639 | .aux1_base = 0xff1800000ULL, |
640 | .aux2_base = 0xff1a01000ULL, | |
7eb0c8e8 BS |
641 | .ecc_base = 0xf00000000ULL, |
642 | .ecc_version = 0x10000000, // version 0, implementation 1 | |
e0353fe2 BS |
643 | .vram_size = 0x00100000, |
644 | .nvram_size = 0x2000, | |
645 | .esp_irq = 18, | |
646 | .le_irq = 16, | |
e3a79bca | 647 | .clock_irq = 7, |
e0353fe2 BS |
648 | .clock1_irq = 19, |
649 | .ms_kb_irq = 14, | |
650 | .ser_irq = 15, | |
651 | .fd_irq = 22, | |
652 | .me_irq = 30, | |
e42c20b4 | 653 | .ecc_irq = 28, |
905fdcb5 BS |
654 | .nvram_machine_id = 0x72, |
655 | .machine_id = ss10_id, | |
7fbfb139 | 656 | .iommu_version = 0x03000000, |
e0353fe2 | 657 | .intbit_to_level = { |
f930d07e BS |
658 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
659 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
e0353fe2 | 660 | }, |
6ef05b95 | 661 | .max_mem = 0xf00000000ULL, |
3ebf5aaf | 662 | .default_cpu_model = "TI SuperSparc II", |
36cd9210 | 663 | }, |
6a3b9cc9 BS |
664 | /* SS-600MP */ |
665 | { | |
666 | .iommu_base = 0xfe0000000ULL, | |
667 | .tcx_base = 0xe20000000ULL, | |
6a3b9cc9 BS |
668 | .slavio_base = 0xff0000000ULL, |
669 | .ms_kb_base = 0xff1000000ULL, | |
670 | .serial_base = 0xff1100000ULL, | |
671 | .nvram_base = 0xff1200000ULL, | |
6a3b9cc9 BS |
672 | .counter_base = 0xff1300000ULL, |
673 | .intctl_base = 0xff1400000ULL, | |
674 | .dma_base = 0xef0081000ULL, | |
675 | .esp_base = 0xef0080000ULL, | |
676 | .le_base = 0xef0060000ULL, | |
0019ad53 | 677 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
678 | .aux1_base = 0xff1800000ULL, |
679 | .aux2_base = 0xff1a01000ULL, // XXX should not exist | |
7eb0c8e8 BS |
680 | .ecc_base = 0xf00000000ULL, |
681 | .ecc_version = 0x00000000, // version 0, implementation 0 | |
6a3b9cc9 BS |
682 | .vram_size = 0x00100000, |
683 | .nvram_size = 0x2000, | |
684 | .esp_irq = 18, | |
685 | .le_irq = 16, | |
e3a79bca | 686 | .clock_irq = 7, |
6a3b9cc9 BS |
687 | .clock1_irq = 19, |
688 | .ms_kb_irq = 14, | |
689 | .ser_irq = 15, | |
690 | .fd_irq = 22, | |
691 | .me_irq = 30, | |
e42c20b4 | 692 | .ecc_irq = 28, |
905fdcb5 BS |
693 | .nvram_machine_id = 0x71, |
694 | .machine_id = ss600mp_id, | |
7fbfb139 | 695 | .iommu_version = 0x01000000, |
6a3b9cc9 BS |
696 | .intbit_to_level = { |
697 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
698 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
699 | }, | |
6ef05b95 | 700 | .max_mem = 0xf00000000ULL, |
3ebf5aaf | 701 | .default_cpu_model = "TI SuperSparc II", |
6a3b9cc9 | 702 | }, |
ae40972f BS |
703 | /* SS-20 */ |
704 | { | |
705 | .iommu_base = 0xfe0000000ULL, | |
706 | .tcx_base = 0xe20000000ULL, | |
ae40972f BS |
707 | .slavio_base = 0xff0000000ULL, |
708 | .ms_kb_base = 0xff1000000ULL, | |
709 | .serial_base = 0xff1100000ULL, | |
710 | .nvram_base = 0xff1200000ULL, | |
711 | .fd_base = 0xff1700000ULL, | |
712 | .counter_base = 0xff1300000ULL, | |
713 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 714 | .idreg_base = 0xef0000000ULL, |
ae40972f BS |
715 | .dma_base = 0xef0400000ULL, |
716 | .esp_base = 0xef0800000ULL, | |
717 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 718 | .apc_base = 0xefa000000ULL, // XXX should not exist |
577d8dd4 BS |
719 | .aux1_base = 0xff1800000ULL, |
720 | .aux2_base = 0xff1a01000ULL, | |
ae40972f BS |
721 | .ecc_base = 0xf00000000ULL, |
722 | .ecc_version = 0x20000000, // version 0, implementation 2 | |
723 | .vram_size = 0x00100000, | |
724 | .nvram_size = 0x2000, | |
725 | .esp_irq = 18, | |
726 | .le_irq = 16, | |
e3a79bca | 727 | .clock_irq = 7, |
ae40972f BS |
728 | .clock1_irq = 19, |
729 | .ms_kb_irq = 14, | |
730 | .ser_irq = 15, | |
731 | .fd_irq = 22, | |
732 | .me_irq = 30, | |
e42c20b4 | 733 | .ecc_irq = 28, |
905fdcb5 BS |
734 | .nvram_machine_id = 0x72, |
735 | .machine_id = ss20_id, | |
ae40972f BS |
736 | .iommu_version = 0x13000000, |
737 | .intbit_to_level = { | |
738 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
739 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
740 | }, | |
6ef05b95 | 741 | .max_mem = 0xf00000000ULL, |
ae40972f BS |
742 | .default_cpu_model = "TI SuperSparc II", |
743 | }, | |
a526a31c BS |
744 | /* Voyager */ |
745 | { | |
746 | .iommu_base = 0x10000000, | |
747 | .tcx_base = 0x50000000, | |
a526a31c BS |
748 | .slavio_base = 0x70000000, |
749 | .ms_kb_base = 0x71000000, | |
750 | .serial_base = 0x71100000, | |
751 | .nvram_base = 0x71200000, | |
752 | .fd_base = 0x71400000, | |
753 | .counter_base = 0x71d00000, | |
754 | .intctl_base = 0x71e00000, | |
755 | .idreg_base = 0x78000000, | |
756 | .dma_base = 0x78400000, | |
757 | .esp_base = 0x78800000, | |
758 | .le_base = 0x78c00000, | |
759 | .apc_base = 0x71300000, // pmc | |
760 | .aux1_base = 0x71900000, | |
761 | .aux2_base = 0x71910000, | |
a526a31c BS |
762 | .vram_size = 0x00100000, |
763 | .nvram_size = 0x2000, | |
764 | .esp_irq = 18, | |
765 | .le_irq = 16, | |
766 | .clock_irq = 7, | |
767 | .clock1_irq = 19, | |
768 | .ms_kb_irq = 14, | |
769 | .ser_irq = 15, | |
770 | .fd_irq = 22, | |
771 | .me_irq = 30, | |
905fdcb5 BS |
772 | .nvram_machine_id = 0x80, |
773 | .machine_id = vger_id, | |
a526a31c BS |
774 | .iommu_version = 0x05000000, |
775 | .intbit_to_level = { | |
776 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
777 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
778 | }, | |
779 | .max_mem = 0x10000000, | |
780 | .default_cpu_model = "Fujitsu MB86904", | |
781 | }, | |
782 | /* LX */ | |
783 | { | |
784 | .iommu_base = 0x10000000, | |
785 | .tcx_base = 0x50000000, | |
a526a31c BS |
786 | .slavio_base = 0x70000000, |
787 | .ms_kb_base = 0x71000000, | |
788 | .serial_base = 0x71100000, | |
789 | .nvram_base = 0x71200000, | |
790 | .fd_base = 0x71400000, | |
791 | .counter_base = 0x71d00000, | |
792 | .intctl_base = 0x71e00000, | |
793 | .idreg_base = 0x78000000, | |
794 | .dma_base = 0x78400000, | |
795 | .esp_base = 0x78800000, | |
796 | .le_base = 0x78c00000, | |
a526a31c BS |
797 | .aux1_base = 0x71900000, |
798 | .aux2_base = 0x71910000, | |
a526a31c BS |
799 | .vram_size = 0x00100000, |
800 | .nvram_size = 0x2000, | |
801 | .esp_irq = 18, | |
802 | .le_irq = 16, | |
803 | .clock_irq = 7, | |
804 | .clock1_irq = 19, | |
805 | .ms_kb_irq = 14, | |
806 | .ser_irq = 15, | |
807 | .fd_irq = 22, | |
808 | .me_irq = 30, | |
905fdcb5 BS |
809 | .nvram_machine_id = 0x80, |
810 | .machine_id = lx_id, | |
a526a31c BS |
811 | .iommu_version = 0x04000000, |
812 | .intbit_to_level = { | |
813 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
814 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
815 | }, | |
816 | .max_mem = 0x10000000, | |
817 | .default_cpu_model = "TI MicroSparc I", | |
818 | }, | |
819 | /* SS-4 */ | |
820 | { | |
821 | .iommu_base = 0x10000000, | |
822 | .tcx_base = 0x50000000, | |
823 | .cs_base = 0x6c000000, | |
824 | .slavio_base = 0x70000000, | |
825 | .ms_kb_base = 0x71000000, | |
826 | .serial_base = 0x71100000, | |
827 | .nvram_base = 0x71200000, | |
828 | .fd_base = 0x71400000, | |
829 | .counter_base = 0x71d00000, | |
830 | .intctl_base = 0x71e00000, | |
831 | .idreg_base = 0x78000000, | |
832 | .dma_base = 0x78400000, | |
833 | .esp_base = 0x78800000, | |
834 | .le_base = 0x78c00000, | |
835 | .apc_base = 0x6a000000, | |
836 | .aux1_base = 0x71900000, | |
837 | .aux2_base = 0x71910000, | |
a526a31c BS |
838 | .vram_size = 0x00100000, |
839 | .nvram_size = 0x2000, | |
840 | .esp_irq = 18, | |
841 | .le_irq = 16, | |
842 | .clock_irq = 7, | |
843 | .clock1_irq = 19, | |
844 | .ms_kb_irq = 14, | |
845 | .ser_irq = 15, | |
846 | .fd_irq = 22, | |
847 | .me_irq = 30, | |
848 | .cs_irq = 5, | |
905fdcb5 BS |
849 | .nvram_machine_id = 0x80, |
850 | .machine_id = ss4_id, | |
a526a31c BS |
851 | .iommu_version = 0x05000000, |
852 | .intbit_to_level = { | |
853 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
854 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
855 | }, | |
856 | .max_mem = 0x10000000, | |
857 | .default_cpu_model = "Fujitsu MB86904", | |
858 | }, | |
859 | /* SPARCClassic */ | |
860 | { | |
861 | .iommu_base = 0x10000000, | |
862 | .tcx_base = 0x50000000, | |
a526a31c BS |
863 | .slavio_base = 0x70000000, |
864 | .ms_kb_base = 0x71000000, | |
865 | .serial_base = 0x71100000, | |
866 | .nvram_base = 0x71200000, | |
867 | .fd_base = 0x71400000, | |
868 | .counter_base = 0x71d00000, | |
869 | .intctl_base = 0x71e00000, | |
870 | .idreg_base = 0x78000000, | |
871 | .dma_base = 0x78400000, | |
872 | .esp_base = 0x78800000, | |
873 | .le_base = 0x78c00000, | |
874 | .apc_base = 0x6a000000, | |
875 | .aux1_base = 0x71900000, | |
876 | .aux2_base = 0x71910000, | |
a526a31c BS |
877 | .vram_size = 0x00100000, |
878 | .nvram_size = 0x2000, | |
879 | .esp_irq = 18, | |
880 | .le_irq = 16, | |
881 | .clock_irq = 7, | |
882 | .clock1_irq = 19, | |
883 | .ms_kb_irq = 14, | |
884 | .ser_irq = 15, | |
885 | .fd_irq = 22, | |
886 | .me_irq = 30, | |
905fdcb5 BS |
887 | .nvram_machine_id = 0x80, |
888 | .machine_id = scls_id, | |
a526a31c BS |
889 | .iommu_version = 0x05000000, |
890 | .intbit_to_level = { | |
891 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
892 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
893 | }, | |
894 | .max_mem = 0x10000000, | |
895 | .default_cpu_model = "TI MicroSparc I", | |
896 | }, | |
897 | /* SPARCbook */ | |
898 | { | |
899 | .iommu_base = 0x10000000, | |
900 | .tcx_base = 0x50000000, // XXX | |
a526a31c BS |
901 | .slavio_base = 0x70000000, |
902 | .ms_kb_base = 0x71000000, | |
903 | .serial_base = 0x71100000, | |
904 | .nvram_base = 0x71200000, | |
905 | .fd_base = 0x71400000, | |
906 | .counter_base = 0x71d00000, | |
907 | .intctl_base = 0x71e00000, | |
908 | .idreg_base = 0x78000000, | |
909 | .dma_base = 0x78400000, | |
910 | .esp_base = 0x78800000, | |
911 | .le_base = 0x78c00000, | |
912 | .apc_base = 0x6a000000, | |
913 | .aux1_base = 0x71900000, | |
914 | .aux2_base = 0x71910000, | |
a526a31c BS |
915 | .vram_size = 0x00100000, |
916 | .nvram_size = 0x2000, | |
917 | .esp_irq = 18, | |
918 | .le_irq = 16, | |
919 | .clock_irq = 7, | |
920 | .clock1_irq = 19, | |
921 | .ms_kb_irq = 14, | |
922 | .ser_irq = 15, | |
923 | .fd_irq = 22, | |
924 | .me_irq = 30, | |
905fdcb5 BS |
925 | .nvram_machine_id = 0x80, |
926 | .machine_id = sbook_id, | |
a526a31c BS |
927 | .iommu_version = 0x05000000, |
928 | .intbit_to_level = { | |
929 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
930 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
931 | }, | |
932 | .max_mem = 0x10000000, | |
933 | .default_cpu_model = "TI MicroSparc I", | |
934 | }, | |
36cd9210 BS |
935 | }; |
936 | ||
36cd9210 | 937 | /* SPARCstation 5 hardware initialisation */ |
00f82b8a | 938 | static void ss5_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 939 | const char *boot_device, |
b881c2c6 BS |
940 | const char *kernel_filename, const char *kernel_cmdline, |
941 | const char *initrd_filename, const char *cpu_model) | |
36cd9210 | 942 | { |
3023f332 | 943 | sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, |
3ebf5aaf | 944 | kernel_cmdline, initrd_filename, cpu_model); |
420557e8 | 945 | } |
c0e564d5 | 946 | |
e0353fe2 | 947 | /* SPARCstation 10 hardware initialisation */ |
00f82b8a | 948 | static void ss10_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 949 | const char *boot_device, |
b881c2c6 BS |
950 | const char *kernel_filename, const char *kernel_cmdline, |
951 | const char *initrd_filename, const char *cpu_model) | |
e0353fe2 | 952 | { |
3023f332 | 953 | sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, |
3ebf5aaf | 954 | kernel_cmdline, initrd_filename, cpu_model); |
e0353fe2 BS |
955 | } |
956 | ||
6a3b9cc9 | 957 | /* SPARCserver 600MP hardware initialisation */ |
00f82b8a | 958 | static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 959 | const char *boot_device, |
77f193da BS |
960 | const char *kernel_filename, |
961 | const char *kernel_cmdline, | |
6a3b9cc9 BS |
962 | const char *initrd_filename, const char *cpu_model) |
963 | { | |
3023f332 | 964 | sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, |
3ebf5aaf | 965 | kernel_cmdline, initrd_filename, cpu_model); |
6a3b9cc9 BS |
966 | } |
967 | ||
ae40972f | 968 | /* SPARCstation 20 hardware initialisation */ |
00f82b8a | 969 | static void ss20_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 970 | const char *boot_device, |
ae40972f BS |
971 | const char *kernel_filename, const char *kernel_cmdline, |
972 | const char *initrd_filename, const char *cpu_model) | |
973 | { | |
3023f332 | 974 | sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, |
ee76f82e BS |
975 | kernel_cmdline, initrd_filename, cpu_model); |
976 | } | |
977 | ||
a526a31c | 978 | /* SPARCstation Voyager hardware initialisation */ |
6ef05b95 | 979 | static void vger_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 980 | const char *boot_device, |
a526a31c BS |
981 | const char *kernel_filename, const char *kernel_cmdline, |
982 | const char *initrd_filename, const char *cpu_model) | |
983 | { | |
3023f332 | 984 | sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
985 | kernel_cmdline, initrd_filename, cpu_model); |
986 | } | |
987 | ||
988 | /* SPARCstation LX hardware initialisation */ | |
6ef05b95 | 989 | static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 990 | const char *boot_device, |
a526a31c BS |
991 | const char *kernel_filename, const char *kernel_cmdline, |
992 | const char *initrd_filename, const char *cpu_model) | |
993 | { | |
3023f332 | 994 | sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
995 | kernel_cmdline, initrd_filename, cpu_model); |
996 | } | |
997 | ||
998 | /* SPARCstation 4 hardware initialisation */ | |
6ef05b95 | 999 | static void ss4_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 1000 | const char *boot_device, |
a526a31c BS |
1001 | const char *kernel_filename, const char *kernel_cmdline, |
1002 | const char *initrd_filename, const char *cpu_model) | |
1003 | { | |
3023f332 | 1004 | sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1005 | kernel_cmdline, initrd_filename, cpu_model); |
1006 | } | |
1007 | ||
1008 | /* SPARCClassic hardware initialisation */ | |
6ef05b95 | 1009 | static void scls_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 1010 | const char *boot_device, |
a526a31c BS |
1011 | const char *kernel_filename, const char *kernel_cmdline, |
1012 | const char *initrd_filename, const char *cpu_model) | |
1013 | { | |
3023f332 | 1014 | sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1015 | kernel_cmdline, initrd_filename, cpu_model); |
1016 | } | |
1017 | ||
1018 | /* SPARCbook hardware initialisation */ | |
6ef05b95 | 1019 | static void sbook_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 1020 | const char *boot_device, |
a526a31c BS |
1021 | const char *kernel_filename, const char *kernel_cmdline, |
1022 | const char *initrd_filename, const char *cpu_model) | |
1023 | { | |
3023f332 | 1024 | sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1025 | kernel_cmdline, initrd_filename, cpu_model); |
1026 | } | |
1027 | ||
36cd9210 | 1028 | QEMUMachine ss5_machine = { |
66de733b BS |
1029 | .name = "SS-5", |
1030 | .desc = "Sun4m platform, SPARCstation 5", | |
1031 | .init = ss5_init, | |
1032 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1033 | .use_scsi = 1, |
c0e564d5 | 1034 | }; |
e0353fe2 BS |
1035 | |
1036 | QEMUMachine ss10_machine = { | |
66de733b BS |
1037 | .name = "SS-10", |
1038 | .desc = "Sun4m platform, SPARCstation 10", | |
1039 | .init = ss10_init, | |
1040 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1041 | .use_scsi = 1, |
1bcee014 | 1042 | .max_cpus = 4, |
e0353fe2 | 1043 | }; |
6a3b9cc9 BS |
1044 | |
1045 | QEMUMachine ss600mp_machine = { | |
66de733b BS |
1046 | .name = "SS-600MP", |
1047 | .desc = "Sun4m platform, SPARCserver 600MP", | |
1048 | .init = ss600mp_init, | |
1049 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1050 | .use_scsi = 1, |
1bcee014 | 1051 | .max_cpus = 4, |
6a3b9cc9 | 1052 | }; |
ae40972f BS |
1053 | |
1054 | QEMUMachine ss20_machine = { | |
66de733b BS |
1055 | .name = "SS-20", |
1056 | .desc = "Sun4m platform, SPARCstation 20", | |
1057 | .init = ss20_init, | |
1058 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1059 | .use_scsi = 1, |
1bcee014 | 1060 | .max_cpus = 4, |
ae40972f BS |
1061 | }; |
1062 | ||
a526a31c | 1063 | QEMUMachine voyager_machine = { |
66de733b BS |
1064 | .name = "Voyager", |
1065 | .desc = "Sun4m platform, SPARCstation Voyager", | |
1066 | .init = vger_init, | |
1067 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1068 | .use_scsi = 1, |
a526a31c BS |
1069 | }; |
1070 | ||
1071 | QEMUMachine ss_lx_machine = { | |
66de733b BS |
1072 | .name = "LX", |
1073 | .desc = "Sun4m platform, SPARCstation LX", | |
1074 | .init = ss_lx_init, | |
1075 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1076 | .use_scsi = 1, |
a526a31c BS |
1077 | }; |
1078 | ||
1079 | QEMUMachine ss4_machine = { | |
66de733b BS |
1080 | .name = "SS-4", |
1081 | .desc = "Sun4m platform, SPARCstation 4", | |
1082 | .init = ss4_init, | |
1083 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1084 | .use_scsi = 1, |
a526a31c BS |
1085 | }; |
1086 | ||
1087 | QEMUMachine scls_machine = { | |
66de733b BS |
1088 | .name = "SPARCClassic", |
1089 | .desc = "Sun4m platform, SPARCClassic", | |
1090 | .init = scls_init, | |
1091 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1092 | .use_scsi = 1, |
a526a31c BS |
1093 | }; |
1094 | ||
1095 | QEMUMachine sbook_machine = { | |
66de733b BS |
1096 | .name = "SPARCbook", |
1097 | .desc = "Sun4m platform, SPARCbook", | |
1098 | .init = sbook_init, | |
1099 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1100 | .use_scsi = 1, |
a526a31c BS |
1101 | }; |
1102 | ||
7d85892b BS |
1103 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1104 | /* SS-1000 */ | |
1105 | { | |
1106 | .iounit_bases = { | |
1107 | 0xfe0200000ULL, | |
1108 | 0xfe1200000ULL, | |
1109 | 0xfe2200000ULL, | |
1110 | 0xfe3200000ULL, | |
1111 | -1, | |
1112 | }, | |
1113 | .tcx_base = 0x820000000ULL, | |
1114 | .slavio_base = 0xf00000000ULL, | |
1115 | .ms_kb_base = 0xf00240000ULL, | |
1116 | .serial_base = 0xf00200000ULL, | |
1117 | .nvram_base = 0xf00280000ULL, | |
1118 | .counter_base = 0xf00300000ULL, | |
1119 | .espdma_base = 0x800081000ULL, | |
1120 | .esp_base = 0x800080000ULL, | |
1121 | .ledma_base = 0x800040000ULL, | |
1122 | .le_base = 0x800060000ULL, | |
1123 | .sbi_base = 0xf02800000ULL, | |
c1d00dc0 | 1124 | .vram_size = 0x00100000, |
7d85892b BS |
1125 | .nvram_size = 0x2000, |
1126 | .esp_irq = 3, | |
1127 | .le_irq = 4, | |
1128 | .clock_irq = 14, | |
1129 | .clock1_irq = 10, | |
1130 | .ms_kb_irq = 12, | |
1131 | .ser_irq = 12, | |
905fdcb5 BS |
1132 | .nvram_machine_id = 0x80, |
1133 | .machine_id = ss1000_id, | |
7d85892b | 1134 | .iounit_version = 0x03000000, |
6ef05b95 | 1135 | .max_mem = 0xf00000000ULL, |
7d85892b BS |
1136 | .default_cpu_model = "TI SuperSparc II", |
1137 | }, | |
1138 | /* SS-2000 */ | |
1139 | { | |
1140 | .iounit_bases = { | |
1141 | 0xfe0200000ULL, | |
1142 | 0xfe1200000ULL, | |
1143 | 0xfe2200000ULL, | |
1144 | 0xfe3200000ULL, | |
1145 | 0xfe4200000ULL, | |
1146 | }, | |
1147 | .tcx_base = 0x820000000ULL, | |
1148 | .slavio_base = 0xf00000000ULL, | |
1149 | .ms_kb_base = 0xf00240000ULL, | |
1150 | .serial_base = 0xf00200000ULL, | |
1151 | .nvram_base = 0xf00280000ULL, | |
1152 | .counter_base = 0xf00300000ULL, | |
1153 | .espdma_base = 0x800081000ULL, | |
1154 | .esp_base = 0x800080000ULL, | |
1155 | .ledma_base = 0x800040000ULL, | |
1156 | .le_base = 0x800060000ULL, | |
1157 | .sbi_base = 0xf02800000ULL, | |
c1d00dc0 | 1158 | .vram_size = 0x00100000, |
7d85892b BS |
1159 | .nvram_size = 0x2000, |
1160 | .esp_irq = 3, | |
1161 | .le_irq = 4, | |
1162 | .clock_irq = 14, | |
1163 | .clock1_irq = 10, | |
1164 | .ms_kb_irq = 12, | |
1165 | .ser_irq = 12, | |
905fdcb5 BS |
1166 | .nvram_machine_id = 0x80, |
1167 | .machine_id = ss2000_id, | |
7d85892b | 1168 | .iounit_version = 0x03000000, |
6ef05b95 | 1169 | .max_mem = 0xf00000000ULL, |
7d85892b BS |
1170 | .default_cpu_model = "TI SuperSparc II", |
1171 | }, | |
1172 | }; | |
1173 | ||
6ef05b95 | 1174 | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
7d85892b | 1175 | const char *boot_device, |
3023f332 | 1176 | const char *kernel_filename, |
7d85892b BS |
1177 | const char *kernel_cmdline, |
1178 | const char *initrd_filename, const char *cpu_model) | |
1179 | { | |
1180 | CPUState *env, *envs[MAX_CPUS]; | |
1181 | unsigned int i; | |
1182 | void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi; | |
1183 | qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, | |
1184 | *espdma_irq, *ledma_irq; | |
1185 | qemu_irq *esp_reset, *le_reset; | |
5c6602c5 BS |
1186 | ram_addr_t ram_offset, prom_offset, tcx_offset; |
1187 | unsigned long kernel_size; | |
7d85892b BS |
1188 | int ret; |
1189 | char buf[1024]; | |
22548760 | 1190 | int drive_index; |
3cce6243 | 1191 | void *fw_cfg; |
7d85892b BS |
1192 | |
1193 | /* init CPUs */ | |
1194 | if (!cpu_model) | |
1195 | cpu_model = hwdef->default_cpu_model; | |
1196 | ||
1197 | for (i = 0; i < smp_cpus; i++) { | |
1198 | env = cpu_init(cpu_model); | |
1199 | if (!env) { | |
8e82c6a8 | 1200 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); |
7d85892b BS |
1201 | exit(1); |
1202 | } | |
1203 | cpu_sparc_set_id(env, i); | |
1204 | envs[i] = env; | |
1205 | if (i == 0) { | |
1206 | qemu_register_reset(main_cpu_reset, env); | |
1207 | } else { | |
1208 | qemu_register_reset(secondary_cpu_reset, env); | |
1209 | env->halted = 1; | |
1210 | } | |
7d85892b BS |
1211 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
1212 | env->prom_addr = hwdef->slavio_base; | |
1213 | } | |
1214 | ||
1215 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
1216 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
1217 | ||
1218 | /* allocate RAM */ | |
1219 | if ((uint64_t)RAM_size > hwdef->max_mem) { | |
77f193da BS |
1220 | fprintf(stderr, |
1221 | "qemu: Too much memory for this machine: %d, maximum %d\n", | |
6ef05b95 | 1222 | (unsigned int)(RAM_size / (1024 * 1024)), |
7d85892b BS |
1223 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
1224 | exit(1); | |
1225 | } | |
5c6602c5 BS |
1226 | ram_offset = qemu_ram_alloc(RAM_size); |
1227 | cpu_register_physical_memory(0, RAM_size, ram_offset); | |
7d85892b BS |
1228 | |
1229 | /* load boot prom */ | |
5c6602c5 | 1230 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
7d85892b BS |
1231 | cpu_register_physical_memory(hwdef->slavio_base, |
1232 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & | |
1233 | TARGET_PAGE_MASK, | |
1234 | prom_offset | IO_MEM_ROM); | |
1235 | ||
1236 | if (bios_name == NULL) | |
1237 | bios_name = PROM_FILENAME; | |
1238 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
1239 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); | |
1240 | if (ret < 0 || ret > PROM_SIZE_MAX) | |
e01f4a1c | 1241 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
7d85892b BS |
1242 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
1243 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
1244 | buf); | |
1245 | exit(1); | |
1246 | } | |
1247 | ||
1248 | /* set up devices */ | |
1249 | sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); | |
1250 | ||
1251 | for (i = 0; i < MAX_IOUNITS; i++) | |
1252 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) | |
ff403da6 BS |
1253 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1254 | hwdef->iounit_version, | |
1255 | sbi_irq[hwdef->me_irq]); | |
7d85892b BS |
1256 | |
1257 | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], | |
1258 | iounits[0], &espdma_irq, &esp_reset); | |
1259 | ||
1260 | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], | |
1261 | iounits[0], &ledma_irq, &le_reset); | |
1262 | ||
1263 | if (graphic_depth != 8 && graphic_depth != 24) { | |
1264 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
1265 | exit (1); | |
1266 | } | |
5c6602c5 | 1267 | tcx_offset = qemu_ram_alloc(hwdef->vram_size); |
3023f332 | 1268 | tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset, |
7d85892b BS |
1269 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
1270 | ||
0ae18cee | 1271 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); |
7d85892b BS |
1272 | |
1273 | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, | |
1274 | hwdef->nvram_size, 8); | |
1275 | ||
1276 | slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], | |
1277 | sbi_cpu_irq, smp_cpus); | |
1278 | ||
1279 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], | |
b4ed08e0 | 1280 | nographic, ESCC_CLOCK, 1); |
7d85892b BS |
1281 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
1282 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
aeeb69c7 AJ |
1283 | escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq], |
1284 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); | |
7d85892b BS |
1285 | |
1286 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
1287 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
1288 | exit(1); | |
1289 | } | |
1290 | ||
5d20fa6b | 1291 | main_esp = esp_init(hwdef->esp_base, 2, |
8b17de88 BS |
1292 | espdma_memory_read, espdma_memory_write, |
1293 | espdma, *espdma_irq, esp_reset); | |
7d85892b BS |
1294 | |
1295 | for (i = 0; i < ESP_MAX_DEVS; i++) { | |
22548760 BS |
1296 | drive_index = drive_get_index(IF_SCSI, 0, i); |
1297 | if (drive_index == -1) | |
7d85892b | 1298 | continue; |
22548760 | 1299 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
7d85892b BS |
1300 | } |
1301 | ||
293f78bc BS |
1302 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1303 | RAM_size); | |
7d85892b BS |
1304 | |
1305 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, | |
1306 | boot_device, RAM_size, kernel_size, graphic_width, | |
905fdcb5 BS |
1307 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1308 | "Sun4d"); | |
3cce6243 BS |
1309 | |
1310 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); | |
1311 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 BS |
1312 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1313 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
513f789f BS |
1314 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1315 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); | |
1316 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1317 | if (kernel_cmdline) { | |
1318 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
1319 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
1320 | } else { | |
1321 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
1322 | } | |
1323 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
1324 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used | |
1325 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
1326 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
7d85892b BS |
1327 | } |
1328 | ||
1329 | /* SPARCserver 1000 hardware initialisation */ | |
00f82b8a | 1330 | static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 1331 | const char *boot_device, |
7d85892b BS |
1332 | const char *kernel_filename, const char *kernel_cmdline, |
1333 | const char *initrd_filename, const char *cpu_model) | |
1334 | { | |
3023f332 | 1335 | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename, |
7d85892b BS |
1336 | kernel_cmdline, initrd_filename, cpu_model); |
1337 | } | |
1338 | ||
1339 | /* SPARCcenter 2000 hardware initialisation */ | |
00f82b8a | 1340 | static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size, |
3023f332 | 1341 | const char *boot_device, |
7d85892b BS |
1342 | const char *kernel_filename, const char *kernel_cmdline, |
1343 | const char *initrd_filename, const char *cpu_model) | |
1344 | { | |
3023f332 | 1345 | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename, |
7d85892b BS |
1346 | kernel_cmdline, initrd_filename, cpu_model); |
1347 | } | |
1348 | ||
1349 | QEMUMachine ss1000_machine = { | |
66de733b BS |
1350 | .name = "SS-1000", |
1351 | .desc = "Sun4d platform, SPARCserver 1000", | |
1352 | .init = ss1000_init, | |
1353 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1354 | .use_scsi = 1, |
1bcee014 | 1355 | .max_cpus = 8, |
7d85892b BS |
1356 | }; |
1357 | ||
1358 | QEMUMachine ss2000_machine = { | |
66de733b BS |
1359 | .name = "SS-2000", |
1360 | .desc = "Sun4d platform, SPARCcenter 2000", | |
1361 | .init = ss2000_init, | |
1362 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
c9b1ae2c | 1363 | .use_scsi = 1, |
1bcee014 | 1364 | .max_cpus = 20, |
7d85892b | 1365 | }; |
8137cde8 BS |
1366 | |
1367 | static const struct sun4c_hwdef sun4c_hwdefs[] = { | |
1368 | /* SS-2 */ | |
1369 | { | |
1370 | .iommu_base = 0xf8000000, | |
1371 | .tcx_base = 0xfe000000, | |
8137cde8 BS |
1372 | .slavio_base = 0xf6000000, |
1373 | .intctl_base = 0xf5000000, | |
1374 | .counter_base = 0xf3000000, | |
1375 | .ms_kb_base = 0xf0000000, | |
1376 | .serial_base = 0xf1000000, | |
1377 | .nvram_base = 0xf2000000, | |
1378 | .fd_base = 0xf7200000, | |
1379 | .dma_base = 0xf8400000, | |
1380 | .esp_base = 0xf8800000, | |
1381 | .le_base = 0xf8c00000, | |
8137cde8 | 1382 | .aux1_base = 0xf7400003, |
8137cde8 BS |
1383 | .vram_size = 0x00100000, |
1384 | .nvram_size = 0x800, | |
1385 | .esp_irq = 2, | |
1386 | .le_irq = 3, | |
1387 | .clock_irq = 5, | |
1388 | .clock1_irq = 7, | |
1389 | .ms_kb_irq = 1, | |
1390 | .ser_irq = 1, | |
1391 | .fd_irq = 1, | |
1392 | .me_irq = 1, | |
8137cde8 BS |
1393 | .nvram_machine_id = 0x55, |
1394 | .machine_id = ss2_id, | |
1395 | .max_mem = 0x10000000, | |
1396 | .default_cpu_model = "Cypress CY7C601", | |
1397 | }, | |
1398 | }; | |
1399 | ||
1400 | static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, | |
1401 | const char *boot_device, | |
3023f332 | 1402 | const char *kernel_filename, |
8137cde8 BS |
1403 | const char *kernel_cmdline, |
1404 | const char *initrd_filename, const char *cpu_model) | |
1405 | { | |
1406 | CPUState *env; | |
1407 | unsigned int i; | |
1408 | void *iommu, *espdma, *ledma, *main_esp, *nvram; | |
1409 | qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; | |
1410 | qemu_irq *esp_reset, *le_reset; | |
1411 | qemu_irq *fdc_tc; | |
5c6602c5 BS |
1412 | ram_addr_t ram_offset, prom_offset, tcx_offset; |
1413 | unsigned long kernel_size; | |
8137cde8 BS |
1414 | int ret; |
1415 | char buf[1024]; | |
1416 | BlockDriverState *fd[MAX_FD]; | |
1417 | int drive_index; | |
1418 | void *fw_cfg; | |
1419 | ||
1420 | /* init CPU */ | |
1421 | if (!cpu_model) | |
1422 | cpu_model = hwdef->default_cpu_model; | |
1423 | ||
1424 | env = cpu_init(cpu_model); | |
1425 | if (!env) { | |
1426 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); | |
1427 | exit(1); | |
1428 | } | |
1429 | ||
1430 | cpu_sparc_set_id(env, 0); | |
1431 | ||
1432 | qemu_register_reset(main_cpu_reset, env); | |
1433 | cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | |
1434 | env->prom_addr = hwdef->slavio_base; | |
1435 | ||
1436 | /* allocate RAM */ | |
1437 | if ((uint64_t)RAM_size > hwdef->max_mem) { | |
1438 | fprintf(stderr, | |
1439 | "qemu: Too much memory for this machine: %d, maximum %d\n", | |
1440 | (unsigned int)(RAM_size / (1024 * 1024)), | |
1441 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); | |
1442 | exit(1); | |
1443 | } | |
5c6602c5 BS |
1444 | ram_offset = qemu_ram_alloc(RAM_size); |
1445 | cpu_register_physical_memory(0, RAM_size, ram_offset); | |
8137cde8 BS |
1446 | |
1447 | /* load boot prom */ | |
5c6602c5 | 1448 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
8137cde8 BS |
1449 | cpu_register_physical_memory(hwdef->slavio_base, |
1450 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & | |
1451 | TARGET_PAGE_MASK, | |
1452 | prom_offset | IO_MEM_ROM); | |
1453 | ||
1454 | if (bios_name == NULL) | |
1455 | bios_name = PROM_FILENAME; | |
1456 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
1457 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); | |
1458 | if (ret < 0 || ret > PROM_SIZE_MAX) | |
1459 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); | |
1460 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
1461 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
1462 | buf); | |
1463 | exit(1); | |
1464 | } | |
8137cde8 BS |
1465 | |
1466 | /* set up devices */ | |
1467 | slavio_intctl = sun4c_intctl_init(hwdef->intctl_base, | |
1468 | &slavio_irq, cpu_irqs); | |
1469 | ||
1470 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, | |
1471 | slavio_irq[hwdef->me_irq]); | |
1472 | ||
1473 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], | |
1474 | iommu, &espdma_irq, &esp_reset); | |
1475 | ||
1476 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, | |
1477 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, | |
1478 | &le_reset); | |
1479 | ||
1480 | if (graphic_depth != 8 && graphic_depth != 24) { | |
1481 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
1482 | exit (1); | |
1483 | } | |
5c6602c5 | 1484 | tcx_offset = qemu_ram_alloc(hwdef->vram_size); |
3023f332 | 1485 | tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset, |
8137cde8 BS |
1486 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
1487 | ||
0ae18cee | 1488 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); |
8137cde8 BS |
1489 | |
1490 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, | |
1491 | hwdef->nvram_size, 2); | |
1492 | ||
1493 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], | |
b4ed08e0 | 1494 | nographic, ESCC_CLOCK, 1); |
8137cde8 BS |
1495 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
1496 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
aeeb69c7 AJ |
1497 | escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
1498 | slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1], | |
1499 | ESCC_CLOCK, 1); | |
8137cde8 | 1500 | |
fe096129 | 1501 | slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0, |
6d0c293d | 1502 | slavio_irq[hwdef->me_irq], NULL, &fdc_tc); |
8137cde8 BS |
1503 | |
1504 | if (hwdef->fd_base != (target_phys_addr_t)-1) { | |
1505 | /* there is zero or one floppy drive */ | |
ce802585 | 1506 | memset(fd, 0, sizeof(fd)); |
8137cde8 BS |
1507 | drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
1508 | if (drive_index != -1) | |
1509 | fd[0] = drives_table[drive_index].bdrv; | |
1510 | ||
1511 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, | |
1512 | fdc_tc); | |
1513 | } | |
1514 | ||
1515 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
1516 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
1517 | exit(1); | |
1518 | } | |
1519 | ||
1520 | main_esp = esp_init(hwdef->esp_base, 2, | |
1521 | espdma_memory_read, espdma_memory_write, | |
1522 | espdma, *espdma_irq, esp_reset); | |
1523 | ||
1524 | for (i = 0; i < ESP_MAX_DEVS; i++) { | |
1525 | drive_index = drive_get_index(IF_SCSI, 0, i); | |
1526 | if (drive_index == -1) | |
1527 | continue; | |
1528 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); | |
1529 | } | |
1530 | ||
1531 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, | |
1532 | RAM_size); | |
1533 | ||
1534 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, | |
1535 | boot_device, RAM_size, kernel_size, graphic_width, | |
1536 | graphic_height, graphic_depth, hwdef->nvram_machine_id, | |
1537 | "Sun4c"); | |
1538 | ||
1539 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); | |
1540 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
1541 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
1542 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
513f789f BS |
1543 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1544 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); | |
1545 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1546 | if (kernel_cmdline) { | |
1547 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
1548 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
1549 | } else { | |
1550 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
1551 | } | |
1552 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
1553 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used | |
1554 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
1555 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
8137cde8 BS |
1556 | } |
1557 | ||
1558 | /* SPARCstation 2 hardware initialisation */ | |
1559 | static void ss2_init(ram_addr_t RAM_size, int vga_ram_size, | |
3023f332 | 1560 | const char *boot_device, |
8137cde8 BS |
1561 | const char *kernel_filename, const char *kernel_cmdline, |
1562 | const char *initrd_filename, const char *cpu_model) | |
1563 | { | |
3023f332 | 1564 | sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename, |
8137cde8 BS |
1565 | kernel_cmdline, initrd_filename, cpu_model); |
1566 | } | |
1567 | ||
1568 | QEMUMachine ss2_machine = { | |
1569 | .name = "SS-2", | |
1570 | .desc = "Sun4c platform, SPARCstation 2", | |
1571 | .init = ss2_init, | |
1572 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, | |
8137cde8 | 1573 | .use_scsi = 1, |
8137cde8 | 1574 | }; |