]>
Commit | Line | Data |
---|---|---|
420557e8 | 1 | /* |
ee76f82e | 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
5fafdf24 | 3 | * |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "qemu-timer.h" | |
26 | #include "sun4m.h" | |
27 | #include "nvram.h" | |
28 | #include "sparc32_dma.h" | |
29 | #include "fdc.h" | |
30 | #include "sysemu.h" | |
31 | #include "net.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
8b17de88 | 34 | #include "scsi.h" |
d2c63fc1 | 35 | |
b3a23197 | 36 | //#define DEBUG_IRQ |
420557e8 | 37 | |
36cd9210 BS |
38 | /* |
39 | * Sun4m architecture was used in the following machines: | |
40 | * | |
41 | * SPARCserver 6xxMP/xx | |
42 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10) | |
43 | * SPARCstation LX/ZX (4/30) | |
44 | * SPARCstation Voyager | |
45 | * SPARCstation 10/xx, SPARCserver 10/xx | |
46 | * SPARCstation 5, SPARCserver 5 | |
47 | * SPARCstation 20/xx, SPARCserver 20 | |
48 | * SPARCstation 4 | |
49 | * | |
7d85892b BS |
50 | * Sun4d architecture was used in the following machines: |
51 | * | |
52 | * SPARCcenter 2000 | |
53 | * SPARCserver 1000 | |
54 | * | |
ee76f82e BS |
55 | * Sun4c architecture was used in the following machines: |
56 | * SPARCstation 1/1+, SPARCserver 1/1+ | |
57 | * SPARCstation SLC | |
58 | * SPARCstation IPC | |
59 | * SPARCstation ELC | |
60 | * SPARCstation IPX | |
61 | * | |
36cd9210 BS |
62 | * See for example: http://www.sunhelp.org/faq/sunref1.html |
63 | */ | |
64 | ||
b3a23197 BS |
65 | #ifdef DEBUG_IRQ |
66 | #define DPRINTF(fmt, args...) \ | |
67 | do { printf("CPUIRQ: " fmt , ##args); } while (0) | |
68 | #else | |
69 | #define DPRINTF(fmt, args...) | |
70 | #endif | |
71 | ||
420557e8 | 72 | #define KERNEL_LOAD_ADDR 0x00004000 |
b6f479d3 | 73 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 74 | #define INITRD_LOAD_ADDR 0x00800000 |
aa6ad6fe | 75 | #define PROM_SIZE_MAX (512 * 1024) |
40ce0a9a | 76 | #define PROM_VADDR 0xffd00000 |
f930d07e | 77 | #define PROM_FILENAME "openbios-sparc32" |
b8174937 | 78 | |
ba3c64fb | 79 | #define MAX_CPUS 16 |
b3a23197 | 80 | #define MAX_PILS 16 |
420557e8 | 81 | |
36cd9210 | 82 | struct hwdef { |
5dcb6b91 BS |
83 | target_phys_addr_t iommu_base, slavio_base; |
84 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; | |
85 | target_phys_addr_t serial_base, fd_base; | |
4c2485de | 86 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
0019ad53 | 87 | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
7eb0c8e8 BS |
88 | target_phys_addr_t ecc_base; |
89 | uint32_t ecc_version; | |
ee76f82e | 90 | target_phys_addr_t sun4c_intctl_base, sun4c_counter_base; |
36cd9210 | 91 | long vram_size, nvram_size; |
6341fdcb | 92 | // IRQ numbers are not PIL ones, but master interrupt controller |
e3a79bca | 93 | // register bit numbers |
d7edfd27 | 94 | int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq; |
e42c20b4 | 95 | int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq; |
36cd9210 | 96 | int machine_id; // For NVRAM |
7fbfb139 | 97 | uint32_t iommu_version; |
e0353fe2 | 98 | uint32_t intbit_to_level[32]; |
3ebf5aaf BS |
99 | uint64_t max_mem; |
100 | const char * const default_cpu_model; | |
36cd9210 BS |
101 | }; |
102 | ||
7d85892b BS |
103 | #define MAX_IOUNITS 5 |
104 | ||
105 | struct sun4d_hwdef { | |
106 | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; | |
107 | target_phys_addr_t counter_base, nvram_base, ms_kb_base; | |
108 | target_phys_addr_t serial_base; | |
109 | target_phys_addr_t espdma_base, esp_base; | |
110 | target_phys_addr_t ledma_base, le_base; | |
111 | target_phys_addr_t tcx_base; | |
112 | target_phys_addr_t sbi_base; | |
113 | unsigned long vram_size, nvram_size; | |
114 | // IRQ numbers are not PIL ones, but SBI register bit numbers | |
115 | int esp_irq, le_irq, clock_irq, clock1_irq; | |
116 | int ser_irq, ms_kb_irq, me_irq; | |
117 | int machine_id; // For NVRAM | |
118 | uint32_t iounit_version; | |
119 | uint64_t max_mem; | |
120 | const char * const default_cpu_model; | |
121 | }; | |
122 | ||
420557e8 FB |
123 | /* TSC handling */ |
124 | ||
125 | uint64_t cpu_get_tsc() | |
126 | { | |
127 | return qemu_get_clock(vm_clock); | |
128 | } | |
129 | ||
6f7e9aec FB |
130 | int DMA_get_channel_mode (int nchan) |
131 | { | |
132 | return 0; | |
133 | } | |
134 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
135 | { | |
136 | return 0; | |
137 | } | |
138 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
139 | { | |
140 | return 0; | |
141 | } | |
142 | void DMA_hold_DREQ (int nchan) {} | |
143 | void DMA_release_DREQ (int nchan) {} | |
144 | void DMA_schedule(int nchan) {} | |
145 | void DMA_run (void) {} | |
146 | void DMA_init (int high_page_enable) {} | |
147 | void DMA_register_channel (int nchan, | |
148 | DMA_transfer_handler transfer_handler, | |
149 | void *opaque) | |
150 | { | |
151 | } | |
152 | ||
6f7e9aec FB |
153 | extern int nographic; |
154 | ||
819385c5 | 155 | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
d2c63fc1 | 156 | const char *boot_devices, uint32_t RAM_size, |
f930d07e BS |
157 | uint32_t kernel_size, |
158 | int width, int height, int depth, | |
7d85892b | 159 | int machine_id, const char *arch) |
e80cfcfc | 160 | { |
d2c63fc1 | 161 | unsigned int i; |
66508601 | 162 | uint32_t start, end; |
d2c63fc1 BS |
163 | uint8_t image[0x1ff0]; |
164 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ | |
165 | struct sparc_arch_cfg *sparc_header; | |
166 | struct OpenBIOS_nvpart_v1 *part_header; | |
167 | ||
168 | memset(image, '\0', sizeof(image)); | |
e80cfcfc | 169 | |
6f7e9aec | 170 | // Try to match PPC NVRAM |
d2c63fc1 BS |
171 | strcpy(header->struct_ident, "QEMU_BIOS"); |
172 | header->struct_version = cpu_to_be32(3); /* structure v3 */ | |
173 | ||
174 | header->nvram_size = cpu_to_be16(0x2000); | |
175 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t)); | |
176 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); | |
7d85892b | 177 | strcpy(header->arch, arch); |
d2c63fc1 BS |
178 | header->nb_cpus = smp_cpus & 0xff; |
179 | header->RAM0_base = 0; | |
180 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); | |
181 | strcpy(header->boot_devices, boot_devices); | |
182 | header->nboot_devices = strlen(boot_devices) & 0xff; | |
183 | header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR); | |
184 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); | |
b6f479d3 | 185 | if (cmdline) { |
f930d07e | 186 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
d2c63fc1 BS |
187 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
188 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); | |
b6f479d3 | 189 | } |
d2c63fc1 BS |
190 | // XXX add initrd_image, initrd_size |
191 | header->width = cpu_to_be16(width); | |
192 | header->height = cpu_to_be16(height); | |
193 | header->depth = cpu_to_be16(depth); | |
194 | if (nographic) | |
195 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); | |
196 | ||
197 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); | |
198 | ||
199 | // Architecture specific header | |
200 | start = sizeof(ohwcfg_v3_t); | |
201 | sparc_header = (struct sparc_arch_cfg *)&image[start]; | |
202 | sparc_header->valid = 0; | |
203 | start += sizeof(struct sparc_arch_cfg); | |
b6f479d3 | 204 | |
66508601 BS |
205 | // OpenBIOS nvram variables |
206 | // Variable partition | |
d2c63fc1 BS |
207 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
208 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
209 | strcpy(part_header->name, "system"); | |
66508601 | 210 | |
d2c63fc1 | 211 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 212 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
213 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
214 | ||
215 | // End marker | |
216 | image[end++] = '\0'; | |
66508601 | 217 | |
66508601 | 218 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 219 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
220 | |
221 | // free partition | |
222 | start = end; | |
d2c63fc1 BS |
223 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
224 | part_header->signature = OPENBIOS_PART_FREE; | |
225 | strcpy(part_header->name, "free"); | |
66508601 BS |
226 | |
227 | end = 0x1fd0; | |
d2c63fc1 BS |
228 | OpenBIOS_finish_partition(part_header, end - start); |
229 | ||
230 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id); | |
231 | ||
232 | for (i = 0; i < sizeof(image); i++) | |
233 | m48t59_write(nvram, i, image[i]); | |
e80cfcfc FB |
234 | } |
235 | ||
236 | static void *slavio_intctl; | |
237 | ||
238 | void pic_info() | |
239 | { | |
7d85892b BS |
240 | if (slavio_intctl) |
241 | slavio_pic_info(slavio_intctl); | |
e80cfcfc FB |
242 | } |
243 | ||
244 | void irq_info() | |
245 | { | |
7d85892b BS |
246 | if (slavio_intctl) |
247 | slavio_irq_info(slavio_intctl); | |
e80cfcfc FB |
248 | } |
249 | ||
327ac2e7 BS |
250 | void cpu_check_irqs(CPUState *env) |
251 | { | |
252 | if (env->pil_in && (env->interrupt_index == 0 || | |
253 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
254 | unsigned int i; | |
255 | ||
256 | for (i = 15; i > 0; i--) { | |
257 | if (env->pil_in & (1 << i)) { | |
258 | int old_interrupt = env->interrupt_index; | |
259 | ||
260 | env->interrupt_index = TT_EXTINT | i; | |
f32d7ec5 BS |
261 | if (old_interrupt != env->interrupt_index) { |
262 | DPRINTF("Set CPU IRQ %d\n", i); | |
327ac2e7 | 263 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
f32d7ec5 | 264 | } |
327ac2e7 BS |
265 | break; |
266 | } | |
267 | } | |
268 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { | |
f32d7ec5 | 269 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
327ac2e7 BS |
270 | env->interrupt_index = 0; |
271 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
272 | } | |
273 | } | |
274 | ||
b3a23197 BS |
275 | static void cpu_set_irq(void *opaque, int irq, int level) |
276 | { | |
277 | CPUState *env = opaque; | |
278 | ||
279 | if (level) { | |
280 | DPRINTF("Raise CPU IRQ %d\n", irq); | |
b3a23197 | 281 | env->halted = 0; |
327ac2e7 BS |
282 | env->pil_in |= 1 << irq; |
283 | cpu_check_irqs(env); | |
b3a23197 BS |
284 | } else { |
285 | DPRINTF("Lower CPU IRQ %d\n", irq); | |
327ac2e7 BS |
286 | env->pil_in &= ~(1 << irq); |
287 | cpu_check_irqs(env); | |
b3a23197 BS |
288 | } |
289 | } | |
290 | ||
291 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) | |
292 | { | |
293 | } | |
294 | ||
3475187d FB |
295 | static void *slavio_misc; |
296 | ||
297 | void qemu_system_powerdown(void) | |
298 | { | |
299 | slavio_set_power_fail(slavio_misc, 1); | |
300 | } | |
301 | ||
c68ea704 FB |
302 | static void main_cpu_reset(void *opaque) |
303 | { | |
304 | CPUState *env = opaque; | |
3d29fbef BS |
305 | |
306 | cpu_reset(env); | |
307 | env->halted = 0; | |
308 | } | |
309 | ||
310 | static void secondary_cpu_reset(void *opaque) | |
311 | { | |
312 | CPUState *env = opaque; | |
313 | ||
c68ea704 | 314 | cpu_reset(env); |
3d29fbef | 315 | env->halted = 1; |
c68ea704 FB |
316 | } |
317 | ||
3ebf5aaf BS |
318 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
319 | const char *kernel_cmdline, | |
320 | const char *initrd_filename) | |
321 | { | |
322 | int linux_boot; | |
323 | unsigned int i; | |
324 | long initrd_size, kernel_size; | |
325 | ||
326 | linux_boot = (kernel_filename != NULL); | |
327 | ||
328 | kernel_size = 0; | |
329 | if (linux_boot) { | |
330 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, | |
331 | NULL); | |
332 | if (kernel_size < 0) | |
333 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
334 | if (kernel_size < 0) | |
335 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
336 | if (kernel_size < 0) { | |
337 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
338 | kernel_filename); | |
339 | exit(1); | |
340 | } | |
341 | ||
342 | /* load initrd */ | |
343 | initrd_size = 0; | |
344 | if (initrd_filename) { | |
345 | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); | |
346 | if (initrd_size < 0) { | |
347 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
348 | initrd_filename); | |
349 | exit(1); | |
350 | } | |
351 | } | |
352 | if (initrd_size > 0) { | |
353 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
354 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) | |
355 | == 0x48647253) { // HdrS | |
356 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
357 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
358 | break; | |
359 | } | |
360 | } | |
361 | } | |
362 | } | |
363 | return kernel_size; | |
364 | } | |
365 | ||
366 | static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, | |
367 | const char *boot_device, | |
368 | DisplayState *ds, const char *kernel_filename, | |
369 | const char *kernel_cmdline, | |
370 | const char *initrd_filename, const char *cpu_model) | |
36cd9210 | 371 | |
420557e8 | 372 | { |
ba3c64fb | 373 | CPUState *env, *envs[MAX_CPUS]; |
713c45fa | 374 | unsigned int i; |
b3ceef24 | 375 | void *iommu, *espdma, *ledma, *main_esp, *nvram; |
b3a23197 | 376 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
d7edfd27 | 377 | *espdma_irq, *ledma_irq; |
2d069bab | 378 | qemu_irq *esp_reset, *le_reset; |
3ebf5aaf BS |
379 | unsigned long prom_offset, kernel_size; |
380 | int ret; | |
381 | char buf[1024]; | |
e4bcb14c TS |
382 | BlockDriverState *fd[MAX_FD]; |
383 | int index; | |
420557e8 | 384 | |
ba3c64fb | 385 | /* init CPUs */ |
3ebf5aaf BS |
386 | if (!cpu_model) |
387 | cpu_model = hwdef->default_cpu_model; | |
b3a23197 | 388 | |
ba3c64fb | 389 | for(i = 0; i < smp_cpus; i++) { |
aaed909a FB |
390 | env = cpu_init(cpu_model); |
391 | if (!env) { | |
8e82c6a8 | 392 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); |
aaed909a FB |
393 | exit(1); |
394 | } | |
395 | cpu_sparc_set_id(env, i); | |
ba3c64fb | 396 | envs[i] = env; |
3d29fbef BS |
397 | if (i == 0) { |
398 | qemu_register_reset(main_cpu_reset, env); | |
399 | } else { | |
400 | qemu_register_reset(secondary_cpu_reset, env); | |
ba3c64fb | 401 | env->halted = 1; |
3d29fbef | 402 | } |
ba3c64fb | 403 | register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
b3a23197 | 404 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
3ebf5aaf | 405 | env->prom_addr = hwdef->slavio_base; |
ba3c64fb | 406 | } |
b3a23197 BS |
407 | |
408 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
409 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
410 | ||
3ebf5aaf | 411 | |
420557e8 | 412 | /* allocate RAM */ |
3ebf5aaf BS |
413 | if ((uint64_t)RAM_size > hwdef->max_mem) { |
414 | fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", | |
415 | (unsigned int)RAM_size / (1024 * 1024), | |
416 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); | |
417 | exit(1); | |
418 | } | |
b3ceef24 | 419 | cpu_register_physical_memory(0, RAM_size, 0); |
420557e8 | 420 | |
3ebf5aaf BS |
421 | /* load boot prom */ |
422 | prom_offset = RAM_size + hwdef->vram_size; | |
423 | cpu_register_physical_memory(hwdef->slavio_base, | |
424 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & | |
425 | TARGET_PAGE_MASK, | |
426 | prom_offset | IO_MEM_ROM); | |
427 | ||
428 | if (bios_name == NULL) | |
429 | bios_name = PROM_FILENAME; | |
430 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
431 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); | |
432 | if (ret < 0 || ret > PROM_SIZE_MAX) | |
433 | ret = load_image(buf, phys_ram_base + prom_offset); | |
434 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
435 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
436 | buf); | |
437 | exit(1); | |
438 | } | |
4c2485de | 439 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
3ebf5aaf BS |
440 | |
441 | /* set up devices */ | |
36cd9210 | 442 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
5dcb6b91 | 443 | hwdef->intctl_base + 0x10000ULL, |
d537cf6c | 444 | &hwdef->intbit_to_level[0], |
d7edfd27 | 445 | &slavio_irq, &slavio_cpu_irq, |
b3a23197 | 446 | cpu_irqs, |
d7edfd27 | 447 | hwdef->clock_irq); |
b3a23197 | 448 | |
4c2485de BS |
449 | if (hwdef->idreg_base != (target_phys_addr_t)-1) { |
450 | stl_raw(phys_ram_base + prom_offset, 0xfe810103); | |
451 | ||
452 | cpu_register_physical_memory(hwdef->idreg_base, sizeof(uint32_t), | |
453 | prom_offset | IO_MEM_ROM); | |
454 | } | |
455 | ||
ff403da6 BS |
456 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
457 | slavio_irq[hwdef->me_irq]); | |
458 | ||
5aca8c3b | 459 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
2d069bab BS |
460 | iommu, &espdma_irq, &esp_reset); |
461 | ||
5aca8c3b | 462 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, |
2d069bab BS |
463 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
464 | &le_reset); | |
ba3c64fb | 465 | |
eee0b836 BS |
466 | if (graphic_depth != 8 && graphic_depth != 24) { |
467 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
468 | exit (1); | |
469 | } | |
b3ceef24 | 470 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
eee0b836 | 471 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
dbe06e18 BS |
472 | |
473 | if (nd_table[0].model == NULL | |
474 | || strcmp(nd_table[0].model, "lance") == 0) { | |
2d069bab | 475 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); |
c4a7060c BS |
476 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
477 | fprintf(stderr, "qemu: Supported NICs: lance\n"); | |
478 | exit (1); | |
dbe06e18 BS |
479 | } else { |
480 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
481 | exit (1); | |
a41b2ff2 | 482 | } |
dbe06e18 | 483 | |
d537cf6c PB |
484 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
485 | hwdef->nvram_size, 8); | |
81732d19 BS |
486 | |
487 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], | |
19f8e5dd | 488 | slavio_cpu_irq, smp_cpus); |
81732d19 | 489 | |
577390ff BS |
490 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
491 | nographic); | |
b81b3b10 FB |
492 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
493 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
d537cf6c PB |
494 | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
495 | serial_hds[1], serial_hds[0]); | |
741402f9 | 496 | |
e4bcb14c TS |
497 | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
498 | /* there is zero or one floppy drive */ | |
309e60bd | 499 | memset(fd, 0, sizeof(fd)); |
e4bcb14c TS |
500 | index = drive_get_index(IF_FLOPPY, 0, 0); |
501 | if (index != -1) | |
502 | fd[0] = drives_table[index].bdrv; | |
2d069bab | 503 | |
e4bcb14c TS |
504 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd); |
505 | } | |
506 | ||
507 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
508 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
509 | exit(1); | |
510 | } | |
511 | ||
8b17de88 BS |
512 | main_esp = esp_init(hwdef->esp_base, |
513 | espdma_memory_read, espdma_memory_write, | |
514 | espdma, *espdma_irq, esp_reset); | |
f1587550 | 515 | |
e4bcb14c TS |
516 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
517 | index = drive_get_index(IF_SCSI, 0, i); | |
518 | if (index == -1) | |
519 | continue; | |
520 | esp_scsi_attach(main_esp, drives_table[index].bdrv, i); | |
f1587550 TS |
521 | } |
522 | ||
0019ad53 BS |
523 | slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base, |
524 | hwdef->aux1_base, hwdef->aux2_base, | |
525 | slavio_irq[hwdef->me_irq], envs[0]); | |
5dcb6b91 | 526 | if (hwdef->cs_base != (target_phys_addr_t)-1) |
803b3c7b | 527 | cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
b3ceef24 | 528 | |
3ebf5aaf BS |
529 | kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, |
530 | initrd_filename); | |
36cd9210 | 531 | |
36cd9210 | 532 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, |
b3ceef24 | 533 | boot_device, RAM_size, kernel_size, graphic_width, |
7d85892b | 534 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4m"); |
7eb0c8e8 BS |
535 | |
536 | if (hwdef->ecc_base != (target_phys_addr_t)-1) | |
e42c20b4 BS |
537 | ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq], |
538 | hwdef->ecc_version); | |
36cd9210 BS |
539 | } |
540 | ||
ee76f82e BS |
541 | static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size, |
542 | const char *boot_device, | |
543 | DisplayState *ds, const char *kernel_filename, | |
544 | const char *kernel_cmdline, | |
545 | const char *initrd_filename, const char *cpu_model) | |
546 | { | |
547 | CPUState *env; | |
548 | unsigned int i; | |
549 | void *iommu, *espdma, *ledma, *main_esp, *nvram; | |
550 | qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; | |
551 | qemu_irq *esp_reset, *le_reset; | |
552 | unsigned long prom_offset, kernel_size; | |
553 | int ret; | |
554 | char buf[1024]; | |
555 | BlockDriverState *fd[MAX_FD]; | |
556 | int index; | |
557 | ||
558 | /* init CPU */ | |
559 | if (!cpu_model) | |
560 | cpu_model = hwdef->default_cpu_model; | |
561 | ||
562 | env = cpu_init(cpu_model); | |
563 | if (!env) { | |
8e82c6a8 | 564 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); |
ee76f82e BS |
565 | exit(1); |
566 | } | |
567 | ||
568 | cpu_sparc_set_id(env, 0); | |
569 | ||
570 | qemu_register_reset(main_cpu_reset, env); | |
571 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | |
572 | cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | |
cebb73aa | 573 | env->prom_addr = hwdef->slavio_base; |
ee76f82e BS |
574 | |
575 | /* allocate RAM */ | |
576 | if ((uint64_t)RAM_size > hwdef->max_mem) { | |
577 | fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", | |
578 | (unsigned int)RAM_size / (1024 * 1024), | |
579 | (unsigned int)hwdef->max_mem / (1024 * 1024)); | |
580 | exit(1); | |
581 | } | |
582 | cpu_register_physical_memory(0, RAM_size, 0); | |
583 | ||
584 | /* load boot prom */ | |
585 | prom_offset = RAM_size + hwdef->vram_size; | |
586 | cpu_register_physical_memory(hwdef->slavio_base, | |
587 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & | |
588 | TARGET_PAGE_MASK, | |
589 | prom_offset | IO_MEM_ROM); | |
590 | ||
591 | if (bios_name == NULL) | |
592 | bios_name = PROM_FILENAME; | |
593 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
594 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); | |
595 | if (ret < 0 || ret > PROM_SIZE_MAX) | |
596 | ret = load_image(buf, phys_ram_base + prom_offset); | |
597 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
598 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
599 | buf); | |
600 | exit(1); | |
601 | } | |
602 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; | |
603 | ||
604 | /* set up devices */ | |
605 | slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base, | |
606 | &slavio_irq, cpu_irqs); | |
607 | ||
ff403da6 BS |
608 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
609 | slavio_irq[hwdef->me_irq]); | |
ee76f82e BS |
610 | |
611 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], | |
612 | iommu, &espdma_irq, &esp_reset); | |
613 | ||
614 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, | |
615 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, | |
616 | &le_reset); | |
617 | ||
618 | if (graphic_depth != 8 && graphic_depth != 24) { | |
619 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
620 | exit (1); | |
621 | } | |
622 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, | |
623 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); | |
624 | ||
625 | if (nd_table[0].model == NULL | |
626 | || strcmp(nd_table[0].model, "lance") == 0) { | |
627 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); | |
628 | } else if (strcmp(nd_table[0].model, "?") == 0) { | |
629 | fprintf(stderr, "qemu: Supported NICs: lance\n"); | |
630 | exit (1); | |
631 | } else { | |
632 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
633 | exit (1); | |
634 | } | |
635 | ||
636 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, | |
4aed2c33 | 637 | hwdef->nvram_size, 2); |
ee76f82e BS |
638 | |
639 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], | |
640 | nographic); | |
641 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device | |
642 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
643 | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], | |
644 | serial_hds[1], serial_hds[0]); | |
645 | ||
646 | if (hwdef->fd_base != (target_phys_addr_t)-1) { | |
647 | /* there is zero or one floppy drive */ | |
648 | fd[1] = fd[0] = NULL; | |
649 | index = drive_get_index(IF_FLOPPY, 0, 0); | |
650 | if (index != -1) | |
651 | fd[0] = drives_table[index].bdrv; | |
652 | ||
653 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd); | |
654 | } | |
655 | ||
656 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
657 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
658 | exit(1); | |
659 | } | |
660 | ||
8b17de88 BS |
661 | main_esp = esp_init(hwdef->esp_base, |
662 | espdma_memory_read, espdma_memory_write, | |
663 | espdma, *espdma_irq, esp_reset); | |
ee76f82e BS |
664 | |
665 | for (i = 0; i < ESP_MAX_DEVS; i++) { | |
666 | index = drive_get_index(IF_SCSI, 0, i); | |
667 | if (index == -1) | |
668 | continue; | |
669 | esp_scsi_attach(main_esp, drives_table[index].bdrv, i); | |
670 | } | |
671 | ||
0019ad53 BS |
672 | slavio_misc = slavio_misc_init(-1, hwdef->apc_base, |
673 | hwdef->aux1_base, hwdef->aux2_base, | |
674 | slavio_irq[hwdef->me_irq], env); | |
675 | ||
ee76f82e BS |
676 | kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, |
677 | initrd_filename); | |
678 | ||
679 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, | |
680 | boot_device, RAM_size, kernel_size, graphic_width, | |
681 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4c"); | |
682 | } | |
683 | ||
36cd9210 BS |
684 | static const struct hwdef hwdefs[] = { |
685 | /* SS-5 */ | |
686 | { | |
687 | .iommu_base = 0x10000000, | |
688 | .tcx_base = 0x50000000, | |
689 | .cs_base = 0x6c000000, | |
384ccb5d | 690 | .slavio_base = 0x70000000, |
36cd9210 BS |
691 | .ms_kb_base = 0x71000000, |
692 | .serial_base = 0x71100000, | |
693 | .nvram_base = 0x71200000, | |
694 | .fd_base = 0x71400000, | |
695 | .counter_base = 0x71d00000, | |
696 | .intctl_base = 0x71e00000, | |
4c2485de | 697 | .idreg_base = 0x78000000, |
36cd9210 BS |
698 | .dma_base = 0x78400000, |
699 | .esp_base = 0x78800000, | |
700 | .le_base = 0x78c00000, | |
127fc407 | 701 | .apc_base = 0x6a000000, |
0019ad53 BS |
702 | .aux1_base = 0x71900000, |
703 | .aux2_base = 0x71910000, | |
7eb0c8e8 | 704 | .ecc_base = -1, |
ee76f82e BS |
705 | .sun4c_intctl_base = -1, |
706 | .sun4c_counter_base = -1, | |
36cd9210 BS |
707 | .vram_size = 0x00100000, |
708 | .nvram_size = 0x2000, | |
709 | .esp_irq = 18, | |
710 | .le_irq = 16, | |
e3a79bca | 711 | .clock_irq = 7, |
36cd9210 BS |
712 | .clock1_irq = 19, |
713 | .ms_kb_irq = 14, | |
714 | .ser_irq = 15, | |
715 | .fd_irq = 22, | |
716 | .me_irq = 30, | |
717 | .cs_irq = 5, | |
718 | .machine_id = 0x80, | |
cf3102ac | 719 | .iommu_version = 0x05000000, |
e0353fe2 | 720 | .intbit_to_level = { |
f930d07e BS |
721 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
722 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
e0353fe2 | 723 | }, |
3ebf5aaf BS |
724 | .max_mem = 0x10000000, |
725 | .default_cpu_model = "Fujitsu MB86904", | |
e0353fe2 BS |
726 | }, |
727 | /* SS-10 */ | |
e0353fe2 | 728 | { |
5dcb6b91 BS |
729 | .iommu_base = 0xfe0000000ULL, |
730 | .tcx_base = 0xe20000000ULL, | |
803b3c7b | 731 | .cs_base = -1, |
5dcb6b91 BS |
732 | .slavio_base = 0xff0000000ULL, |
733 | .ms_kb_base = 0xff1000000ULL, | |
734 | .serial_base = 0xff1100000ULL, | |
735 | .nvram_base = 0xff1200000ULL, | |
736 | .fd_base = 0xff1700000ULL, | |
737 | .counter_base = 0xff1300000ULL, | |
738 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 739 | .idreg_base = 0xef0000000ULL, |
5dcb6b91 BS |
740 | .dma_base = 0xef0400000ULL, |
741 | .esp_base = 0xef0800000ULL, | |
742 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 743 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
744 | .aux1_base = 0xff1800000ULL, |
745 | .aux2_base = 0xff1a01000ULL, | |
7eb0c8e8 BS |
746 | .ecc_base = 0xf00000000ULL, |
747 | .ecc_version = 0x10000000, // version 0, implementation 1 | |
ee76f82e BS |
748 | .sun4c_intctl_base = -1, |
749 | .sun4c_counter_base = -1, | |
e0353fe2 BS |
750 | .vram_size = 0x00100000, |
751 | .nvram_size = 0x2000, | |
752 | .esp_irq = 18, | |
753 | .le_irq = 16, | |
e3a79bca | 754 | .clock_irq = 7, |
e0353fe2 BS |
755 | .clock1_irq = 19, |
756 | .ms_kb_irq = 14, | |
757 | .ser_irq = 15, | |
758 | .fd_irq = 22, | |
759 | .me_irq = 30, | |
803b3c7b | 760 | .cs_irq = -1, |
e42c20b4 | 761 | .ecc_irq = 28, |
803b3c7b | 762 | .machine_id = 0x72, |
7fbfb139 | 763 | .iommu_version = 0x03000000, |
e0353fe2 | 764 | .intbit_to_level = { |
f930d07e BS |
765 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
766 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
e0353fe2 | 767 | }, |
3ebf5aaf BS |
768 | .max_mem = 0xffffffff, // XXX actually first 62GB ok |
769 | .default_cpu_model = "TI SuperSparc II", | |
36cd9210 | 770 | }, |
6a3b9cc9 BS |
771 | /* SS-600MP */ |
772 | { | |
773 | .iommu_base = 0xfe0000000ULL, | |
774 | .tcx_base = 0xe20000000ULL, | |
775 | .cs_base = -1, | |
776 | .slavio_base = 0xff0000000ULL, | |
777 | .ms_kb_base = 0xff1000000ULL, | |
778 | .serial_base = 0xff1100000ULL, | |
779 | .nvram_base = 0xff1200000ULL, | |
780 | .fd_base = -1, | |
781 | .counter_base = 0xff1300000ULL, | |
782 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 783 | .idreg_base = -1, |
6a3b9cc9 BS |
784 | .dma_base = 0xef0081000ULL, |
785 | .esp_base = 0xef0080000ULL, | |
786 | .le_base = 0xef0060000ULL, | |
0019ad53 | 787 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
788 | .aux1_base = 0xff1800000ULL, |
789 | .aux2_base = 0xff1a01000ULL, // XXX should not exist | |
7eb0c8e8 BS |
790 | .ecc_base = 0xf00000000ULL, |
791 | .ecc_version = 0x00000000, // version 0, implementation 0 | |
ee76f82e BS |
792 | .sun4c_intctl_base = -1, |
793 | .sun4c_counter_base = -1, | |
6a3b9cc9 BS |
794 | .vram_size = 0x00100000, |
795 | .nvram_size = 0x2000, | |
796 | .esp_irq = 18, | |
797 | .le_irq = 16, | |
e3a79bca | 798 | .clock_irq = 7, |
6a3b9cc9 BS |
799 | .clock1_irq = 19, |
800 | .ms_kb_irq = 14, | |
801 | .ser_irq = 15, | |
802 | .fd_irq = 22, | |
803 | .me_irq = 30, | |
804 | .cs_irq = -1, | |
e42c20b4 | 805 | .ecc_irq = 28, |
6a3b9cc9 | 806 | .machine_id = 0x71, |
7fbfb139 | 807 | .iommu_version = 0x01000000, |
6a3b9cc9 BS |
808 | .intbit_to_level = { |
809 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
810 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
811 | }, | |
3ebf5aaf BS |
812 | .max_mem = 0xffffffff, // XXX actually first 62GB ok |
813 | .default_cpu_model = "TI SuperSparc II", | |
6a3b9cc9 | 814 | }, |
ae40972f BS |
815 | /* SS-20 */ |
816 | { | |
817 | .iommu_base = 0xfe0000000ULL, | |
818 | .tcx_base = 0xe20000000ULL, | |
819 | .cs_base = -1, | |
820 | .slavio_base = 0xff0000000ULL, | |
821 | .ms_kb_base = 0xff1000000ULL, | |
822 | .serial_base = 0xff1100000ULL, | |
823 | .nvram_base = 0xff1200000ULL, | |
824 | .fd_base = 0xff1700000ULL, | |
825 | .counter_base = 0xff1300000ULL, | |
826 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 827 | .idreg_base = 0xef0000000ULL, |
ae40972f BS |
828 | .dma_base = 0xef0400000ULL, |
829 | .esp_base = 0xef0800000ULL, | |
830 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 831 | .apc_base = 0xefa000000ULL, // XXX should not exist |
577d8dd4 BS |
832 | .aux1_base = 0xff1800000ULL, |
833 | .aux2_base = 0xff1a01000ULL, | |
ae40972f BS |
834 | .ecc_base = 0xf00000000ULL, |
835 | .ecc_version = 0x20000000, // version 0, implementation 2 | |
ee76f82e BS |
836 | .sun4c_intctl_base = -1, |
837 | .sun4c_counter_base = -1, | |
ae40972f BS |
838 | .vram_size = 0x00100000, |
839 | .nvram_size = 0x2000, | |
840 | .esp_irq = 18, | |
841 | .le_irq = 16, | |
e3a79bca | 842 | .clock_irq = 7, |
ae40972f BS |
843 | .clock1_irq = 19, |
844 | .ms_kb_irq = 14, | |
845 | .ser_irq = 15, | |
846 | .fd_irq = 22, | |
847 | .me_irq = 30, | |
848 | .cs_irq = -1, | |
e42c20b4 | 849 | .ecc_irq = 28, |
ae40972f BS |
850 | .machine_id = 0x72, |
851 | .iommu_version = 0x13000000, | |
852 | .intbit_to_level = { | |
853 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
854 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
855 | }, | |
856 | .max_mem = 0xffffffff, // XXX actually first 62GB ok | |
857 | .default_cpu_model = "TI SuperSparc II", | |
858 | }, | |
ee76f82e BS |
859 | /* SS-2 */ |
860 | { | |
861 | .iommu_base = 0xf8000000, | |
862 | .tcx_base = 0xfe000000, | |
863 | .cs_base = -1, | |
864 | .slavio_base = 0xf6000000, | |
865 | .ms_kb_base = 0xf0000000, | |
866 | .serial_base = 0xf1000000, | |
867 | .nvram_base = 0xf2000000, | |
868 | .fd_base = 0xf7200000, | |
869 | .counter_base = -1, | |
870 | .intctl_base = -1, | |
871 | .dma_base = 0xf8400000, | |
872 | .esp_base = 0xf8800000, | |
873 | .le_base = 0xf8c00000, | |
0019ad53 BS |
874 | .apc_base = -1, |
875 | .aux1_base = 0xf7400003, | |
876 | .aux2_base = -1, | |
ee76f82e BS |
877 | .sun4c_intctl_base = 0xf5000000, |
878 | .sun4c_counter_base = 0xf3000000, | |
879 | .vram_size = 0x00100000, | |
4aed2c33 | 880 | .nvram_size = 0x800, |
ee76f82e BS |
881 | .esp_irq = 2, |
882 | .le_irq = 3, | |
883 | .clock_irq = 5, | |
884 | .clock1_irq = 7, | |
885 | .ms_kb_irq = 1, | |
886 | .ser_irq = 1, | |
887 | .fd_irq = 1, | |
888 | .me_irq = 1, | |
889 | .cs_irq = -1, | |
890 | .machine_id = 0x55, | |
891 | .max_mem = 0x10000000, | |
892 | .default_cpu_model = "Cypress CY7C601", | |
893 | }, | |
a526a31c BS |
894 | /* Voyager */ |
895 | { | |
896 | .iommu_base = 0x10000000, | |
897 | .tcx_base = 0x50000000, | |
898 | .cs_base = -1, | |
899 | .slavio_base = 0x70000000, | |
900 | .ms_kb_base = 0x71000000, | |
901 | .serial_base = 0x71100000, | |
902 | .nvram_base = 0x71200000, | |
903 | .fd_base = 0x71400000, | |
904 | .counter_base = 0x71d00000, | |
905 | .intctl_base = 0x71e00000, | |
906 | .idreg_base = 0x78000000, | |
907 | .dma_base = 0x78400000, | |
908 | .esp_base = 0x78800000, | |
909 | .le_base = 0x78c00000, | |
910 | .apc_base = 0x71300000, // pmc | |
911 | .aux1_base = 0x71900000, | |
912 | .aux2_base = 0x71910000, | |
913 | .ecc_base = -1, | |
914 | .sun4c_intctl_base = -1, | |
915 | .sun4c_counter_base = -1, | |
916 | .vram_size = 0x00100000, | |
917 | .nvram_size = 0x2000, | |
918 | .esp_irq = 18, | |
919 | .le_irq = 16, | |
920 | .clock_irq = 7, | |
921 | .clock1_irq = 19, | |
922 | .ms_kb_irq = 14, | |
923 | .ser_irq = 15, | |
924 | .fd_irq = 22, | |
925 | .me_irq = 30, | |
926 | .cs_irq = -1, | |
927 | .machine_id = 0x80, | |
928 | .iommu_version = 0x05000000, | |
929 | .intbit_to_level = { | |
930 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
931 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
932 | }, | |
933 | .max_mem = 0x10000000, | |
934 | .default_cpu_model = "Fujitsu MB86904", | |
935 | }, | |
936 | /* LX */ | |
937 | { | |
938 | .iommu_base = 0x10000000, | |
939 | .tcx_base = 0x50000000, | |
940 | .cs_base = -1, | |
941 | .slavio_base = 0x70000000, | |
942 | .ms_kb_base = 0x71000000, | |
943 | .serial_base = 0x71100000, | |
944 | .nvram_base = 0x71200000, | |
945 | .fd_base = 0x71400000, | |
946 | .counter_base = 0x71d00000, | |
947 | .intctl_base = 0x71e00000, | |
948 | .idreg_base = 0x78000000, | |
949 | .dma_base = 0x78400000, | |
950 | .esp_base = 0x78800000, | |
951 | .le_base = 0x78c00000, | |
952 | .apc_base = -1, | |
953 | .aux1_base = 0x71900000, | |
954 | .aux2_base = 0x71910000, | |
955 | .ecc_base = -1, | |
956 | .sun4c_intctl_base = -1, | |
957 | .sun4c_counter_base = -1, | |
958 | .vram_size = 0x00100000, | |
959 | .nvram_size = 0x2000, | |
960 | .esp_irq = 18, | |
961 | .le_irq = 16, | |
962 | .clock_irq = 7, | |
963 | .clock1_irq = 19, | |
964 | .ms_kb_irq = 14, | |
965 | .ser_irq = 15, | |
966 | .fd_irq = 22, | |
967 | .me_irq = 30, | |
968 | .cs_irq = -1, | |
969 | .machine_id = 0x80, | |
970 | .iommu_version = 0x04000000, | |
971 | .intbit_to_level = { | |
972 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
973 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
974 | }, | |
975 | .max_mem = 0x10000000, | |
976 | .default_cpu_model = "TI MicroSparc I", | |
977 | }, | |
978 | /* SS-4 */ | |
979 | { | |
980 | .iommu_base = 0x10000000, | |
981 | .tcx_base = 0x50000000, | |
982 | .cs_base = 0x6c000000, | |
983 | .slavio_base = 0x70000000, | |
984 | .ms_kb_base = 0x71000000, | |
985 | .serial_base = 0x71100000, | |
986 | .nvram_base = 0x71200000, | |
987 | .fd_base = 0x71400000, | |
988 | .counter_base = 0x71d00000, | |
989 | .intctl_base = 0x71e00000, | |
990 | .idreg_base = 0x78000000, | |
991 | .dma_base = 0x78400000, | |
992 | .esp_base = 0x78800000, | |
993 | .le_base = 0x78c00000, | |
994 | .apc_base = 0x6a000000, | |
995 | .aux1_base = 0x71900000, | |
996 | .aux2_base = 0x71910000, | |
997 | .ecc_base = -1, | |
998 | .sun4c_intctl_base = -1, | |
999 | .sun4c_counter_base = -1, | |
1000 | .vram_size = 0x00100000, | |
1001 | .nvram_size = 0x2000, | |
1002 | .esp_irq = 18, | |
1003 | .le_irq = 16, | |
1004 | .clock_irq = 7, | |
1005 | .clock1_irq = 19, | |
1006 | .ms_kb_irq = 14, | |
1007 | .ser_irq = 15, | |
1008 | .fd_irq = 22, | |
1009 | .me_irq = 30, | |
1010 | .cs_irq = 5, | |
1011 | .machine_id = 0x80, | |
1012 | .iommu_version = 0x05000000, | |
1013 | .intbit_to_level = { | |
1014 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1015 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1016 | }, | |
1017 | .max_mem = 0x10000000, | |
1018 | .default_cpu_model = "Fujitsu MB86904", | |
1019 | }, | |
1020 | /* SPARCClassic */ | |
1021 | { | |
1022 | .iommu_base = 0x10000000, | |
1023 | .tcx_base = 0x50000000, | |
1024 | .cs_base = -1, | |
1025 | .slavio_base = 0x70000000, | |
1026 | .ms_kb_base = 0x71000000, | |
1027 | .serial_base = 0x71100000, | |
1028 | .nvram_base = 0x71200000, | |
1029 | .fd_base = 0x71400000, | |
1030 | .counter_base = 0x71d00000, | |
1031 | .intctl_base = 0x71e00000, | |
1032 | .idreg_base = 0x78000000, | |
1033 | .dma_base = 0x78400000, | |
1034 | .esp_base = 0x78800000, | |
1035 | .le_base = 0x78c00000, | |
1036 | .apc_base = 0x6a000000, | |
1037 | .aux1_base = 0x71900000, | |
1038 | .aux2_base = 0x71910000, | |
1039 | .ecc_base = -1, | |
1040 | .sun4c_intctl_base = -1, | |
1041 | .sun4c_counter_base = -1, | |
1042 | .vram_size = 0x00100000, | |
1043 | .nvram_size = 0x2000, | |
1044 | .esp_irq = 18, | |
1045 | .le_irq = 16, | |
1046 | .clock_irq = 7, | |
1047 | .clock1_irq = 19, | |
1048 | .ms_kb_irq = 14, | |
1049 | .ser_irq = 15, | |
1050 | .fd_irq = 22, | |
1051 | .me_irq = 30, | |
1052 | .cs_irq = -1, | |
1053 | .machine_id = 0x80, | |
1054 | .iommu_version = 0x05000000, | |
1055 | .intbit_to_level = { | |
1056 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1057 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1058 | }, | |
1059 | .max_mem = 0x10000000, | |
1060 | .default_cpu_model = "TI MicroSparc I", | |
1061 | }, | |
1062 | /* SPARCbook */ | |
1063 | { | |
1064 | .iommu_base = 0x10000000, | |
1065 | .tcx_base = 0x50000000, // XXX | |
1066 | .cs_base = -1, | |
1067 | .slavio_base = 0x70000000, | |
1068 | .ms_kb_base = 0x71000000, | |
1069 | .serial_base = 0x71100000, | |
1070 | .nvram_base = 0x71200000, | |
1071 | .fd_base = 0x71400000, | |
1072 | .counter_base = 0x71d00000, | |
1073 | .intctl_base = 0x71e00000, | |
1074 | .idreg_base = 0x78000000, | |
1075 | .dma_base = 0x78400000, | |
1076 | .esp_base = 0x78800000, | |
1077 | .le_base = 0x78c00000, | |
1078 | .apc_base = 0x6a000000, | |
1079 | .aux1_base = 0x71900000, | |
1080 | .aux2_base = 0x71910000, | |
1081 | .ecc_base = -1, | |
1082 | .sun4c_intctl_base = -1, | |
1083 | .sun4c_counter_base = -1, | |
1084 | .vram_size = 0x00100000, | |
1085 | .nvram_size = 0x2000, | |
1086 | .esp_irq = 18, | |
1087 | .le_irq = 16, | |
1088 | .clock_irq = 7, | |
1089 | .clock1_irq = 19, | |
1090 | .ms_kb_irq = 14, | |
1091 | .ser_irq = 15, | |
1092 | .fd_irq = 22, | |
1093 | .me_irq = 30, | |
1094 | .cs_irq = -1, | |
1095 | .machine_id = 0x80, | |
1096 | .iommu_version = 0x05000000, | |
1097 | .intbit_to_level = { | |
1098 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
1099 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
1100 | }, | |
1101 | .max_mem = 0x10000000, | |
1102 | .default_cpu_model = "TI MicroSparc I", | |
1103 | }, | |
36cd9210 BS |
1104 | }; |
1105 | ||
36cd9210 | 1106 | /* SPARCstation 5 hardware initialisation */ |
b881c2c6 BS |
1107 | static void ss5_init(int RAM_size, int vga_ram_size, |
1108 | const char *boot_device, DisplayState *ds, | |
1109 | const char *kernel_filename, const char *kernel_cmdline, | |
1110 | const char *initrd_filename, const char *cpu_model) | |
36cd9210 | 1111 | { |
3ebf5aaf BS |
1112 | sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename, |
1113 | kernel_cmdline, initrd_filename, cpu_model); | |
420557e8 | 1114 | } |
c0e564d5 | 1115 | |
e0353fe2 | 1116 | /* SPARCstation 10 hardware initialisation */ |
b881c2c6 BS |
1117 | static void ss10_init(int RAM_size, int vga_ram_size, |
1118 | const char *boot_device, DisplayState *ds, | |
1119 | const char *kernel_filename, const char *kernel_cmdline, | |
1120 | const char *initrd_filename, const char *cpu_model) | |
e0353fe2 | 1121 | { |
3ebf5aaf BS |
1122 | sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename, |
1123 | kernel_cmdline, initrd_filename, cpu_model); | |
e0353fe2 BS |
1124 | } |
1125 | ||
6a3b9cc9 | 1126 | /* SPARCserver 600MP hardware initialisation */ |
b881c2c6 BS |
1127 | static void ss600mp_init(int RAM_size, int vga_ram_size, |
1128 | const char *boot_device, DisplayState *ds, | |
6a3b9cc9 BS |
1129 | const char *kernel_filename, const char *kernel_cmdline, |
1130 | const char *initrd_filename, const char *cpu_model) | |
1131 | { | |
3ebf5aaf BS |
1132 | sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename, |
1133 | kernel_cmdline, initrd_filename, cpu_model); | |
6a3b9cc9 BS |
1134 | } |
1135 | ||
ae40972f BS |
1136 | /* SPARCstation 20 hardware initialisation */ |
1137 | static void ss20_init(int RAM_size, int vga_ram_size, | |
1138 | const char *boot_device, DisplayState *ds, | |
1139 | const char *kernel_filename, const char *kernel_cmdline, | |
1140 | const char *initrd_filename, const char *cpu_model) | |
1141 | { | |
1142 | sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename, | |
1143 | kernel_cmdline, initrd_filename, cpu_model); | |
1144 | } | |
1145 | ||
ee76f82e BS |
1146 | /* SPARCstation 2 hardware initialisation */ |
1147 | static void ss2_init(int RAM_size, int vga_ram_size, | |
1148 | const char *boot_device, DisplayState *ds, | |
1149 | const char *kernel_filename, const char *kernel_cmdline, | |
1150 | const char *initrd_filename, const char *cpu_model) | |
1151 | { | |
1152 | sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename, | |
1153 | kernel_cmdline, initrd_filename, cpu_model); | |
1154 | } | |
1155 | ||
a526a31c BS |
1156 | /* SPARCstation Voyager hardware initialisation */ |
1157 | static void vger_init(int RAM_size, int vga_ram_size, | |
1158 | const char *boot_device, DisplayState *ds, | |
1159 | const char *kernel_filename, const char *kernel_cmdline, | |
1160 | const char *initrd_filename, const char *cpu_model) | |
1161 | { | |
1162 | sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename, | |
1163 | kernel_cmdline, initrd_filename, cpu_model); | |
1164 | } | |
1165 | ||
1166 | /* SPARCstation LX hardware initialisation */ | |
1167 | static void ss_lx_init(int RAM_size, int vga_ram_size, | |
1168 | const char *boot_device, DisplayState *ds, | |
1169 | const char *kernel_filename, const char *kernel_cmdline, | |
1170 | const char *initrd_filename, const char *cpu_model) | |
1171 | { | |
1172 | sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename, | |
1173 | kernel_cmdline, initrd_filename, cpu_model); | |
1174 | } | |
1175 | ||
1176 | /* SPARCstation 4 hardware initialisation */ | |
1177 | static void ss4_init(int RAM_size, int vga_ram_size, | |
1178 | const char *boot_device, DisplayState *ds, | |
1179 | const char *kernel_filename, const char *kernel_cmdline, | |
1180 | const char *initrd_filename, const char *cpu_model) | |
1181 | { | |
1182 | sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename, | |
1183 | kernel_cmdline, initrd_filename, cpu_model); | |
1184 | } | |
1185 | ||
1186 | /* SPARCClassic hardware initialisation */ | |
1187 | static void scls_init(int RAM_size, int vga_ram_size, | |
1188 | const char *boot_device, DisplayState *ds, | |
1189 | const char *kernel_filename, const char *kernel_cmdline, | |
1190 | const char *initrd_filename, const char *cpu_model) | |
1191 | { | |
1192 | sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename, | |
1193 | kernel_cmdline, initrd_filename, cpu_model); | |
1194 | } | |
1195 | ||
1196 | /* SPARCbook hardware initialisation */ | |
1197 | static void sbook_init(int RAM_size, int vga_ram_size, | |
1198 | const char *boot_device, DisplayState *ds, | |
1199 | const char *kernel_filename, const char *kernel_cmdline, | |
1200 | const char *initrd_filename, const char *cpu_model) | |
1201 | { | |
1202 | sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename, | |
1203 | kernel_cmdline, initrd_filename, cpu_model); | |
1204 | } | |
1205 | ||
36cd9210 BS |
1206 | QEMUMachine ss5_machine = { |
1207 | "SS-5", | |
1208 | "Sun4m platform, SPARCstation 5", | |
1209 | ss5_init, | |
c0e564d5 | 1210 | }; |
e0353fe2 BS |
1211 | |
1212 | QEMUMachine ss10_machine = { | |
1213 | "SS-10", | |
1214 | "Sun4m platform, SPARCstation 10", | |
1215 | ss10_init, | |
1216 | }; | |
6a3b9cc9 BS |
1217 | |
1218 | QEMUMachine ss600mp_machine = { | |
1219 | "SS-600MP", | |
1220 | "Sun4m platform, SPARCserver 600MP", | |
1221 | ss600mp_init, | |
1222 | }; | |
ae40972f BS |
1223 | |
1224 | QEMUMachine ss20_machine = { | |
1225 | "SS-20", | |
1226 | "Sun4m platform, SPARCstation 20", | |
1227 | ss20_init, | |
1228 | }; | |
1229 | ||
ee76f82e BS |
1230 | QEMUMachine ss2_machine = { |
1231 | "SS-2", | |
1232 | "Sun4c platform, SPARCstation 2", | |
1233 | ss2_init, | |
1234 | }; | |
7d85892b | 1235 | |
a526a31c BS |
1236 | QEMUMachine voyager_machine = { |
1237 | "Voyager", | |
1238 | "Sun4m platform, SPARCstation Voyager", | |
1239 | vger_init, | |
1240 | }; | |
1241 | ||
1242 | QEMUMachine ss_lx_machine = { | |
1243 | "LX", | |
1244 | "Sun4m platform, SPARCstation LX", | |
1245 | ss_lx_init, | |
1246 | }; | |
1247 | ||
1248 | QEMUMachine ss4_machine = { | |
1249 | "SS-4", | |
1250 | "Sun4m platform, SPARCstation 4", | |
1251 | ss4_init, | |
1252 | }; | |
1253 | ||
1254 | QEMUMachine scls_machine = { | |
1255 | "SPARCClassic", | |
1256 | "Sun4m platform, SPARCClassic", | |
1257 | scls_init, | |
1258 | }; | |
1259 | ||
1260 | QEMUMachine sbook_machine = { | |
1261 | "SPARCbook", | |
1262 | "Sun4m platform, SPARCbook", | |
1263 | sbook_init, | |
1264 | }; | |
1265 | ||
7d85892b BS |
1266 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1267 | /* SS-1000 */ | |
1268 | { | |
1269 | .iounit_bases = { | |
1270 | 0xfe0200000ULL, | |
1271 | 0xfe1200000ULL, | |
1272 | 0xfe2200000ULL, | |
1273 | 0xfe3200000ULL, | |
1274 | -1, | |
1275 | }, | |
1276 | .tcx_base = 0x820000000ULL, | |
1277 | .slavio_base = 0xf00000000ULL, | |
1278 | .ms_kb_base = 0xf00240000ULL, | |
1279 | .serial_base = 0xf00200000ULL, | |
1280 | .nvram_base = 0xf00280000ULL, | |
1281 | .counter_base = 0xf00300000ULL, | |
1282 | .espdma_base = 0x800081000ULL, | |
1283 | .esp_base = 0x800080000ULL, | |
1284 | .ledma_base = 0x800040000ULL, | |
1285 | .le_base = 0x800060000ULL, | |
1286 | .sbi_base = 0xf02800000ULL, | |
1287 | .vram_size = 0x00100000, | |
1288 | .nvram_size = 0x2000, | |
1289 | .esp_irq = 3, | |
1290 | .le_irq = 4, | |
1291 | .clock_irq = 14, | |
1292 | .clock1_irq = 10, | |
1293 | .ms_kb_irq = 12, | |
1294 | .ser_irq = 12, | |
1295 | .machine_id = 0x80, | |
1296 | .iounit_version = 0x03000000, | |
1297 | .max_mem = 0xffffffff, // XXX actually first 62GB ok | |
1298 | .default_cpu_model = "TI SuperSparc II", | |
1299 | }, | |
1300 | /* SS-2000 */ | |
1301 | { | |
1302 | .iounit_bases = { | |
1303 | 0xfe0200000ULL, | |
1304 | 0xfe1200000ULL, | |
1305 | 0xfe2200000ULL, | |
1306 | 0xfe3200000ULL, | |
1307 | 0xfe4200000ULL, | |
1308 | }, | |
1309 | .tcx_base = 0x820000000ULL, | |
1310 | .slavio_base = 0xf00000000ULL, | |
1311 | .ms_kb_base = 0xf00240000ULL, | |
1312 | .serial_base = 0xf00200000ULL, | |
1313 | .nvram_base = 0xf00280000ULL, | |
1314 | .counter_base = 0xf00300000ULL, | |
1315 | .espdma_base = 0x800081000ULL, | |
1316 | .esp_base = 0x800080000ULL, | |
1317 | .ledma_base = 0x800040000ULL, | |
1318 | .le_base = 0x800060000ULL, | |
1319 | .sbi_base = 0xf02800000ULL, | |
1320 | .vram_size = 0x00100000, | |
1321 | .nvram_size = 0x2000, | |
1322 | .esp_irq = 3, | |
1323 | .le_irq = 4, | |
1324 | .clock_irq = 14, | |
1325 | .clock1_irq = 10, | |
1326 | .ms_kb_irq = 12, | |
1327 | .ser_irq = 12, | |
1328 | .machine_id = 0x80, | |
1329 | .iounit_version = 0x03000000, | |
1330 | .max_mem = 0xffffffff, // XXX actually first 62GB ok | |
1331 | .default_cpu_model = "TI SuperSparc II", | |
1332 | }, | |
1333 | }; | |
1334 | ||
1335 | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size, | |
1336 | const char *boot_device, | |
1337 | DisplayState *ds, const char *kernel_filename, | |
1338 | const char *kernel_cmdline, | |
1339 | const char *initrd_filename, const char *cpu_model) | |
1340 | { | |
1341 | CPUState *env, *envs[MAX_CPUS]; | |
1342 | unsigned int i; | |
1343 | void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi; | |
1344 | qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, | |
1345 | *espdma_irq, *ledma_irq; | |
1346 | qemu_irq *esp_reset, *le_reset; | |
1347 | unsigned long prom_offset, kernel_size; | |
1348 | int ret; | |
1349 | char buf[1024]; | |
1350 | int index; | |
1351 | ||
1352 | /* init CPUs */ | |
1353 | if (!cpu_model) | |
1354 | cpu_model = hwdef->default_cpu_model; | |
1355 | ||
1356 | for (i = 0; i < smp_cpus; i++) { | |
1357 | env = cpu_init(cpu_model); | |
1358 | if (!env) { | |
8e82c6a8 | 1359 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); |
7d85892b BS |
1360 | exit(1); |
1361 | } | |
1362 | cpu_sparc_set_id(env, i); | |
1363 | envs[i] = env; | |
1364 | if (i == 0) { | |
1365 | qemu_register_reset(main_cpu_reset, env); | |
1366 | } else { | |
1367 | qemu_register_reset(secondary_cpu_reset, env); | |
1368 | env->halted = 1; | |
1369 | } | |
1370 | register_savevm("cpu", i, 3, cpu_save, cpu_load, env); | |
1371 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); | |
1372 | env->prom_addr = hwdef->slavio_base; | |
1373 | } | |
1374 | ||
1375 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
1376 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
1377 | ||
1378 | /* allocate RAM */ | |
1379 | if ((uint64_t)RAM_size > hwdef->max_mem) { | |
1380 | fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", | |
1381 | (unsigned int)RAM_size / (1024 * 1024), | |
1382 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); | |
1383 | exit(1); | |
1384 | } | |
1385 | cpu_register_physical_memory(0, RAM_size, 0); | |
1386 | ||
1387 | /* load boot prom */ | |
1388 | prom_offset = RAM_size + hwdef->vram_size; | |
1389 | cpu_register_physical_memory(hwdef->slavio_base, | |
1390 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & | |
1391 | TARGET_PAGE_MASK, | |
1392 | prom_offset | IO_MEM_ROM); | |
1393 | ||
1394 | if (bios_name == NULL) | |
1395 | bios_name = PROM_FILENAME; | |
1396 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
1397 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); | |
1398 | if (ret < 0 || ret > PROM_SIZE_MAX) | |
1399 | ret = load_image(buf, phys_ram_base + prom_offset); | |
1400 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
1401 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
1402 | buf); | |
1403 | exit(1); | |
1404 | } | |
1405 | ||
1406 | /* set up devices */ | |
1407 | sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); | |
1408 | ||
1409 | for (i = 0; i < MAX_IOUNITS; i++) | |
1410 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) | |
ff403da6 BS |
1411 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1412 | hwdef->iounit_version, | |
1413 | sbi_irq[hwdef->me_irq]); | |
7d85892b BS |
1414 | |
1415 | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], | |
1416 | iounits[0], &espdma_irq, &esp_reset); | |
1417 | ||
1418 | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], | |
1419 | iounits[0], &ledma_irq, &le_reset); | |
1420 | ||
1421 | if (graphic_depth != 8 && graphic_depth != 24) { | |
1422 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
1423 | exit (1); | |
1424 | } | |
1425 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, | |
1426 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); | |
1427 | ||
1428 | if (nd_table[0].model == NULL | |
1429 | || strcmp(nd_table[0].model, "lance") == 0) { | |
1430 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); | |
1431 | } else if (strcmp(nd_table[0].model, "?") == 0) { | |
1432 | fprintf(stderr, "qemu: Supported NICs: lance\n"); | |
1433 | exit (1); | |
1434 | } else { | |
1435 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
1436 | exit (1); | |
1437 | } | |
1438 | ||
1439 | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, | |
1440 | hwdef->nvram_size, 8); | |
1441 | ||
1442 | slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], | |
1443 | sbi_cpu_irq, smp_cpus); | |
1444 | ||
1445 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], | |
1446 | nographic); | |
1447 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device | |
1448 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
1449 | slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], | |
1450 | serial_hds[1], serial_hds[0]); | |
1451 | ||
1452 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
1453 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
1454 | exit(1); | |
1455 | } | |
1456 | ||
8b17de88 BS |
1457 | main_esp = esp_init(hwdef->esp_base, |
1458 | espdma_memory_read, espdma_memory_write, | |
1459 | espdma, *espdma_irq, esp_reset); | |
7d85892b BS |
1460 | |
1461 | for (i = 0; i < ESP_MAX_DEVS; i++) { | |
1462 | index = drive_get_index(IF_SCSI, 0, i); | |
1463 | if (index == -1) | |
1464 | continue; | |
1465 | esp_scsi_attach(main_esp, drives_table[index].bdrv, i); | |
1466 | } | |
1467 | ||
1468 | kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, | |
1469 | initrd_filename); | |
1470 | ||
1471 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, | |
1472 | boot_device, RAM_size, kernel_size, graphic_width, | |
1473 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4d"); | |
1474 | } | |
1475 | ||
1476 | /* SPARCserver 1000 hardware initialisation */ | |
1477 | static void ss1000_init(int RAM_size, int vga_ram_size, | |
1478 | const char *boot_device, DisplayState *ds, | |
1479 | const char *kernel_filename, const char *kernel_cmdline, | |
1480 | const char *initrd_filename, const char *cpu_model) | |
1481 | { | |
1482 | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename, | |
1483 | kernel_cmdline, initrd_filename, cpu_model); | |
1484 | } | |
1485 | ||
1486 | /* SPARCcenter 2000 hardware initialisation */ | |
1487 | static void ss2000_init(int RAM_size, int vga_ram_size, | |
1488 | const char *boot_device, DisplayState *ds, | |
1489 | const char *kernel_filename, const char *kernel_cmdline, | |
1490 | const char *initrd_filename, const char *cpu_model) | |
1491 | { | |
1492 | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename, | |
1493 | kernel_cmdline, initrd_filename, cpu_model); | |
1494 | } | |
1495 | ||
1496 | QEMUMachine ss1000_machine = { | |
1497 | "SS-1000", | |
1498 | "Sun4d platform, SPARCserver 1000", | |
1499 | ss1000_init, | |
1500 | }; | |
1501 | ||
1502 | QEMUMachine ss2000_machine = { | |
1503 | "SS-2000", | |
1504 | "Sun4d platform, SPARCcenter 2000", | |
1505 | ss2000_init, | |
1506 | }; |