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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
26 | #include "pc.h" | |
27 | #include "nvram.h" | |
28 | #include "fdc.h" | |
29 | #include "net.h" | |
30 | #include "qemu-timer.h" | |
31 | #include "sysemu.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
3cce6243 | 34 | #include "fw_cfg.h" |
3475187d | 35 | |
83469015 FB |
36 | #define KERNEL_LOAD_ADDR 0x00404000 |
37 | #define CMDLINE_ADDR 0x003ff000 | |
38 | #define INITRD_LOAD_ADDR 0x00300000 | |
ac2e9d66 | 39 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e BS |
40 | #define PROM_ADDR 0x1fff0000000ULL |
41 | #define PROM_VADDR 0x000ffd00000ULL | |
83469015 | 42 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e BS |
43 | #define APB_MEM_BASE 0x1ff00000000ULL |
44 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) | |
45 | #define PROM_FILENAME "openbios-sparc64" | |
83469015 | 46 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 47 | #define MAX_IDE_BUS 2 |
3cce6243 | 48 | #define BIOS_CFG_IOPORT 0x510 |
3475187d | 49 | |
c7ba218d BS |
50 | struct hwdef { |
51 | const char * const default_cpu_model; | |
52 | }; | |
53 | ||
3475187d FB |
54 | int DMA_get_channel_mode (int nchan) |
55 | { | |
56 | return 0; | |
57 | } | |
58 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
59 | { | |
60 | return 0; | |
61 | } | |
62 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
63 | { | |
64 | return 0; | |
65 | } | |
66 | void DMA_hold_DREQ (int nchan) {} | |
67 | void DMA_release_DREQ (int nchan) {} | |
68 | void DMA_schedule(int nchan) {} | |
69 | void DMA_run (void) {} | |
70 | void DMA_init (int high_page_enable) {} | |
71 | void DMA_register_channel (int nchan, | |
72 | DMA_transfer_handler transfer_handler, | |
73 | void *opaque) | |
74 | { | |
75 | } | |
76 | ||
81864572 BS |
77 | static int nvram_boot_set(void *opaque, const char *boot_device) |
78 | { | |
79 | unsigned int i; | |
80 | uint8_t image[sizeof(ohwcfg_v3_t)]; | |
81 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ | |
82 | m48t59_t *nvram = (m48t59_t *)opaque; | |
83 | ||
84 | for (i = 0; i < sizeof(image); i++) | |
85 | image[i] = m48t59_read(nvram, i) & 0xff; | |
86 | ||
363a37d5 BS |
87 | pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
88 | boot_device); | |
81864572 BS |
89 | header->nboot_devices = strlen(boot_device) & 0xff; |
90 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); | |
91 | ||
92 | for (i = 0; i < sizeof(image); i++) | |
93 | m48t59_write(nvram, i, image[i]); | |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
3475187d FB |
98 | extern int nographic; |
99 | ||
d2c63fc1 | 100 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
e7fb1406 | 101 | const char *arch, |
77f193da BS |
102 | ram_addr_t RAM_size, |
103 | const char *boot_devices, | |
d2c63fc1 BS |
104 | uint32_t kernel_image, uint32_t kernel_size, |
105 | const char *cmdline, | |
106 | uint32_t initrd_image, uint32_t initrd_size, | |
107 | uint32_t NVRAM_image, | |
0d31cb99 BS |
108 | int width, int height, int depth, |
109 | const uint8_t *macaddr) | |
83469015 | 110 | { |
66508601 BS |
111 | unsigned int i; |
112 | uint32_t start, end; | |
d2c63fc1 BS |
113 | uint8_t image[0x1ff0]; |
114 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ | |
115 | struct sparc_arch_cfg *sparc_header; | |
116 | struct OpenBIOS_nvpart_v1 *part_header; | |
117 | ||
118 | memset(image, '\0', sizeof(image)); | |
119 | ||
120 | // Try to match PPC NVRAM | |
363a37d5 BS |
121 | pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident), |
122 | "QEMU_BIOS"); | |
d2c63fc1 BS |
123 | header->struct_version = cpu_to_be32(3); /* structure v3 */ |
124 | ||
125 | header->nvram_size = cpu_to_be16(NVRAM_size); | |
126 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t)); | |
127 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); | |
363a37d5 | 128 | pstrcpy((char *)header->arch, sizeof(header->arch), arch); |
d2c63fc1 BS |
129 | header->nb_cpus = smp_cpus & 0xff; |
130 | header->RAM0_base = 0; | |
131 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); | |
363a37d5 BS |
132 | pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
133 | boot_devices); | |
d2c63fc1 BS |
134 | header->nboot_devices = strlen(boot_devices) & 0xff; |
135 | header->kernel_image = cpu_to_be64((uint64_t)kernel_image); | |
136 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); | |
3475187d | 137 | if (cmdline) { |
293f78bc | 138 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline); |
d2c63fc1 BS |
139 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
140 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); | |
3475187d | 141 | } |
d2c63fc1 BS |
142 | header->initrd_image = cpu_to_be64((uint64_t)initrd_image); |
143 | header->initrd_size = cpu_to_be64((uint64_t)initrd_size); | |
144 | header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image); | |
145 | ||
146 | header->width = cpu_to_be16(width); | |
147 | header->height = cpu_to_be16(height); | |
148 | header->depth = cpu_to_be16(depth); | |
149 | if (nographic) | |
150 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); | |
83469015 | 151 | |
d2c63fc1 BS |
152 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
153 | ||
154 | // Architecture specific header | |
155 | start = sizeof(ohwcfg_v3_t); | |
156 | sparc_header = (struct sparc_arch_cfg *)&image[start]; | |
157 | sparc_header->valid = 0; | |
158 | start += sizeof(struct sparc_arch_cfg); | |
83469015 | 159 | |
66508601 BS |
160 | // OpenBIOS nvram variables |
161 | // Variable partition | |
d2c63fc1 BS |
162 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
163 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 164 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 165 | |
d2c63fc1 | 166 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 167 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
168 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
169 | ||
170 | // End marker | |
171 | image[end++] = '\0'; | |
66508601 | 172 | |
66508601 | 173 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 174 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
175 | |
176 | // free partition | |
177 | start = end; | |
d2c63fc1 BS |
178 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
179 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 180 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
181 | |
182 | end = 0x1fd0; | |
d2c63fc1 BS |
183 | OpenBIOS_finish_partition(part_header, end - start); |
184 | ||
0d31cb99 BS |
185 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
186 | ||
d2c63fc1 BS |
187 | for (i = 0; i < sizeof(image); i++) |
188 | m48t59_write(nvram, i, image[i]); | |
66508601 | 189 | |
81864572 BS |
190 | qemu_register_boot_set(nvram_boot_set, nvram); |
191 | ||
83469015 | 192 | return 0; |
3475187d FB |
193 | } |
194 | ||
22548760 | 195 | void pic_info(void) |
3475187d FB |
196 | { |
197 | } | |
198 | ||
22548760 | 199 | void irq_info(void) |
3475187d FB |
200 | { |
201 | } | |
202 | ||
83469015 | 203 | void qemu_system_powerdown(void) |
3475187d FB |
204 | { |
205 | } | |
206 | ||
c68ea704 FB |
207 | static void main_cpu_reset(void *opaque) |
208 | { | |
209 | CPUState *env = opaque; | |
20c9f095 | 210 | |
c68ea704 | 211 | cpu_reset(env); |
20c9f095 BS |
212 | ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); |
213 | ptimer_run(env->tick, 0); | |
214 | ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); | |
215 | ptimer_run(env->stick, 0); | |
216 | ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); | |
217 | ptimer_run(env->hstick, 0); | |
218 | } | |
219 | ||
22548760 | 220 | static void tick_irq(void *opaque) |
20c9f095 BS |
221 | { |
222 | CPUState *env = opaque; | |
223 | ||
224 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
225 | } | |
226 | ||
22548760 | 227 | static void stick_irq(void *opaque) |
20c9f095 BS |
228 | { |
229 | CPUState *env = opaque; | |
230 | ||
231 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
232 | } | |
233 | ||
22548760 | 234 | static void hstick_irq(void *opaque) |
20c9f095 BS |
235 | { |
236 | CPUState *env = opaque; | |
237 | ||
238 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
c68ea704 FB |
239 | } |
240 | ||
f19e918d BS |
241 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
242 | { | |
243 | } | |
244 | ||
83469015 FB |
245 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
246 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
247 | static const int ide_irq[2] = { 14, 15 }; | |
3475187d | 248 | |
83469015 FB |
249 | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
250 | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
251 | ||
252 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; | |
253 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
254 | ||
255 | static fdctrl_t *floppy_controller; | |
3475187d | 256 | |
c7ba218d BS |
257 | static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size, |
258 | const char *boot_devices, DisplayState *ds, | |
259 | const char *kernel_filename, const char *kernel_cmdline, | |
260 | const char *initrd_filename, const char *cpu_model, | |
261 | const struct hwdef *hwdef) | |
3475187d | 262 | { |
c68ea704 | 263 | CPUState *env; |
3475187d | 264 | char buf[1024]; |
83469015 | 265 | m48t59_t *nvram; |
3475187d FB |
266 | int ret, linux_boot; |
267 | unsigned int i; | |
83469015 FB |
268 | long prom_offset, initrd_size, kernel_size; |
269 | PCIBus *pci_bus; | |
20c9f095 | 270 | QEMUBH *bh; |
f19e918d | 271 | qemu_irq *irq; |
22548760 | 272 | int drive_index; |
e4bcb14c TS |
273 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
274 | BlockDriverState *fd[MAX_FD]; | |
3cce6243 | 275 | void *fw_cfg; |
3475187d FB |
276 | |
277 | linux_boot = (kernel_filename != NULL); | |
278 | ||
62724a37 | 279 | /* init CPUs */ |
c7ba218d BS |
280 | if (!cpu_model) |
281 | cpu_model = hwdef->default_cpu_model; | |
282 | ||
aaed909a FB |
283 | env = cpu_init(cpu_model); |
284 | if (!env) { | |
62724a37 BS |
285 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); |
286 | exit(1); | |
287 | } | |
20c9f095 BS |
288 | bh = qemu_bh_new(tick_irq, env); |
289 | env->tick = ptimer_init(bh); | |
290 | ptimer_set_period(env->tick, 1ULL); | |
291 | ||
292 | bh = qemu_bh_new(stick_irq, env); | |
293 | env->stick = ptimer_init(bh); | |
294 | ptimer_set_period(env->stick, 1ULL); | |
295 | ||
296 | bh = qemu_bh_new(hstick_irq, env); | |
297 | env->hstick = ptimer_init(bh); | |
298 | ptimer_set_period(env->hstick, 1ULL); | |
c68ea704 | 299 | qemu_register_reset(main_cpu_reset, env); |
20c9f095 | 300 | main_cpu_reset(env); |
c68ea704 | 301 | |
3475187d | 302 | /* allocate RAM */ |
22548760 | 303 | cpu_register_physical_memory(0, RAM_size, 0); |
3475187d | 304 | |
22548760 | 305 | prom_offset = RAM_size + vga_ram_size; |
5fafdf24 | 306 | cpu_register_physical_memory(PROM_ADDR, |
77f193da BS |
307 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & |
308 | TARGET_PAGE_MASK, | |
b3783731 | 309 | prom_offset | IO_MEM_ROM); |
3475187d | 310 | |
1192dad8 JM |
311 | if (bios_name == NULL) |
312 | bios_name = PROM_FILENAME; | |
313 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
f19e918d | 314 | ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); |
3475187d | 315 | if (ret < 0) { |
f930d07e BS |
316 | fprintf(stderr, "qemu: could not load prom '%s'\n", |
317 | buf); | |
318 | exit(1); | |
3475187d | 319 | } |
3475187d FB |
320 | |
321 | kernel_size = 0; | |
83469015 | 322 | initrd_size = 0; |
3475187d | 323 | if (linux_boot) { |
b3783731 | 324 | /* XXX: put correct offset */ |
74287114 | 325 | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
3475187d | 326 | if (kernel_size < 0) |
293f78bc BS |
327 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
328 | ram_size - KERNEL_LOAD_ADDR); | |
f930d07e | 329 | if (kernel_size < 0) |
293f78bc BS |
330 | kernel_size = load_image_targphys(kernel_filename, |
331 | KERNEL_LOAD_ADDR, | |
332 | ram_size - KERNEL_LOAD_ADDR); | |
3475187d | 333 | if (kernel_size < 0) { |
5fafdf24 | 334 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
3475187d | 335 | kernel_filename); |
f930d07e | 336 | exit(1); |
3475187d FB |
337 | } |
338 | ||
339 | /* load initrd */ | |
3475187d | 340 | if (initrd_filename) { |
293f78bc BS |
341 | initrd_size = load_image_targphys(initrd_filename, |
342 | INITRD_LOAD_ADDR, | |
343 | ram_size - INITRD_LOAD_ADDR); | |
3475187d | 344 | if (initrd_size < 0) { |
5fafdf24 | 345 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
3475187d FB |
346 | initrd_filename); |
347 | exit(1); | |
348 | } | |
349 | } | |
350 | if (initrd_size > 0) { | |
f930d07e | 351 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
293f78bc BS |
352 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
353 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
354 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
f930d07e BS |
355 | break; |
356 | } | |
357 | } | |
3475187d FB |
358 | } |
359 | } | |
502a5395 | 360 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); |
83469015 | 361 | isa_mem_base = VGA_BASE; |
77f193da BS |
362 | pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size, |
363 | vga_ram_size); | |
83469015 FB |
364 | |
365 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
366 | if (serial_hds[i]) { | |
cbf5c748 BS |
367 | serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
368 | serial_hds[i]); | |
83469015 FB |
369 | } |
370 | } | |
371 | ||
372 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
373 | if (parallel_hds[i]) { | |
77f193da BS |
374 | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, |
375 | parallel_hds[i]); | |
83469015 FB |
376 | } |
377 | } | |
378 | ||
379 | for(i = 0; i < nb_nics; i++) { | |
a41b2ff2 PB |
380 | if (!nd_table[i].model) |
381 | nd_table[i].model = "ne2k_pci"; | |
f930d07e | 382 | pci_nic_init(pci_bus, &nd_table[i], -1); |
83469015 FB |
383 | } |
384 | ||
f19e918d | 385 | irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32); |
e4bcb14c TS |
386 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
387 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
388 | exit(1); | |
389 | } | |
390 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
22548760 BS |
391 | drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, |
392 | i % MAX_IDE_DEVS); | |
393 | if (drive_index != -1) | |
394 | hd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
395 | else |
396 | hd[i] = NULL; | |
397 | } | |
398 | ||
399 | // XXX pci_cmd646_ide_init(pci_bus, hd, 1); | |
400 | pci_piix3_ide_init(pci_bus, hd, -1, irq); | |
d537cf6c PB |
401 | /* FIXME: wire up interrupts. */ |
402 | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); | |
e4bcb14c | 403 | for(i = 0; i < MAX_FD; i++) { |
22548760 BS |
404 | drive_index = drive_get_index(IF_FLOPPY, 0, i); |
405 | if (drive_index != -1) | |
406 | fd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
407 | else |
408 | fd[i] = NULL; | |
409 | } | |
410 | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd); | |
d537cf6c | 411 | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
22548760 | 412 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices, |
0d31cb99 BS |
413 | KERNEL_LOAD_ADDR, kernel_size, |
414 | kernel_cmdline, | |
415 | INITRD_LOAD_ADDR, initrd_size, | |
416 | /* XXX: need an option to load a NVRAM image */ | |
417 | 0, | |
418 | graphic_width, graphic_height, graphic_depth, | |
419 | (uint8_t *)&nd_table[0].macaddr); | |
83469015 | 420 | |
3cce6243 BS |
421 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
422 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
3475187d FB |
423 | } |
424 | ||
c7ba218d BS |
425 | static const struct hwdef hwdefs[] = { |
426 | /* Sun4u generic PC-like machine */ | |
427 | { | |
428 | .default_cpu_model = "TI UltraSparc II", | |
429 | }, | |
430 | /* Sun4v generic PC-like machine */ | |
431 | { | |
432 | .default_cpu_model = "Sun UltraSparc T1", | |
433 | }, | |
434 | }; | |
435 | ||
436 | /* Sun4u hardware initialisation */ | |
437 | static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, | |
438 | const char *boot_devices, DisplayState *ds, | |
439 | const char *kernel_filename, const char *kernel_cmdline, | |
440 | const char *initrd_filename, const char *cpu_model) | |
441 | { | |
442 | sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, | |
443 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]); | |
444 | } | |
445 | ||
446 | /* Sun4v hardware initialisation */ | |
447 | static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size, | |
448 | const char *boot_devices, DisplayState *ds, | |
449 | const char *kernel_filename, const char *kernel_cmdline, | |
450 | const char *initrd_filename, const char *cpu_model) | |
451 | { | |
452 | sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, | |
453 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]); | |
454 | } | |
455 | ||
3475187d | 456 | QEMUMachine sun4u_machine = { |
66de733b BS |
457 | .name = "sun4u", |
458 | .desc = "Sun4u platform", | |
459 | .init = sun4u_init, | |
460 | .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, | |
f88e4b91 | 461 | .nodisk_ok = 1, |
3475187d | 462 | }; |
c7ba218d BS |
463 | |
464 | QEMUMachine sun4v_machine = { | |
66de733b BS |
465 | .name = "sun4v", |
466 | .desc = "Sun4v platform", | |
467 | .init = sun4v_init, | |
468 | .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, | |
f88e4b91 | 469 | .nodisk_ok = 1, |
c7ba218d | 470 | }; |