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3475187d FB |
1 | /* |
2 | * QEMU Sun4u System Emulator | |
3 | * | |
4 | * Copyright (c) 2005 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "vl.h" | |
25 | #include "m48t08.h" | |
26 | ||
27 | #define KERNEL_LOAD_ADDR 0x00004000 | |
28 | #define CMDLINE_ADDR 0x007ff000 | |
29 | #define INITRD_LOAD_ADDR 0x00800000 | |
30 | #define PROM_ADDR 0xffd00000 | |
31 | #define PROM_FILENAMEB "proll-sparc64.bin" | |
32 | #define PROM_FILENAMEE "proll-sparc64.elf" | |
33 | #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ | |
34 | #define PHYS_JJ_IDPROM_OFF 0x1FD8 | |
35 | #define PHYS_JJ_EEPROM_SIZE 0x2000 | |
36 | // IRQs are not PIL ones, but master interrupt controller register | |
37 | // bits | |
38 | #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ | |
39 | #define PHYS_JJ_MS_KBD_IRQ 14 | |
40 | #define PHYS_JJ_SER 0x71100000 /* Serial */ | |
41 | #define PHYS_JJ_SER_IRQ 15 | |
42 | ||
43 | /* TSC handling */ | |
44 | ||
45 | uint64_t cpu_get_tsc() | |
46 | { | |
47 | return qemu_get_clock(vm_clock); | |
48 | } | |
49 | ||
50 | int DMA_get_channel_mode (int nchan) | |
51 | { | |
52 | return 0; | |
53 | } | |
54 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
55 | { | |
56 | return 0; | |
57 | } | |
58 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
59 | { | |
60 | return 0; | |
61 | } | |
62 | void DMA_hold_DREQ (int nchan) {} | |
63 | void DMA_release_DREQ (int nchan) {} | |
64 | void DMA_schedule(int nchan) {} | |
65 | void DMA_run (void) {} | |
66 | void DMA_init (int high_page_enable) {} | |
67 | void DMA_register_channel (int nchan, | |
68 | DMA_transfer_handler transfer_handler, | |
69 | void *opaque) | |
70 | { | |
71 | } | |
72 | ||
73 | static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value) | |
74 | { | |
75 | m48t08_write(nvram, addr++, (value >> 8) & 0xff); | |
76 | m48t08_write(nvram, addr++, value & 0xff); | |
77 | } | |
78 | ||
79 | static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value) | |
80 | { | |
81 | m48t08_write(nvram, addr++, value >> 24); | |
82 | m48t08_write(nvram, addr++, (value >> 16) & 0xff); | |
83 | m48t08_write(nvram, addr++, (value >> 8) & 0xff); | |
84 | m48t08_write(nvram, addr++, value & 0xff); | |
85 | } | |
86 | ||
87 | static void nvram_set_string (m48t08_t *nvram, uint32_t addr, | |
88 | const unsigned char *str, uint32_t max) | |
89 | { | |
90 | unsigned int i; | |
91 | ||
92 | for (i = 0; i < max && str[i] != '\0'; i++) { | |
93 | m48t08_write(nvram, addr + i, str[i]); | |
94 | } | |
95 | m48t08_write(nvram, addr + max - 1, '\0'); | |
96 | } | |
97 | ||
98 | static m48t08_t *nvram; | |
99 | ||
100 | extern int nographic; | |
101 | ||
102 | static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline, | |
103 | int boot_device, uint32_t RAM_size, | |
104 | uint32_t kernel_size, | |
105 | int width, int height, int depth) | |
106 | { | |
107 | unsigned char tmp = 0; | |
108 | int i, j; | |
109 | ||
110 | // Try to match PPC NVRAM | |
111 | nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); | |
112 | nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ | |
113 | // NVRAM_size, arch not applicable | |
114 | m48t08_write(nvram, 0x2F, nographic & 0xff); | |
115 | nvram_set_lword(nvram, 0x30, RAM_size); | |
116 | m48t08_write(nvram, 0x34, boot_device & 0xff); | |
117 | nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); | |
118 | nvram_set_lword(nvram, 0x3C, kernel_size); | |
119 | if (cmdline) { | |
120 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); | |
121 | nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); | |
122 | nvram_set_lword(nvram, 0x44, strlen(cmdline)); | |
123 | } | |
124 | // initrd_image, initrd_size passed differently | |
125 | nvram_set_word(nvram, 0x54, width); | |
126 | nvram_set_word(nvram, 0x56, height); | |
127 | nvram_set_word(nvram, 0x58, depth); | |
128 | ||
129 | // Sun4m specific use | |
130 | i = 0x1fd8; | |
131 | m48t08_write(nvram, i++, 0x01); | |
132 | m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ | |
133 | j = 0; | |
134 | m48t08_write(nvram, i++, macaddr[j++]); | |
135 | m48t08_write(nvram, i++, macaddr[j++]); | |
136 | m48t08_write(nvram, i++, macaddr[j++]); | |
137 | m48t08_write(nvram, i++, macaddr[j++]); | |
138 | m48t08_write(nvram, i++, macaddr[j++]); | |
139 | m48t08_write(nvram, i, macaddr[j]); | |
140 | ||
141 | /* Calculate checksum */ | |
142 | for (i = 0x1fd8; i < 0x1fe7; i++) { | |
143 | tmp ^= m48t08_read(nvram, i); | |
144 | } | |
145 | m48t08_write(nvram, 0x1fe7, tmp); | |
146 | } | |
147 | ||
148 | void pic_info() | |
149 | { | |
150 | } | |
151 | ||
152 | void irq_info() | |
153 | { | |
154 | } | |
155 | ||
156 | void pic_set_irq(int irq, int level) | |
157 | { | |
158 | } | |
159 | ||
160 | void vga_update_display() | |
161 | { | |
162 | } | |
163 | ||
164 | void vga_invalidate_display() | |
165 | { | |
166 | } | |
167 | ||
168 | void vga_screen_dump(const char *filename) | |
169 | { | |
170 | } | |
171 | ||
172 | void qemu_system_powerdown(void) | |
173 | { | |
174 | } | |
175 | ||
176 | /* Sun4u hardware initialisation */ | |
177 | static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, | |
178 | DisplayState *ds, const char **fd_filename, int snapshot, | |
179 | const char *kernel_filename, const char *kernel_cmdline, | |
180 | const char *initrd_filename) | |
181 | { | |
182 | char buf[1024]; | |
183 | int ret, linux_boot; | |
184 | unsigned int i; | |
185 | long vram_size = 0x100000, prom_offset, initrd_size, kernel_size; | |
186 | ||
187 | linux_boot = (kernel_filename != NULL); | |
188 | ||
189 | /* allocate RAM */ | |
190 | cpu_register_physical_memory(0, ram_size, 0); | |
191 | ||
192 | nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); | |
193 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device | |
194 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
195 | slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]); | |
196 | ||
197 | prom_offset = ram_size + vram_size; | |
198 | ||
199 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE); | |
200 | ret = load_elf(buf, phys_ram_base + prom_offset); | |
201 | if (ret < 0) { | |
202 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB); | |
203 | ret = load_image(buf, phys_ram_base + prom_offset); | |
204 | } | |
205 | if (ret < 0) { | |
206 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
207 | buf); | |
208 | exit(1); | |
209 | } | |
210 | cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, | |
211 | prom_offset | IO_MEM_ROM); | |
212 | ||
213 | kernel_size = 0; | |
214 | if (linux_boot) { | |
215 | kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
216 | if (kernel_size < 0) | |
217 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
218 | if (kernel_size < 0) | |
219 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
220 | if (kernel_size < 0) { | |
221 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
222 | kernel_filename); | |
223 | exit(1); | |
224 | } | |
225 | ||
226 | /* load initrd */ | |
227 | initrd_size = 0; | |
228 | if (initrd_filename) { | |
229 | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); | |
230 | if (initrd_size < 0) { | |
231 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
232 | initrd_filename); | |
233 | exit(1); | |
234 | } | |
235 | } | |
236 | if (initrd_size > 0) { | |
237 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
238 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) | |
239 | == 0x48647253) { // HdrS | |
240 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
241 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
242 | break; | |
243 | } | |
244 | } | |
245 | } | |
246 | } | |
247 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth); | |
248 | } | |
249 | ||
250 | QEMUMachine sun4u_machine = { | |
251 | "sun4u", | |
252 | "Sun4u platform", | |
253 | sun4u_init, | |
254 | }; |