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Commit | Line | Data |
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3475187d FB |
1 | /* |
2 | * QEMU Sun4u System Emulator | |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
26 | #include "pc.h" | |
27 | #include "nvram.h" | |
28 | #include "fdc.h" | |
29 | #include "net.h" | |
30 | #include "qemu-timer.h" | |
31 | #include "sysemu.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
3475187d | 34 | |
83469015 FB |
35 | #define KERNEL_LOAD_ADDR 0x00404000 |
36 | #define CMDLINE_ADDR 0x003ff000 | |
37 | #define INITRD_LOAD_ADDR 0x00300000 | |
ac2e9d66 | 38 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e BS |
39 | #define PROM_ADDR 0x1fff0000000ULL |
40 | #define PROM_VADDR 0x000ffd00000ULL | |
83469015 | 41 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e BS |
42 | #define APB_MEM_BASE 0x1ff00000000ULL |
43 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) | |
44 | #define PROM_FILENAME "openbios-sparc64" | |
83469015 | 45 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 46 | #define MAX_IDE_BUS 2 |
3475187d | 47 | |
3475187d FB |
48 | int DMA_get_channel_mode (int nchan) |
49 | { | |
50 | return 0; | |
51 | } | |
52 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
53 | { | |
54 | return 0; | |
55 | } | |
56 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
57 | { | |
58 | return 0; | |
59 | } | |
60 | void DMA_hold_DREQ (int nchan) {} | |
61 | void DMA_release_DREQ (int nchan) {} | |
62 | void DMA_schedule(int nchan) {} | |
63 | void DMA_run (void) {} | |
64 | void DMA_init (int high_page_enable) {} | |
65 | void DMA_register_channel (int nchan, | |
66 | DMA_transfer_handler transfer_handler, | |
67 | void *opaque) | |
68 | { | |
69 | } | |
70 | ||
3475187d FB |
71 | extern int nographic; |
72 | ||
d2c63fc1 BS |
73 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
74 | const unsigned char *arch, | |
77f193da BS |
75 | ram_addr_t RAM_size, |
76 | const char *boot_devices, | |
d2c63fc1 BS |
77 | uint32_t kernel_image, uint32_t kernel_size, |
78 | const char *cmdline, | |
79 | uint32_t initrd_image, uint32_t initrd_size, | |
80 | uint32_t NVRAM_image, | |
81 | int width, int height, int depth) | |
83469015 | 82 | { |
66508601 BS |
83 | unsigned int i; |
84 | uint32_t start, end; | |
d2c63fc1 BS |
85 | uint8_t image[0x1ff0]; |
86 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ | |
87 | struct sparc_arch_cfg *sparc_header; | |
88 | struct OpenBIOS_nvpart_v1 *part_header; | |
89 | ||
90 | memset(image, '\0', sizeof(image)); | |
91 | ||
92 | // Try to match PPC NVRAM | |
93 | strcpy(header->struct_ident, "QEMU_BIOS"); | |
94 | header->struct_version = cpu_to_be32(3); /* structure v3 */ | |
95 | ||
96 | header->nvram_size = cpu_to_be16(NVRAM_size); | |
97 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t)); | |
98 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); | |
99 | strcpy(header->arch, arch); | |
100 | header->nb_cpus = smp_cpus & 0xff; | |
101 | header->RAM0_base = 0; | |
102 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); | |
103 | strcpy(header->boot_devices, boot_devices); | |
104 | header->nboot_devices = strlen(boot_devices) & 0xff; | |
105 | header->kernel_image = cpu_to_be64((uint64_t)kernel_image); | |
106 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); | |
3475187d | 107 | if (cmdline) { |
293f78bc | 108 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline); |
d2c63fc1 BS |
109 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
110 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); | |
3475187d | 111 | } |
d2c63fc1 BS |
112 | header->initrd_image = cpu_to_be64((uint64_t)initrd_image); |
113 | header->initrd_size = cpu_to_be64((uint64_t)initrd_size); | |
114 | header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image); | |
115 | ||
116 | header->width = cpu_to_be16(width); | |
117 | header->height = cpu_to_be16(height); | |
118 | header->depth = cpu_to_be16(depth); | |
119 | if (nographic) | |
120 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); | |
83469015 | 121 | |
d2c63fc1 BS |
122 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
123 | ||
124 | // Architecture specific header | |
125 | start = sizeof(ohwcfg_v3_t); | |
126 | sparc_header = (struct sparc_arch_cfg *)&image[start]; | |
127 | sparc_header->valid = 0; | |
128 | start += sizeof(struct sparc_arch_cfg); | |
83469015 | 129 | |
66508601 BS |
130 | // OpenBIOS nvram variables |
131 | // Variable partition | |
d2c63fc1 BS |
132 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
133 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
134 | strcpy(part_header->name, "system"); | |
66508601 | 135 | |
d2c63fc1 | 136 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 137 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
138 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
139 | ||
140 | // End marker | |
141 | image[end++] = '\0'; | |
66508601 | 142 | |
66508601 | 143 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 144 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
145 | |
146 | // free partition | |
147 | start = end; | |
d2c63fc1 BS |
148 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
149 | part_header->signature = OPENBIOS_PART_FREE; | |
150 | strcpy(part_header->name, "free"); | |
66508601 BS |
151 | |
152 | end = 0x1fd0; | |
d2c63fc1 BS |
153 | OpenBIOS_finish_partition(part_header, end - start); |
154 | ||
155 | for (i = 0; i < sizeof(image); i++) | |
156 | m48t59_write(nvram, i, image[i]); | |
66508601 | 157 | |
83469015 | 158 | return 0; |
3475187d FB |
159 | } |
160 | ||
22548760 | 161 | void pic_info(void) |
3475187d FB |
162 | { |
163 | } | |
164 | ||
22548760 | 165 | void irq_info(void) |
3475187d FB |
166 | { |
167 | } | |
168 | ||
83469015 | 169 | void qemu_system_powerdown(void) |
3475187d FB |
170 | { |
171 | } | |
172 | ||
c68ea704 FB |
173 | static void main_cpu_reset(void *opaque) |
174 | { | |
175 | CPUState *env = opaque; | |
20c9f095 | 176 | |
c68ea704 | 177 | cpu_reset(env); |
20c9f095 BS |
178 | ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); |
179 | ptimer_run(env->tick, 0); | |
180 | ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); | |
181 | ptimer_run(env->stick, 0); | |
182 | ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); | |
183 | ptimer_run(env->hstick, 0); | |
184 | } | |
185 | ||
22548760 | 186 | static void tick_irq(void *opaque) |
20c9f095 BS |
187 | { |
188 | CPUState *env = opaque; | |
189 | ||
190 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
191 | } | |
192 | ||
22548760 | 193 | static void stick_irq(void *opaque) |
20c9f095 BS |
194 | { |
195 | CPUState *env = opaque; | |
196 | ||
197 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
198 | } | |
199 | ||
22548760 | 200 | static void hstick_irq(void *opaque) |
20c9f095 BS |
201 | { |
202 | CPUState *env = opaque; | |
203 | ||
204 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
c68ea704 FB |
205 | } |
206 | ||
f19e918d BS |
207 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
208 | { | |
209 | } | |
210 | ||
83469015 FB |
211 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
212 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
213 | static const int ide_irq[2] = { 14, 15 }; | |
3475187d | 214 | |
83469015 FB |
215 | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
216 | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
217 | ||
218 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; | |
219 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
220 | ||
221 | static fdctrl_t *floppy_controller; | |
3475187d FB |
222 | |
223 | /* Sun4u hardware initialisation */ | |
22548760 | 224 | static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, |
b881c2c6 BS |
225 | const char *boot_devices, DisplayState *ds, |
226 | const char *kernel_filename, const char *kernel_cmdline, | |
227 | const char *initrd_filename, const char *cpu_model) | |
3475187d | 228 | { |
c68ea704 | 229 | CPUState *env; |
3475187d | 230 | char buf[1024]; |
83469015 | 231 | m48t59_t *nvram; |
3475187d FB |
232 | int ret, linux_boot; |
233 | unsigned int i; | |
83469015 FB |
234 | long prom_offset, initrd_size, kernel_size; |
235 | PCIBus *pci_bus; | |
20c9f095 | 236 | QEMUBH *bh; |
f19e918d | 237 | qemu_irq *irq; |
22548760 | 238 | int drive_index; |
e4bcb14c TS |
239 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
240 | BlockDriverState *fd[MAX_FD]; | |
3475187d FB |
241 | |
242 | linux_boot = (kernel_filename != NULL); | |
243 | ||
62724a37 BS |
244 | /* init CPUs */ |
245 | if (cpu_model == NULL) | |
246 | cpu_model = "TI UltraSparc II"; | |
aaed909a FB |
247 | env = cpu_init(cpu_model); |
248 | if (!env) { | |
62724a37 BS |
249 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); |
250 | exit(1); | |
251 | } | |
20c9f095 BS |
252 | bh = qemu_bh_new(tick_irq, env); |
253 | env->tick = ptimer_init(bh); | |
254 | ptimer_set_period(env->tick, 1ULL); | |
255 | ||
256 | bh = qemu_bh_new(stick_irq, env); | |
257 | env->stick = ptimer_init(bh); | |
258 | ptimer_set_period(env->stick, 1ULL); | |
259 | ||
260 | bh = qemu_bh_new(hstick_irq, env); | |
261 | env->hstick = ptimer_init(bh); | |
262 | ptimer_set_period(env->hstick, 1ULL); | |
1a14026e | 263 | register_savevm("cpu", 0, 4, cpu_save, cpu_load, env); |
c68ea704 | 264 | qemu_register_reset(main_cpu_reset, env); |
20c9f095 | 265 | main_cpu_reset(env); |
c68ea704 | 266 | |
3475187d | 267 | /* allocate RAM */ |
22548760 | 268 | cpu_register_physical_memory(0, RAM_size, 0); |
3475187d | 269 | |
22548760 | 270 | prom_offset = RAM_size + vga_ram_size; |
5fafdf24 | 271 | cpu_register_physical_memory(PROM_ADDR, |
77f193da BS |
272 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & |
273 | TARGET_PAGE_MASK, | |
b3783731 | 274 | prom_offset | IO_MEM_ROM); |
3475187d | 275 | |
1192dad8 JM |
276 | if (bios_name == NULL) |
277 | bios_name = PROM_FILENAME; | |
278 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
f19e918d | 279 | ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); |
3475187d | 280 | if (ret < 0) { |
f930d07e BS |
281 | fprintf(stderr, "qemu: could not load prom '%s'\n", |
282 | buf); | |
283 | exit(1); | |
3475187d | 284 | } |
3475187d FB |
285 | |
286 | kernel_size = 0; | |
83469015 | 287 | initrd_size = 0; |
3475187d | 288 | if (linux_boot) { |
b3783731 | 289 | /* XXX: put correct offset */ |
74287114 | 290 | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
3475187d | 291 | if (kernel_size < 0) |
293f78bc BS |
292 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
293 | ram_size - KERNEL_LOAD_ADDR); | |
f930d07e | 294 | if (kernel_size < 0) |
293f78bc BS |
295 | kernel_size = load_image_targphys(kernel_filename, |
296 | KERNEL_LOAD_ADDR, | |
297 | ram_size - KERNEL_LOAD_ADDR); | |
3475187d | 298 | if (kernel_size < 0) { |
5fafdf24 | 299 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
3475187d | 300 | kernel_filename); |
f930d07e | 301 | exit(1); |
3475187d FB |
302 | } |
303 | ||
304 | /* load initrd */ | |
3475187d | 305 | if (initrd_filename) { |
293f78bc BS |
306 | initrd_size = load_image_targphys(initrd_filename, |
307 | INITRD_LOAD_ADDR, | |
308 | ram_size - INITRD_LOAD_ADDR); | |
3475187d | 309 | if (initrd_size < 0) { |
5fafdf24 | 310 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
3475187d FB |
311 | initrd_filename); |
312 | exit(1); | |
313 | } | |
314 | } | |
315 | if (initrd_size > 0) { | |
f930d07e | 316 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
293f78bc BS |
317 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
318 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
319 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
f930d07e BS |
320 | break; |
321 | } | |
322 | } | |
3475187d FB |
323 | } |
324 | } | |
502a5395 | 325 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); |
83469015 | 326 | isa_mem_base = VGA_BASE; |
77f193da BS |
327 | pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size, |
328 | vga_ram_size); | |
83469015 FB |
329 | |
330 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
331 | if (serial_hds[i]) { | |
cbf5c748 BS |
332 | serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
333 | serial_hds[i]); | |
83469015 FB |
334 | } |
335 | } | |
336 | ||
337 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
338 | if (parallel_hds[i]) { | |
77f193da BS |
339 | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, |
340 | parallel_hds[i]); | |
83469015 FB |
341 | } |
342 | } | |
343 | ||
344 | for(i = 0; i < nb_nics; i++) { | |
a41b2ff2 PB |
345 | if (!nd_table[i].model) |
346 | nd_table[i].model = "ne2k_pci"; | |
f930d07e | 347 | pci_nic_init(pci_bus, &nd_table[i], -1); |
83469015 FB |
348 | } |
349 | ||
f19e918d | 350 | irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32); |
e4bcb14c TS |
351 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
352 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
353 | exit(1); | |
354 | } | |
355 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
22548760 BS |
356 | drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, |
357 | i % MAX_IDE_DEVS); | |
358 | if (drive_index != -1) | |
359 | hd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
360 | else |
361 | hd[i] = NULL; | |
362 | } | |
363 | ||
364 | // XXX pci_cmd646_ide_init(pci_bus, hd, 1); | |
365 | pci_piix3_ide_init(pci_bus, hd, -1, irq); | |
d537cf6c PB |
366 | /* FIXME: wire up interrupts. */ |
367 | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); | |
e4bcb14c | 368 | for(i = 0; i < MAX_FD; i++) { |
22548760 BS |
369 | drive_index = drive_get_index(IF_FLOPPY, 0, i); |
370 | if (drive_index != -1) | |
371 | fd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
372 | else |
373 | fd[i] = NULL; | |
374 | } | |
375 | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd); | |
d537cf6c | 376 | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
22548760 | 377 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices, |
83469015 FB |
378 | KERNEL_LOAD_ADDR, kernel_size, |
379 | kernel_cmdline, | |
380 | INITRD_LOAD_ADDR, initrd_size, | |
381 | /* XXX: need an option to load a NVRAM image */ | |
382 | 0, | |
383 | graphic_width, graphic_height, graphic_depth); | |
384 | ||
3475187d FB |
385 | } |
386 | ||
387 | QEMUMachine sun4u_machine = { | |
388 | "sun4u", | |
389 | "Sun4u platform", | |
390 | sun4u_init, | |
7fb4fdcf | 391 | PROM_SIZE_MAX + VGA_RAM_SIZE, |
3475187d | 392 | }; |