[qemu.git] / hw / sun4u.c

/*
 * QEMU Sun4u System Emulator
 * 
 * Copyright (c) 2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
#include "m48t59.h"

#define KERNEL_LOAD_ADDR     0x00404000
#define CMDLINE_ADDR         0x003ff000
#define INITRD_LOAD_ADDR     0x00300000
#define PROM_SIZE_MAX        (256 * 1024)
#define PROM_ADDR	     0x1fff0000000ULL
#define APB_SPECIAL_BASE     0x1fe00000000ULL
#define APB_MEM_BASE	     0x1ff00000000ULL
#define VGA_BASE	     (APB_MEM_BASE + 0x400000ULL)
#define PROM_FILENAMEB	     "proll-sparc64.bin"
#define PROM_FILENAMEE	     "proll-sparc64.elf"
#define NVRAM_SIZE           0x2000

/* TSC handling */

uint64_t cpu_get_tsc()
{
    return qemu_get_clock(vm_clock);
}

int DMA_get_channel_mode (int nchan)
{
    return 0;
}
int DMA_read_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
int DMA_write_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(int nchan) {}
void DMA_run (void) {}
void DMA_init (int high_page_enable) {}
void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler,
                           void *opaque)
{
}

/* NVRAM helpers */
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
{
    m48t59_write(nvram, addr, value);
}

uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
{
    return m48t59_read(nvram, addr);
}

void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
{
    m48t59_write(nvram, addr, value >> 8);
    m48t59_write(nvram, addr + 1, value & 0xFF);
}

uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
{
    uint16_t tmp;

    tmp = m48t59_read(nvram, addr) << 8;
    tmp |= m48t59_read(nvram, addr + 1);

    return tmp;
}

void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
{
    m48t59_write(nvram, addr, value >> 24);
    m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
    m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
    m48t59_write(nvram, addr + 3, value & 0xFF);
}

uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
{
    uint32_t tmp;

    tmp = m48t59_read(nvram, addr) << 24;
    tmp |= m48t59_read(nvram, addr + 1) << 16;
    tmp |= m48t59_read(nvram, addr + 2) << 8;
    tmp |= m48t59_read(nvram, addr + 3);

    return tmp;
}

void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
                       const unsigned char *str, uint32_t max)
{
    int i;

    for (i = 0; i < max && str[i] != '\0'; i++) {
        m48t59_write(nvram, addr + i, str[i]);
    }
    m48t59_write(nvram, addr + max - 1, '\0');
}

int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
{
    int i;

    memset(dst, 0, max);
    for (i = 0; i < max; i++) {
        dst[i] = NVRAM_get_byte(nvram, addr + i);
        if (dst[i] == '\0')
            break;
    }

    return i;
}

static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
{
    uint16_t tmp;
    uint16_t pd, pd1, pd2;

    tmp = prev >> 8;
    pd = prev ^ value;
    pd1 = pd & 0x000F;
    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
    tmp ^= (pd1 << 3) | (pd1 << 8);
    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);

    return tmp;
}

uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
{
    uint32_t i;
    uint16_t crc = 0xFFFF;
    int odd;

    odd = count & 1;
    count &= ~1;
    for (i = 0; i != count; i++) {
	crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
    }
    if (odd) {
	crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
    }

    return crc;
}

extern int nographic;

int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
                          const unsigned char *arch,
                          uint32_t RAM_size, int boot_device,
                          uint32_t kernel_image, uint32_t kernel_size,
                          const char *cmdline,
                          uint32_t initrd_image, uint32_t initrd_size,
                          uint32_t NVRAM_image,
                          int width, int height, int depth)
{
    uint16_t crc;

    /* Set parameters for Open Hack'Ware BIOS */
    NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
    NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
    NVRAM_set_word(nvram,   0x14, NVRAM_size);
    NVRAM_set_string(nvram, 0x20, arch, 16);
    NVRAM_set_byte(nvram,   0x2f, nographic & 0xff);
    NVRAM_set_lword(nvram,  0x30, RAM_size);
    NVRAM_set_byte(nvram,   0x34, boot_device);
    NVRAM_set_lword(nvram,  0x38, kernel_image);
    NVRAM_set_lword(nvram,  0x3C, kernel_size);
    if (cmdline) {
        /* XXX: put the cmdline in NVRAM too ? */
        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
        NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
        NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
    } else {
        NVRAM_set_lword(nvram,  0x40, 0);
        NVRAM_set_lword(nvram,  0x44, 0);
    }
    NVRAM_set_lword(nvram,  0x48, initrd_image);
    NVRAM_set_lword(nvram,  0x4C, initrd_size);
    NVRAM_set_lword(nvram,  0x50, NVRAM_image);

    NVRAM_set_word(nvram,   0x54, width);
    NVRAM_set_word(nvram,   0x56, height);
    NVRAM_set_word(nvram,   0x58, depth);
    crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
    NVRAM_set_word(nvram,  0xFC, crc);

    return 0;
}

void pic_info()
{
}

void irq_info()
{
}

void pic_set_irq(int irq, int level)
{
}

void pic_set_irq_new(void *opaque, int irq, int level)
{
}

void qemu_system_powerdown(void)
{
}

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;
    cpu_reset(env);
}

static const int ide_iobase[2] = { 0x1f0, 0x170 };
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 14, 15 };

static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };

static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };

static fdctrl_t *floppy_controller;

/* Sun4u hardware initialisation */
static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
             DisplayState *ds, const char **fd_filename, int snapshot,
             const char *kernel_filename, const char *kernel_cmdline,
             const char *initrd_filename)
{
    CPUState *env;
    char buf[1024];
    m48t59_t *nvram;
    int ret, linux_boot;
    unsigned int i;
    long prom_offset, initrd_size, kernel_size;
    PCIBus *pci_bus;

    linux_boot = (kernel_filename != NULL);

    env = cpu_init();
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
    qemu_register_reset(main_cpu_reset, env);

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, 0);

    prom_offset = ram_size + vga_ram_size;
    cpu_register_physical_memory(PROM_ADDR, 
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, 
                                 prom_offset | IO_MEM_ROM);

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
    ret = load_elf(buf, 0, NULL);
    if (ret < 0) {
	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
	ret = load_image(buf, phys_ram_base + prom_offset);
    }
    if (ret < 0) {
	fprintf(stderr, "qemu: could not load prom '%s'\n", 
		buf);
	exit(1);
    }

    kernel_size = 0;
    initrd_size = 0;
    if (linux_boot) {
        /* XXX: put correct offset */
        kernel_size = load_elf(kernel_filename, 0, NULL);
        if (kernel_size < 0)
	    kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
	if (kernel_size < 0)
	    kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n", 
                    kernel_filename);
	    exit(1);
        }

        /* load initrd */
        if (initrd_filename) {
            initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
                        initrd_filename);
                exit(1);
            }
        }
        if (initrd_size > 0) {
	    for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
		if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
		    == 0x48647253) { // HdrS
		    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
		    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
		    break;
		}
	    }
        }
    }
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE);
    isa_mem_base = VGA_BASE;
    vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, 
                   vga_ram_size, 0, 0);
    cpu_register_physical_memory(VGA_BASE, vga_ram_size, ram_size);
    //pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);

    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
        if (serial_hds[i]) {
            serial_init(&pic_set_irq_new, NULL,
                        serial_io[i], serial_irq[i], serial_hds[i]);
        }
    }

    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
        if (parallel_hds[i]) {
            parallel_init(parallel_io[i], parallel_irq[i], parallel_hds[i]);
        }
    }

    for(i = 0; i < nb_nics; i++) {
        if (!nd_table[i].model)
            nd_table[i].model = "ne2k_pci";
	pci_nic_init(pci_bus, &nd_table[i]);
    }

    pci_cmd646_ide_init(pci_bus, bs_table, 1);
    kbd_init();
    floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
    nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
                         KERNEL_LOAD_ADDR, kernel_size,
                         kernel_cmdline,
                         INITRD_LOAD_ADDR, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0,
                         graphic_width, graphic_height, graphic_depth);

}

QEMUMachine sun4u_machine = {
    "sun4u",
    "Sun4u platform",
    sun4u_init,
};
Commit	Line	Data
3475187d FB	1	/*
	2	* QEMU Sun4u System Emulator
	3	*
	4	* Copyright (c) 2005 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
83469015	25	#include "m48t59.h"
3475187d	26
83469015 FB	27	#define KERNEL_LOAD_ADDR 0x00404000
	28	#define CMDLINE_ADDR 0x003ff000
	29	#define INITRD_LOAD_ADDR 0x00300000
b3783731	30	#define PROM_SIZE_MAX (256 * 1024)
83469015 FB	31	#define PROM_ADDR 0x1fff0000000ULL
	32	#define APB_SPECIAL_BASE 0x1fe00000000ULL
	33	#define APB_MEM_BASE 0x1ff00000000ULL
	34	#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
3475187d FB	35	#define PROM_FILENAMEB "proll-sparc64.bin"
3475187d FB	36	#define PROM_FILENAMEE "proll-sparc64.elf"
83469015	37	#define NVRAM_SIZE 0x2000
3475187d FB	38
	39	/* TSC handling */
	40
	41	uint64_t cpu_get_tsc()
	42	{
	43	return qemu_get_clock(vm_clock);
	44	}
	45
	46	int DMA_get_channel_mode (int nchan)
	47	{
	48	return 0;
	49	}
	50	int DMA_read_memory (int nchan, void *buf, int pos, int size)
	51	{
	52	return 0;
	53	}
	54	int DMA_write_memory (int nchan, void *buf, int pos, int size)
	55	{
	56	return 0;
	57	}
	58	void DMA_hold_DREQ (int nchan) {}
	59	void DMA_release_DREQ (int nchan) {}
	60	void DMA_schedule(int nchan) {}
	61	void DMA_run (void) {}
	62	void DMA_init (int high_page_enable) {}
	63	void DMA_register_channel (int nchan,
	64	DMA_transfer_handler transfer_handler,
	65	void *opaque)
	66	{
	67	}
	68
83469015 FB	69	/* NVRAM helpers */
83469015 FB	70	void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
3475187d	71	{
819385c5	72	m48t59_write(nvram, addr, value);
3475187d FB	73	}
3475187d FB	74
83469015	75	uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
3475187d	76	{
819385c5	77	return m48t59_read(nvram, addr);
3475187d FB	78	}
3475187d FB	79
83469015 FB	80	void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
83469015 FB	81	{
819385c5 FB	82	m48t59_write(nvram, addr, value >> 8);
819385c5 FB	83	m48t59_write(nvram, addr + 1, value & 0xFF);
83469015 FB	84	}
	85
	86	uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
	87	{
	88	uint16_t tmp;
	89
819385c5 FB	90	tmp = m48t59_read(nvram, addr) << 8;
819385c5 FB	91	tmp \|= m48t59_read(nvram, addr + 1);
83469015 FB	92
	93	return tmp;
	94	}
	95
	96	void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
	97	{
819385c5 FB	98	m48t59_write(nvram, addr, value >> 24);
	99	m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
	100	m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
	101	m48t59_write(nvram, addr + 3, value & 0xFF);
83469015 FB	102	}
	103
	104	uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
	105	{
	106	uint32_t tmp;
	107
819385c5 FB	108	tmp = m48t59_read(nvram, addr) << 24;
	109	tmp \|= m48t59_read(nvram, addr + 1) << 16;
	110	tmp \|= m48t59_read(nvram, addr + 2) << 8;
	111	tmp \|= m48t59_read(nvram, addr + 3);
83469015 FB	112
	113	return tmp;
	114	}
	115
	116	void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
3475187d FB	117	const unsigned char *str, uint32_t max)
3475187d FB	118	{
83469015	119	int i;
3475187d FB	120
3475187d FB	121	for (i = 0; i < max && str[i] != '\0'; i++) {
819385c5	122	m48t59_write(nvram, addr + i, str[i]);
3475187d	123	}
819385c5	124	m48t59_write(nvram, addr + max - 1, '\0');
3475187d FB	125	}
3475187d FB	126
83469015 FB	127	int NVRAM_get_string (m48t59_t nvram, uint8_t dst, uint16_t addr, int max)
	128	{
	129	int i;
	130
	131	memset(dst, 0, max);
	132	for (i = 0; i < max; i++) {
	133	dst[i] = NVRAM_get_byte(nvram, addr + i);
	134	if (dst[i] == '\0')
	135	break;
	136	}
	137
	138	return i;
	139	}
	140
	141	static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
	142	{
	143	uint16_t tmp;
	144	uint16_t pd, pd1, pd2;
	145
	146	tmp = prev >> 8;
	147	pd = prev ^ value;
	148	pd1 = pd & 0x000F;
	149	pd2 = ((pd >> 4) & 0x000F) ^ pd1;
	150	tmp ^= (pd1 << 3) \| (pd1 << 8);
	151	tmp ^= pd2 \| (pd2 << 7) \| (pd2 << 12);
	152
	153	return tmp;
	154	}
	155
	156	uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
	157	{
	158	uint32_t i;
	159	uint16_t crc = 0xFFFF;
	160	int odd;
	161
	162	odd = count & 1;
	163	count &= ~1;
	164	for (i = 0; i != count; i++) {
	165	crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
	166	}
	167	if (odd) {
	168	crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
	169	}
	170
	171	return crc;
	172	}
3475187d FB	173
	174	extern int nographic;
	175
83469015 FB	176	int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
	177	const unsigned char *arch,
	178	uint32_t RAM_size, int boot_device,
	179	uint32_t kernel_image, uint32_t kernel_size,
	180	const char *cmdline,
	181	uint32_t initrd_image, uint32_t initrd_size,
	182	uint32_t NVRAM_image,
	183	int width, int height, int depth)
	184	{
	185	uint16_t crc;
	186
	187	/* Set parameters for Open Hack'Ware BIOS */
	188	NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
	189	NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
	190	NVRAM_set_word(nvram, 0x14, NVRAM_size);
	191	NVRAM_set_string(nvram, 0x20, arch, 16);
	192	NVRAM_set_byte(nvram, 0x2f, nographic & 0xff);
	193	NVRAM_set_lword(nvram, 0x30, RAM_size);
	194	NVRAM_set_byte(nvram, 0x34, boot_device);
	195	NVRAM_set_lword(nvram, 0x38, kernel_image);
	196	NVRAM_set_lword(nvram, 0x3C, kernel_size);
3475187d	197	if (cmdline) {
83469015 FB	198	/* XXX: put the cmdline in NVRAM too ? */
	199	strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
	200	NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
	201	NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
	202	} else {
	203	NVRAM_set_lword(nvram, 0x40, 0);
	204	NVRAM_set_lword(nvram, 0x44, 0);
3475187d	205	}
83469015 FB	206	NVRAM_set_lword(nvram, 0x48, initrd_image);
	207	NVRAM_set_lword(nvram, 0x4C, initrd_size);
	208	NVRAM_set_lword(nvram, 0x50, NVRAM_image);
	209
	210	NVRAM_set_word(nvram, 0x54, width);
	211	NVRAM_set_word(nvram, 0x56, height);
	212	NVRAM_set_word(nvram, 0x58, depth);
	213	crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
	214	NVRAM_set_word(nvram, 0xFC, crc);
	215
	216	return 0;
3475187d FB	217	}
	218
	219	void pic_info()
	220	{
	221	}
	222
	223	void irq_info()
	224	{
	225	}
	226
	227	void pic_set_irq(int irq, int level)
	228	{
	229	}
	230
83469015	231	void pic_set_irq_new(void *opaque, int irq, int level)
3475187d FB	232	{
	233	}
	234
83469015	235	void qemu_system_powerdown(void)
3475187d FB	236	{
	237	}
	238
c68ea704 FB	239	static void main_cpu_reset(void *opaque)
	240	{
	241	CPUState *env = opaque;
	242	cpu_reset(env);
	243	}
	244
83469015 FB	245	static const int ide_iobase[2] = { 0x1f0, 0x170 };
	246	static const int ide_iobase2[2] = { 0x3f6, 0x376 };
	247	static const int ide_irq[2] = { 14, 15 };
3475187d	248
83469015 FB	249	static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
	250	static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
	251
	252	static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
	253	static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
	254
	255	static fdctrl_t *floppy_controller;
3475187d FB	256
	257	/* Sun4u hardware initialisation */
	258	static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
	259	DisplayState ds, const char *fd_filename, int snapshot,
	260	const char kernel_filename, const char kernel_cmdline,
	261	const char *initrd_filename)
	262	{
c68ea704	263	CPUState *env;
3475187d	264	char buf[1024];
83469015	265	m48t59_t *nvram;
3475187d FB	266	int ret, linux_boot;
3475187d FB	267	unsigned int i;
83469015 FB	268	long prom_offset, initrd_size, kernel_size;
83469015 FB	269	PCIBus *pci_bus;
3475187d FB	270
	271	linux_boot = (kernel_filename != NULL);
	272
c68ea704 FB	273	env = cpu_init();
	274	register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
	275	qemu_register_reset(main_cpu_reset, env);
	276
3475187d FB	277	/* allocate RAM */
	278	cpu_register_physical_memory(0, ram_size, 0);
	279
83469015	280	prom_offset = ram_size + vga_ram_size;
b3783731 FB	281	cpu_register_physical_memory(PROM_ADDR,
	282	(PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
	283	prom_offset \| IO_MEM_ROM);
3475187d FB	284
3475187d FB	285	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
9ee3c029	286	ret = load_elf(buf, 0, NULL);
3475187d FB	287	if (ret < 0) {
	288	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
	289	ret = load_image(buf, phys_ram_base + prom_offset);
	290	}
	291	if (ret < 0) {
	292	fprintf(stderr, "qemu: could not load prom '%s'\n",
	293	buf);
	294	exit(1);
	295	}
3475187d FB	296
3475187d FB	297	kernel_size = 0;
83469015	298	initrd_size = 0;
3475187d	299	if (linux_boot) {
b3783731	300	/* XXX: put correct offset */
9ee3c029	301	kernel_size = load_elf(kernel_filename, 0, NULL);
3475187d FB	302	if (kernel_size < 0)
	303	kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
	304	if (kernel_size < 0)
	305	kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
	306	if (kernel_size < 0) {
	307	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	308	kernel_filename);
	309	exit(1);
	310	}
	311
	312	/* load initrd */
3475187d FB	313	if (initrd_filename) {
	314	initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
	315	if (initrd_size < 0) {
	316	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	317	initrd_filename);
	318	exit(1);
	319	}
	320	}
	321	if (initrd_size > 0) {
	322	for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
	323	if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
	324	== 0x48647253) { // HdrS
	325	stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
	326	stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
	327	break;
	328	}
	329	}
	330	}
	331	}
83469015 FB	332	pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE);
	333	isa_mem_base = VGA_BASE;
	334	vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
	335	vga_ram_size, 0, 0);
	336	cpu_register_physical_memory(VGA_BASE, vga_ram_size, ram_size);
	337	//pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
	338
	339	for(i = 0; i < MAX_SERIAL_PORTS; i++) {
	340	if (serial_hds[i]) {
e5d13e2f FB	341	serial_init(&pic_set_irq_new, NULL,
e5d13e2f FB	342	serial_io[i], serial_irq[i], serial_hds[i]);
83469015 FB	343	}
	344	}
	345
	346	for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
	347	if (parallel_hds[i]) {
	348	parallel_init(parallel_io[i], parallel_irq[i], parallel_hds[i]);
	349	}
	350	}
	351
	352	for(i = 0; i < nb_nics; i++) {
a41b2ff2 PB	353	if (!nd_table[i].model)
	354	nd_table[i].model = "ne2k_pci";
	355	pci_nic_init(pci_bus, &nd_table[i]);
83469015 FB	356	}
	357
	358	pci_cmd646_ide_init(pci_bus, bs_table, 1);
	359	kbd_init();
	360	floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
819385c5	361	nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
83469015 FB	362	sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
	363	KERNEL_LOAD_ADDR, kernel_size,
	364	kernel_cmdline,
	365	INITRD_LOAD_ADDR, initrd_size,
	366	/* XXX: need an option to load a NVRAM image */
	367	0,
	368	graphic_width, graphic_height, graphic_depth);
	369
3475187d FB	370	}
	371
	372	QEMUMachine sun4u_machine = {
	373	"sun4u",
	374	"Sun4u platform",
	375	sun4u_init,
	376	};